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41655239 DT |
1 | STMicroelectronics STM32 Reset and Clock Controller |
2 | =================================================== | |
3 | ||
57bd63a4 | 4 | The RCC IP is both a reset and a clock controller. |
41655239 | 5 | |
57bd63a4 MC |
6 | Please refer to clock-bindings.txt for common clock controller binding usage. |
7 | Please also refer to reset.txt for common reset controller binding usage. | |
41655239 DT |
8 | |
9 | Required properties: | |
10 | - compatible: Should be "st,stm32f42xx-rcc" | |
11 | - reg: should be register base and length as documented in the | |
12 | datasheet | |
57bd63a4 | 13 | - #reset-cells: 1, see below |
41655239 DT |
14 | - #clock-cells: 2, device nodes should specify the clock in their "clocks" |
15 | property, containing a phandle to the clock device node, an index selecting | |
16 | between gated clocks and other clocks and an index specifying the clock to | |
17 | use. | |
18 | ||
19 | Example: | |
20 | ||
21 | rcc: rcc@40023800 { | |
57bd63a4 | 22 | #reset-cells = <1>; |
41655239 DT |
23 | #clock-cells = <2> |
24 | compatible = "st,stm32f42xx-rcc", "st,stm32-rcc"; | |
25 | reg = <0x40023800 0x400>; | |
26 | }; | |
27 | ||
28 | Specifying gated clocks | |
29 | ======================= | |
30 | ||
31 | The primary index must be set to 0. | |
32 | ||
33 | The secondary index is the bit number within the RCC register bank, starting | |
34 | from the first RCC clock enable register (RCC_AHB1ENR, address offset 0x30). | |
35 | ||
36 | It is calculated as: index = register_offset / 4 * 32 + bit_offset. | |
37 | Where bit_offset is the bit offset within the register (LSB is 0, MSB is 31). | |
38 | ||
57bd63a4 MC |
39 | To simplify the usage and to share bit definition with the reset and clock |
40 | drivers of the RCC IP, macros are available to generate the index in | |
41 | human-readble format. | |
42 | ||
43 | For STM32F4 series, the macro are available here: | |
44 | - include/dt-bindings/mfd/stm32f4-rcc.h | |
45 | ||
41655239 DT |
46 | Example: |
47 | ||
48 | /* Gated clock, AHB1 bit 0 (GPIOA) */ | |
49 | ... { | |
57bd63a4 | 50 | clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOA)> |
41655239 DT |
51 | }; |
52 | ||
53 | /* Gated clock, AHB2 bit 4 (CRYP) */ | |
54 | ... { | |
57bd63a4 | 55 | clocks = <&rcc 0 STM32F4_AHB2_CLOCK(CRYP)> |
41655239 DT |
56 | }; |
57 | ||
58 | Specifying other clocks | |
59 | ======================= | |
60 | ||
61 | The primary index must be set to 1. | |
62 | ||
63 | The secondary index is bound with the following magic numbers: | |
64 | ||
65 | 0 SYSTICK | |
66 | 1 FCLK | |
67 | ||
68 | Example: | |
69 | ||
70 | /* Misc clock, FCLK */ | |
71 | ... { | |
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72 | clocks = <&rcc 1 STM32F4_APB1_CLOCK(TIM2)> |
73 | }; | |
74 | ||
75 | ||
76 | Specifying softreset control of devices | |
77 | ======================================= | |
78 | ||
79 | Device nodes should specify the reset channel required in their "resets" | |
80 | property, containing a phandle to the reset device node and an index specifying | |
81 | which channel to use. | |
82 | The index is the bit number within the RCC registers bank, starting from RCC | |
83 | base address. | |
84 | It is calculated as: index = register_offset / 4 * 32 + bit_offset. | |
85 | Where bit_offset is the bit offset within the register. | |
86 | For example, for CRC reset: | |
87 | crc = AHB1RSTR_offset / 4 * 32 + CRCRST_bit_offset = 0x10 / 4 * 32 + 12 = 140 | |
88 | ||
89 | example: | |
90 | ||
91 | timer2 { | |
92 | resets = <&rcc STM32F4_APB1_RESET(TIM2)>; | |
41655239 | 93 | }; |