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21a454fd MR |
1 | Allwinner A10 Display Pipeline |
2 | ============================== | |
3 | ||
4 | The Allwinner A10 Display pipeline is composed of several components | |
5 | that are going to be documented below: | |
6 | ||
7 | TV Encoder | |
8 | ---------- | |
9 | ||
10 | The TV Encoder supports the composite and VGA output. It is one end of | |
11 | the pipeline. | |
12 | ||
13 | Required properties: | |
14 | - compatible: value should be "allwinner,sun4i-a10-tv-encoder". | |
15 | - reg: base address and size of memory-mapped region | |
16 | - clocks: the clocks driving the TV encoder | |
17 | - resets: phandle to the reset controller driving the encoder | |
18 | ||
19 | - ports: A ports node with endpoint definitions as defined in | |
20 | Documentation/devicetree/bindings/media/video-interfaces.txt. The | |
21 | first port should be the input endpoint. | |
22 | ||
23 | TCON | |
24 | ---- | |
25 | ||
26 | The TCON acts as a timing controller for RGB, LVDS and TV interfaces. | |
27 | ||
28 | Required properties: | |
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29 | - compatible: value must be either: |
30 | * allwinner,sun5i-a13-tcon | |
31 | * allwinner,sun8i-a33-tcon | |
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32 | - reg: base address and size of memory-mapped region |
33 | - interrupts: interrupt associated to this IP | |
34 | - clocks: phandles to the clocks feeding the TCON. Three are needed: | |
35 | - 'ahb': the interface clocks | |
36 | - 'tcon-ch0': The clock driving the TCON channel 0 | |
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37 | - resets: phandles to the reset controllers driving the encoder |
38 | - "lcd": the reset line for the TCON channel 0 | |
39 | ||
40 | - clock-names: the clock names mentioned above | |
41 | - reset-names: the reset names mentioned above | |
42 | - clock-output-names: Name of the pixel clock created | |
43 | ||
44 | - ports: A ports node with endpoint definitions as defined in | |
45 | Documentation/devicetree/bindings/media/video-interfaces.txt. The | |
46 | first port should be the input endpoint, the second one the output | |
47 | ||
48 | The output should have two endpoints. The first is the block | |
49 | connected to the TCON channel 0 (usually a panel or a bridge), the | |
50 | second the block connected to the TCON channel 1 (usually the TV | |
51 | encoder) | |
52 | ||
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53 | On the A13, there is one more clock required: |
54 | - 'tcon-ch1': The clock driving the TCON channel 1 | |
55 | ||
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56 | DRC |
57 | --- | |
58 | ||
59 | The DRC (Dynamic Range Controller), found in the latest Allwinner SoCs | |
60 | (A31, A23, A33), allows to dynamically adjust pixel | |
61 | brightness/contrast based on histogram measurements for LCD content | |
62 | adaptive backlight control. | |
63 | ||
64 | ||
65 | Required properties: | |
66 | - compatible: value must be one of: | |
67 | * allwinner,sun8i-a33-drc | |
68 | - reg: base address and size of the memory-mapped region. | |
69 | - interrupts: interrupt associated to this IP | |
70 | - clocks: phandles to the clocks feeding the DRC | |
71 | * ahb: the DRC interface clock | |
72 | * mod: the DRC module clock | |
73 | * ram: the DRC DRAM clock | |
74 | - clock-names: the clock names mentioned above | |
75 | - resets: phandles to the reset line driving the DRC | |
76 | ||
77 | - ports: A ports node with endpoint definitions as defined in | |
78 | Documentation/devicetree/bindings/media/video-interfaces.txt. The | |
79 | first port should be the input endpoints, the second one the outputs | |
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80 | |
81 | Display Engine Backend | |
82 | ---------------------- | |
83 | ||
84 | The display engine backend exposes layers and sprites to the | |
85 | system. | |
86 | ||
87 | Required properties: | |
88 | - compatible: value must be one of: | |
89 | * allwinner,sun5i-a13-display-backend | |
4a408f1f | 90 | * allwinner,sun8i-a33-display-backend |
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91 | - reg: base address and size of the memory-mapped region. |
92 | - clocks: phandles to the clocks feeding the frontend and backend | |
93 | * ahb: the backend interface clock | |
94 | * mod: the backend module clock | |
95 | * ram: the backend DRAM clock | |
96 | - clock-names: the clock names mentioned above | |
97 | - resets: phandles to the reset controllers driving the backend | |
98 | ||
99 | - ports: A ports node with endpoint definitions as defined in | |
100 | Documentation/devicetree/bindings/media/video-interfaces.txt. The | |
101 | first port should be the input endpoints, the second one the output | |
102 | ||
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103 | On the A33, some additional properties are required: |
104 | - reg needs to have an additional region corresponding to the SAT | |
105 | - reg-names need to be set, with "be" and "sat" | |
106 | - clocks and clock-names need to have a phandle to the SAT bus | |
107 | clocks, whose name will be "sat" | |
108 | - resets and reset-names need to have a phandle to the SAT bus | |
109 | resets, whose name will be "sat" | |
110 | ||
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111 | Display Engine Frontend |
112 | ----------------------- | |
113 | ||
114 | The display engine frontend does formats conversion, scaling, | |
115 | deinterlacing and color space conversion. | |
116 | ||
117 | Required properties: | |
118 | - compatible: value must be one of: | |
119 | * allwinner,sun5i-a13-display-frontend | |
4a408f1f | 120 | * allwinner,sun8i-a33-display-frontend |
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121 | - reg: base address and size of the memory-mapped region. |
122 | - interrupts: interrupt associated to this IP | |
123 | - clocks: phandles to the clocks feeding the frontend and backend | |
124 | * ahb: the backend interface clock | |
125 | * mod: the backend module clock | |
126 | * ram: the backend DRAM clock | |
127 | - clock-names: the clock names mentioned above | |
128 | - resets: phandles to the reset controllers driving the backend | |
129 | ||
130 | - ports: A ports node with endpoint definitions as defined in | |
131 | Documentation/devicetree/bindings/media/video-interfaces.txt. The | |
132 | first port should be the input endpoints, the second one the outputs | |
133 | ||
134 | ||
135 | Display Engine Pipeline | |
136 | ----------------------- | |
137 | ||
138 | The display engine pipeline (and its entry point, since it can be | |
139 | either directly the backend or the frontend) is represented as an | |
140 | extra node. | |
141 | ||
142 | Required properties: | |
143 | - compatible: value must be one of: | |
144 | * allwinner,sun5i-a13-display-engine | |
4a408f1f | 145 | * allwinner,sun8i-a33-display-engine |
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146 | |
147 | - allwinner,pipelines: list of phandle to the display engine | |
148 | frontends available. | |
149 | ||
150 | Example: | |
151 | ||
152 | panel: panel { | |
153 | compatible = "olimex,lcd-olinuxino-43-ts"; | |
154 | #address-cells = <1>; | |
155 | #size-cells = <0>; | |
156 | ||
157 | port { | |
158 | #address-cells = <1>; | |
159 | #size-cells = <0>; | |
160 | ||
161 | panel_input: endpoint { | |
162 | remote-endpoint = <&tcon0_out_panel>; | |
163 | }; | |
164 | }; | |
165 | }; | |
166 | ||
167 | tve0: tv-encoder@01c0a000 { | |
168 | compatible = "allwinner,sun4i-a10-tv-encoder"; | |
169 | reg = <0x01c0a000 0x1000>; | |
170 | clocks = <&ahb_gates 34>; | |
171 | resets = <&tcon_ch0_clk 0>; | |
172 | ||
173 | port { | |
174 | #address-cells = <1>; | |
175 | #size-cells = <0>; | |
176 | ||
177 | tve0_in_tcon0: endpoint@0 { | |
178 | reg = <0>; | |
179 | remote-endpoint = <&tcon0_out_tve0>; | |
180 | }; | |
181 | }; | |
182 | }; | |
183 | ||
184 | tcon0: lcd-controller@1c0c000 { | |
185 | compatible = "allwinner,sun5i-a13-tcon"; | |
186 | reg = <0x01c0c000 0x1000>; | |
187 | interrupts = <44>; | |
188 | resets = <&tcon_ch0_clk 1>; | |
189 | reset-names = "lcd"; | |
190 | clocks = <&ahb_gates 36>, | |
191 | <&tcon_ch0_clk>, | |
192 | <&tcon_ch1_clk>; | |
193 | clock-names = "ahb", | |
194 | "tcon-ch0", | |
195 | "tcon-ch1"; | |
196 | clock-output-names = "tcon-pixel-clock"; | |
197 | ||
198 | ports { | |
199 | #address-cells = <1>; | |
200 | #size-cells = <0>; | |
201 | ||
202 | tcon0_in: port@0 { | |
203 | #address-cells = <1>; | |
204 | #size-cells = <0>; | |
205 | reg = <0>; | |
206 | ||
207 | tcon0_in_be0: endpoint@0 { | |
208 | reg = <0>; | |
209 | remote-endpoint = <&be0_out_tcon0>; | |
210 | }; | |
211 | }; | |
212 | ||
213 | tcon0_out: port@1 { | |
214 | #address-cells = <1>; | |
215 | #size-cells = <0>; | |
216 | reg = <1>; | |
217 | ||
218 | tcon0_out_panel: endpoint@0 { | |
219 | reg = <0>; | |
220 | remote-endpoint = <&panel_input>; | |
221 | }; | |
222 | ||
223 | tcon0_out_tve0: endpoint@1 { | |
224 | reg = <1>; | |
225 | remote-endpoint = <&tve0_in_tcon0>; | |
226 | }; | |
227 | }; | |
228 | }; | |
229 | }; | |
230 | ||
231 | fe0: display-frontend@1e00000 { | |
232 | compatible = "allwinner,sun5i-a13-display-frontend"; | |
233 | reg = <0x01e00000 0x20000>; | |
234 | interrupts = <47>; | |
235 | clocks = <&ahb_gates 46>, <&de_fe_clk>, | |
236 | <&dram_gates 25>; | |
237 | clock-names = "ahb", "mod", | |
238 | "ram"; | |
239 | resets = <&de_fe_clk>; | |
240 | ||
241 | ports { | |
242 | #address-cells = <1>; | |
243 | #size-cells = <0>; | |
244 | ||
245 | fe0_out: port@1 { | |
246 | #address-cells = <1>; | |
247 | #size-cells = <0>; | |
248 | reg = <1>; | |
249 | ||
250 | fe0_out_be0: endpoint { | |
251 | remote-endpoint = <&be0_in_fe0>; | |
252 | }; | |
253 | }; | |
254 | }; | |
255 | }; | |
256 | ||
257 | be0: display-backend@1e60000 { | |
258 | compatible = "allwinner,sun5i-a13-display-backend"; | |
259 | reg = <0x01e60000 0x10000>; | |
260 | clocks = <&ahb_gates 44>, <&de_be_clk>, | |
261 | <&dram_gates 26>; | |
262 | clock-names = "ahb", "mod", | |
263 | "ram"; | |
264 | resets = <&de_be_clk>; | |
265 | ||
266 | ports { | |
267 | #address-cells = <1>; | |
268 | #size-cells = <0>; | |
269 | ||
270 | be0_in: port@0 { | |
271 | #address-cells = <1>; | |
272 | #size-cells = <0>; | |
273 | reg = <0>; | |
274 | ||
275 | be0_in_fe0: endpoint@0 { | |
276 | reg = <0>; | |
277 | remote-endpoint = <&fe0_out_be0>; | |
278 | }; | |
279 | }; | |
280 | ||
281 | be0_out: port@1 { | |
282 | #address-cells = <1>; | |
283 | #size-cells = <0>; | |
284 | reg = <1>; | |
285 | ||
286 | be0_out_tcon0: endpoint@0 { | |
287 | reg = <0>; | |
288 | remote-endpoint = <&tcon0_in_be0>; | |
289 | }; | |
290 | }; | |
291 | }; | |
292 | }; | |
293 | ||
294 | display-engine { | |
295 | compatible = "allwinner,sun5i-a13-display-engine"; | |
296 | allwinner,pipelines = <&fe0>; | |
297 | }; |