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1da177e4 LT |
1 | /* |
2 | * linux/arch/arm/boot/compressed/head.S | |
3 | * | |
4 | * Copyright (C) 1996-2002 Russell King | |
10c2df65 | 5 | * Copyright (C) 2004 Hyok S. Choi (MPU support) |
1da177e4 LT |
6 | * |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
1da177e4 LT |
11 | #include <linux/linkage.h> |
12 | ||
13 | /* | |
14 | * Debugging stuff | |
15 | * | |
16 | * Note that these macros must not contain any code which is not | |
17 | * 100% relocatable. Any attempt to do so will result in a crash. | |
18 | * Please select one of the following when turning on debugging. | |
19 | */ | |
20 | #ifdef DEBUG | |
5cd0c344 | 21 | |
5cd0c344 | 22 | #if defined(CONFIG_DEBUG_ICEDCC) |
7d95ded9 TL |
23 | |
24 | #ifdef CONFIG_CPU_V6 | |
25 | .macro loadsp, rb | |
26 | .endm | |
27 | .macro writeb, ch, rb | |
28 | mcr p14, 0, \ch, c0, c5, 0 | |
29 | .endm | |
c633c3cf JCPV |
30 | #elif defined(CONFIG_CPU_XSCALE) |
31 | .macro loadsp, rb | |
32 | .endm | |
33 | .macro writeb, ch, rb | |
34 | mcr p14, 0, \ch, c8, c0, 0 | |
35 | .endm | |
7d95ded9 | 36 | #else |
1da177e4 LT |
37 | .macro loadsp, rb |
38 | .endm | |
224b5be6 | 39 | .macro writeb, ch, rb |
41a9e680 | 40 | mcr p14, 0, \ch, c1, c0, 0 |
1da177e4 | 41 | .endm |
7d95ded9 TL |
42 | #endif |
43 | ||
5cd0c344 | 44 | #else |
224b5be6 | 45 | |
a09e64fb | 46 | #include <mach/debug-macro.S> |
224b5be6 | 47 | |
5cd0c344 RK |
48 | .macro writeb, ch, rb |
49 | senduart \ch, \rb | |
1da177e4 | 50 | .endm |
5cd0c344 | 51 | |
224b5be6 | 52 | #if defined(CONFIG_ARCH_SA1100) |
1da177e4 LT |
53 | .macro loadsp, rb |
54 | mov \rb, #0x80000000 @ physical base address | |
224b5be6 | 55 | #ifdef CONFIG_DEBUG_LL_SER3 |
1da177e4 | 56 | add \rb, \rb, #0x00050000 @ Ser3 |
224b5be6 | 57 | #else |
1da177e4 | 58 | add \rb, \rb, #0x00010000 @ Ser1 |
224b5be6 | 59 | #endif |
1da177e4 | 60 | .endm |
1da177e4 | 61 | #elif defined(CONFIG_ARCH_S3C2410) |
5cd0c344 | 62 | .macro loadsp, rb |
1da177e4 | 63 | mov \rb, #0x50000000 |
c7657846 | 64 | add \rb, \rb, #0x4000 * CONFIG_S3C_LOWLEVEL_UART_PORT |
1da177e4 | 65 | .endm |
1da177e4 | 66 | #else |
224b5be6 RK |
67 | .macro loadsp, rb |
68 | addruart \rb | |
69 | .endm | |
1da177e4 | 70 | #endif |
5cd0c344 | 71 | #endif |
1da177e4 LT |
72 | #endif |
73 | ||
74 | .macro kputc,val | |
75 | mov r0, \val | |
76 | bl putc | |
77 | .endm | |
78 | ||
79 | .macro kphex,val,len | |
80 | mov r0, \val | |
81 | mov r1, #\len | |
82 | bl phex | |
83 | .endm | |
84 | ||
85 | .macro debug_reloc_start | |
86 | #ifdef DEBUG | |
87 | kputc #'\n' | |
88 | kphex r6, 8 /* processor id */ | |
89 | kputc #':' | |
90 | kphex r7, 8 /* architecture id */ | |
f12d0d7c | 91 | #ifdef CONFIG_CPU_CP15 |
1da177e4 LT |
92 | kputc #':' |
93 | mrc p15, 0, r0, c1, c0 | |
94 | kphex r0, 8 /* control reg */ | |
f12d0d7c | 95 | #endif |
1da177e4 LT |
96 | kputc #'\n' |
97 | kphex r5, 8 /* decompressed kernel start */ | |
98 | kputc #'-' | |
f4619025 | 99 | kphex r9, 8 /* decompressed kernel end */ |
1da177e4 LT |
100 | kputc #'>' |
101 | kphex r4, 8 /* kernel execution address */ | |
102 | kputc #'\n' | |
103 | #endif | |
104 | .endm | |
105 | ||
106 | .macro debug_reloc_end | |
107 | #ifdef DEBUG | |
108 | kphex r5, 8 /* end of kernel */ | |
109 | kputc #'\n' | |
110 | mov r0, r4 | |
111 | bl memdump /* dump 256 bytes at start of kernel */ | |
112 | #endif | |
113 | .endm | |
114 | ||
115 | .section ".start", #alloc, #execinstr | |
116 | /* | |
117 | * sort out different calling conventions | |
118 | */ | |
119 | .align | |
120 | start: | |
121 | .type start,#function | |
122 | .rept 8 | |
123 | mov r0, r0 | |
124 | .endr | |
125 | ||
126 | b 1f | |
127 | .word 0x016f2818 @ Magic numbers to help the loader | |
128 | .word start @ absolute load/run zImage address | |
129 | .word _edata @ zImage end address | |
130 | 1: mov r7, r1 @ save architecture ID | |
f4619025 | 131 | mov r8, r2 @ save atags pointer |
1da177e4 LT |
132 | |
133 | #ifndef __ARM_ARCH_2__ | |
134 | /* | |
135 | * Booting from Angel - need to enter SVC mode and disable | |
136 | * FIQs/IRQs (numeric definitions from angel arm.h source). | |
137 | * We only do this if we were in user mode on entry. | |
138 | */ | |
139 | mrs r2, cpsr @ get current mode | |
140 | tst r2, #3 @ not user? | |
141 | bne not_angel | |
142 | mov r0, #0x17 @ angel_SWIreason_EnterSVC | |
143 | swi 0x123456 @ angel_SWI_ARM | |
144 | not_angel: | |
145 | mrs r2, cpsr @ turn off interrupts to | |
146 | orr r2, r2, #0xc0 @ prevent angel from running | |
147 | msr cpsr_c, r2 | |
148 | #else | |
149 | teqp pc, #0x0c000003 @ turn off interrupts | |
150 | #endif | |
151 | ||
152 | /* | |
153 | * Note that some cache flushing and other stuff may | |
154 | * be needed here - is there an Angel SWI call for this? | |
155 | */ | |
156 | ||
157 | /* | |
158 | * some architecture specific code can be inserted | |
f4619025 | 159 | * by the linker here, but it should preserve r7, r8, and r9. |
1da177e4 LT |
160 | */ |
161 | ||
162 | .text | |
163 | adr r0, LC0 | |
164 | ldmia r0, {r1, r2, r3, r4, r5, r6, ip, sp} | |
165 | subs r0, r0, r1 @ calculate the delta offset | |
166 | ||
167 | @ if delta is zero, we are | |
168 | beq not_relocated @ running at the address we | |
169 | @ were linked at. | |
170 | ||
171 | /* | |
172 | * We're running at a different address. We need to fix | |
173 | * up various pointers: | |
174 | * r5 - zImage base address | |
175 | * r6 - GOT start | |
176 | * ip - GOT end | |
177 | */ | |
178 | add r5, r5, r0 | |
179 | add r6, r6, r0 | |
180 | add ip, ip, r0 | |
181 | ||
182 | #ifndef CONFIG_ZBOOT_ROM | |
183 | /* | |
184 | * If we're running fully PIC === CONFIG_ZBOOT_ROM = n, | |
185 | * we need to fix up pointers into the BSS region. | |
186 | * r2 - BSS start | |
187 | * r3 - BSS end | |
188 | * sp - stack pointer | |
189 | */ | |
190 | add r2, r2, r0 | |
191 | add r3, r3, r0 | |
192 | add sp, sp, r0 | |
193 | ||
194 | /* | |
195 | * Relocate all entries in the GOT table. | |
196 | */ | |
197 | 1: ldr r1, [r6, #0] @ relocate entries in the GOT | |
198 | add r1, r1, r0 @ table. This fixes up the | |
199 | str r1, [r6], #4 @ C references. | |
200 | cmp r6, ip | |
201 | blo 1b | |
202 | #else | |
203 | ||
204 | /* | |
205 | * Relocate entries in the GOT table. We only relocate | |
206 | * the entries that are outside the (relocated) BSS region. | |
207 | */ | |
208 | 1: ldr r1, [r6, #0] @ relocate entries in the GOT | |
209 | cmp r1, r2 @ entry < bss_start || | |
210 | cmphs r3, r1 @ _end < entry | |
211 | addlo r1, r1, r0 @ table. This fixes up the | |
212 | str r1, [r6], #4 @ C references. | |
213 | cmp r6, ip | |
214 | blo 1b | |
215 | #endif | |
216 | ||
217 | not_relocated: mov r0, #0 | |
218 | 1: str r0, [r2], #4 @ clear bss | |
219 | str r0, [r2], #4 | |
220 | str r0, [r2], #4 | |
221 | str r0, [r2], #4 | |
222 | cmp r2, r3 | |
223 | blo 1b | |
224 | ||
225 | /* | |
226 | * The C runtime environment should now be setup | |
227 | * sufficiently. Turn the cache on, set up some | |
228 | * pointers, and start decompressing. | |
229 | */ | |
230 | bl cache_on | |
231 | ||
232 | mov r1, sp @ malloc space above stack | |
233 | add r2, sp, #0x10000 @ 64k max | |
234 | ||
235 | /* | |
236 | * Check to see if we will overwrite ourselves. | |
237 | * r4 = final kernel address | |
238 | * r5 = start of this image | |
239 | * r2 = end of malloc space (and therefore this image) | |
240 | * We basically want: | |
241 | * r4 >= r2 -> OK | |
242 | * r4 + image length <= r5 -> OK | |
243 | */ | |
244 | cmp r4, r2 | |
245 | bhs wont_overwrite | |
2552fc27 LB |
246 | sub r3, sp, r5 @ > compressed kernel size |
247 | add r0, r4, r3, lsl #2 @ allow for 4x expansion | |
1da177e4 LT |
248 | cmp r0, r5 |
249 | bls wont_overwrite | |
250 | ||
251 | mov r5, r2 @ decompress after malloc space | |
252 | mov r0, r5 | |
253 | mov r3, r7 | |
254 | bl decompress_kernel | |
255 | ||
c7341d43 | 256 | add r0, r0, #127 + 128 @ alignment + stack |
1da177e4 LT |
257 | bic r0, r0, #127 @ align the kernel length |
258 | /* | |
259 | * r0 = decompressed kernel length | |
260 | * r1-r3 = unused | |
261 | * r4 = kernel execution address | |
262 | * r5 = decompressed kernel start | |
263 | * r6 = processor ID | |
264 | * r7 = architecture ID | |
f4619025 RK |
265 | * r8 = atags pointer |
266 | * r9-r14 = corrupted | |
1da177e4 LT |
267 | */ |
268 | add r1, r5, r0 @ end of decompressed kernel | |
269 | adr r2, reloc_start | |
270 | ldr r3, LC1 | |
271 | add r3, r2, r3 | |
f4619025 RK |
272 | 1: ldmia r2!, {r9 - r14} @ copy relocation code |
273 | stmia r1!, {r9 - r14} | |
274 | ldmia r2!, {r9 - r14} | |
275 | stmia r1!, {r9 - r14} | |
1da177e4 LT |
276 | cmp r2, r3 |
277 | blo 1b | |
c7341d43 | 278 | add sp, r1, #128 @ relocate the stack |
1da177e4 LT |
279 | |
280 | bl cache_clean_flush | |
281 | add pc, r5, r0 @ call relocation code | |
282 | ||
283 | /* | |
284 | * We're not in danger of overwriting ourselves. Do this the simple way. | |
285 | * | |
286 | * r4 = kernel execution address | |
287 | * r7 = architecture ID | |
288 | */ | |
289 | wont_overwrite: mov r0, r4 | |
290 | mov r3, r7 | |
291 | bl decompress_kernel | |
292 | b call_kernel | |
293 | ||
88987ef9 | 294 | .align 2 |
1da177e4 LT |
295 | .type LC0, #object |
296 | LC0: .word LC0 @ r1 | |
297 | .word __bss_start @ r2 | |
298 | .word _end @ r3 | |
299 | .word zreladdr @ r4 | |
300 | .word _start @ r5 | |
301 | .word _got_start @ r6 | |
302 | .word _got_end @ ip | |
303 | .word user_stack+4096 @ sp | |
304 | LC1: .word reloc_end - reloc_start | |
305 | .size LC0, . - LC0 | |
306 | ||
307 | #ifdef CONFIG_ARCH_RPC | |
308 | .globl params | |
309 | params: ldr r0, =params_phys | |
310 | mov pc, lr | |
311 | .ltorg | |
312 | .align | |
313 | #endif | |
314 | ||
315 | /* | |
316 | * Turn on the cache. We need to setup some page tables so that we | |
317 | * can have both the I and D caches on. | |
318 | * | |
319 | * We place the page tables 16k down from the kernel execution address, | |
320 | * and we hope that nothing else is using it. If we're using it, we | |
321 | * will go pop! | |
322 | * | |
323 | * On entry, | |
324 | * r4 = kernel execution address | |
325 | * r6 = processor ID | |
326 | * r7 = architecture number | |
f4619025 RK |
327 | * r8 = atags pointer |
328 | * r9 = run-time address of "start" (???) | |
1da177e4 | 329 | * On exit, |
f4619025 | 330 | * r1, r2, r3, r9, r10, r12 corrupted |
1da177e4 | 331 | * This routine must preserve: |
f4619025 | 332 | * r4, r5, r6, r7, r8 |
1da177e4 LT |
333 | */ |
334 | .align 5 | |
335 | cache_on: mov r3, #8 @ cache_on function | |
336 | b call_cache_fn | |
337 | ||
10c2df65 HC |
338 | /* |
339 | * Initialize the highest priority protection region, PR7 | |
340 | * to cover all 32bit address and cacheable and bufferable. | |
341 | */ | |
342 | __armv4_mpu_cache_on: | |
343 | mov r0, #0x3f @ 4G, the whole | |
344 | mcr p15, 0, r0, c6, c7, 0 @ PR7 Area Setting | |
345 | mcr p15, 0, r0, c6, c7, 1 | |
346 | ||
347 | mov r0, #0x80 @ PR7 | |
348 | mcr p15, 0, r0, c2, c0, 0 @ D-cache on | |
349 | mcr p15, 0, r0, c2, c0, 1 @ I-cache on | |
350 | mcr p15, 0, r0, c3, c0, 0 @ write-buffer on | |
351 | ||
352 | mov r0, #0xc000 | |
353 | mcr p15, 0, r0, c5, c0, 1 @ I-access permission | |
354 | mcr p15, 0, r0, c5, c0, 0 @ D-access permission | |
355 | ||
356 | mov r0, #0 | |
357 | mcr p15, 0, r0, c7, c10, 4 @ drain write buffer | |
358 | mcr p15, 0, r0, c7, c5, 0 @ flush(inval) I-Cache | |
359 | mcr p15, 0, r0, c7, c6, 0 @ flush(inval) D-Cache | |
360 | mrc p15, 0, r0, c1, c0, 0 @ read control reg | |
361 | @ ...I .... ..D. WC.M | |
362 | orr r0, r0, #0x002d @ .... .... ..1. 11.1 | |
363 | orr r0, r0, #0x1000 @ ...1 .... .... .... | |
364 | ||
365 | mcr p15, 0, r0, c1, c0, 0 @ write control reg | |
366 | ||
367 | mov r0, #0 | |
368 | mcr p15, 0, r0, c7, c5, 0 @ flush(inval) I-Cache | |
369 | mcr p15, 0, r0, c7, c6, 0 @ flush(inval) D-Cache | |
370 | mov pc, lr | |
371 | ||
372 | __armv3_mpu_cache_on: | |
373 | mov r0, #0x3f @ 4G, the whole | |
374 | mcr p15, 0, r0, c6, c7, 0 @ PR7 Area Setting | |
375 | ||
376 | mov r0, #0x80 @ PR7 | |
377 | mcr p15, 0, r0, c2, c0, 0 @ cache on | |
378 | mcr p15, 0, r0, c3, c0, 0 @ write-buffer on | |
379 | ||
380 | mov r0, #0xc000 | |
381 | mcr p15, 0, r0, c5, c0, 0 @ access permission | |
382 | ||
383 | mov r0, #0 | |
384 | mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3 | |
385 | mrc p15, 0, r0, c1, c0, 0 @ read control reg | |
386 | @ .... .... .... WC.M | |
387 | orr r0, r0, #0x000d @ .... .... .... 11.1 | |
388 | mov r0, #0 | |
389 | mcr p15, 0, r0, c1, c0, 0 @ write control reg | |
390 | ||
391 | mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3 | |
392 | mov pc, lr | |
393 | ||
1da177e4 LT |
394 | __setup_mmu: sub r3, r4, #16384 @ Page directory size |
395 | bic r3, r3, #0xff @ Align the pointer | |
396 | bic r3, r3, #0x3f00 | |
397 | /* | |
398 | * Initialise the page tables, turning on the cacheable and bufferable | |
399 | * bits for the RAM area only. | |
400 | */ | |
401 | mov r0, r3 | |
f4619025 RK |
402 | mov r9, r0, lsr #18 |
403 | mov r9, r9, lsl #18 @ start of RAM | |
404 | add r10, r9, #0x10000000 @ a reasonable RAM size | |
1da177e4 LT |
405 | mov r1, #0x12 |
406 | orr r1, r1, #3 << 10 | |
407 | add r2, r3, #16384 | |
265d5e48 | 408 | 1: cmp r1, r9 @ if virt > start of RAM |
1da177e4 | 409 | orrhs r1, r1, #0x0c @ set cacheable, bufferable |
f4619025 | 410 | cmp r1, r10 @ if virt > end of RAM |
1da177e4 LT |
411 | bichs r1, r1, #0x0c @ clear cacheable, bufferable |
412 | str r1, [r0], #4 @ 1:1 mapping | |
413 | add r1, r1, #1048576 | |
414 | teq r0, r2 | |
415 | bne 1b | |
416 | /* | |
417 | * If ever we are running from Flash, then we surely want the cache | |
418 | * to be enabled also for our execution instance... We map 2MB of it | |
419 | * so there is no map overlap problem for up to 1 MB compressed kernel. | |
420 | * If the execution is in RAM then we would only be duplicating the above. | |
421 | */ | |
422 | mov r1, #0x1e | |
423 | orr r1, r1, #3 << 10 | |
424 | mov r2, pc, lsr #20 | |
425 | orr r1, r1, r2, lsl #20 | |
426 | add r0, r3, r2, lsl #2 | |
427 | str r1, [r0], #4 | |
428 | add r1, r1, #1048576 | |
429 | str r1, [r0] | |
430 | mov pc, lr | |
93ed3970 | 431 | ENDPROC(__setup_mmu) |
1da177e4 | 432 | |
c76b6b41 | 433 | __armv4_mmu_cache_on: |
1da177e4 LT |
434 | mov r12, lr |
435 | bl __setup_mmu | |
436 | mov r0, #0 | |
437 | mcr p15, 0, r0, c7, c10, 4 @ drain write buffer | |
438 | mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs | |
439 | mrc p15, 0, r0, c1, c0, 0 @ read control reg | |
440 | orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement | |
441 | orr r0, r0, #0x0030 | |
26584853 CM |
442 | #ifdef CONFIG_CPU_ENDIAN_BE8 |
443 | orr r0, r0, #1 << 25 @ big-endian page tables | |
444 | #endif | |
c76b6b41 | 445 | bl __common_mmu_cache_on |
1da177e4 LT |
446 | mov r0, #0 |
447 | mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs | |
448 | mov pc, r12 | |
449 | ||
7d09e854 CM |
450 | __armv7_mmu_cache_on: |
451 | mov r12, lr | |
452 | mrc p15, 0, r11, c0, c1, 4 @ read ID_MMFR0 | |
453 | tst r11, #0xf @ VMSA | |
454 | blne __setup_mmu | |
455 | mov r0, #0 | |
456 | mcr p15, 0, r0, c7, c10, 4 @ drain write buffer | |
457 | tst r11, #0xf @ VMSA | |
458 | mcrne p15, 0, r0, c8, c7, 0 @ flush I,D TLBs | |
459 | mrc p15, 0, r0, c1, c0, 0 @ read control reg | |
460 | orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement | |
461 | orr r0, r0, #0x003c @ write buffer | |
26584853 CM |
462 | #ifdef CONFIG_CPU_ENDIAN_BE8 |
463 | orr r0, r0, #1 << 25 @ big-endian page tables | |
464 | #endif | |
7d09e854 CM |
465 | orrne r0, r0, #1 @ MMU enabled |
466 | movne r1, #-1 | |
467 | mcrne p15, 0, r3, c2, c0, 0 @ load page table pointer | |
468 | mcrne p15, 0, r1, c3, c0, 0 @ load domain access control | |
469 | mcr p15, 0, r0, c1, c0, 0 @ load control register | |
470 | mrc p15, 0, r0, c1, c0, 0 @ and read it back | |
471 | mov r0, #0 | |
472 | mcr p15, 0, r0, c7, c5, 4 @ ISB | |
473 | mov pc, r12 | |
474 | ||
28853ac8 PZ |
475 | __fa526_cache_on: |
476 | mov r12, lr | |
477 | bl __setup_mmu | |
478 | mov r0, #0 | |
479 | mcr p15, 0, r0, c7, c7, 0 @ Invalidate whole cache | |
480 | mcr p15, 0, r0, c7, c10, 4 @ drain write buffer | |
481 | mcr p15, 0, r0, c8, c7, 0 @ flush UTLB | |
482 | mrc p15, 0, r0, c1, c0, 0 @ read control reg | |
483 | orr r0, r0, #0x1000 @ I-cache enable | |
484 | bl __common_mmu_cache_on | |
485 | mov r0, #0 | |
486 | mcr p15, 0, r0, c8, c7, 0 @ flush UTLB | |
487 | mov pc, r12 | |
488 | ||
c76b6b41 | 489 | __arm6_mmu_cache_on: |
1da177e4 LT |
490 | mov r12, lr |
491 | bl __setup_mmu | |
492 | mov r0, #0 | |
493 | mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3 | |
494 | mcr p15, 0, r0, c5, c0, 0 @ invalidate whole TLB v3 | |
495 | mov r0, #0x30 | |
c76b6b41 | 496 | bl __common_mmu_cache_on |
1da177e4 LT |
497 | mov r0, #0 |
498 | mcr p15, 0, r0, c5, c0, 0 @ invalidate whole TLB v3 | |
499 | mov pc, r12 | |
500 | ||
c76b6b41 | 501 | __common_mmu_cache_on: |
1da177e4 LT |
502 | #ifndef DEBUG |
503 | orr r0, r0, #0x000d @ Write buffer, mmu | |
504 | #endif | |
505 | mov r1, #-1 | |
506 | mcr p15, 0, r3, c2, c0, 0 @ load page table pointer | |
507 | mcr p15, 0, r1, c3, c0, 0 @ load domain access control | |
2dc7667b NP |
508 | b 1f |
509 | .align 5 @ cache line aligned | |
510 | 1: mcr p15, 0, r0, c1, c0, 0 @ load control register | |
511 | mrc p15, 0, r0, c1, c0, 0 @ and read it back to | |
512 | sub pc, lr, r0, lsr #32 @ properly flush pipeline | |
1da177e4 LT |
513 | |
514 | /* | |
515 | * All code following this line is relocatable. It is relocated by | |
516 | * the above code to the end of the decompressed kernel image and | |
517 | * executed there. During this time, we have no stacks. | |
518 | * | |
519 | * r0 = decompressed kernel length | |
520 | * r1-r3 = unused | |
521 | * r4 = kernel execution address | |
522 | * r5 = decompressed kernel start | |
523 | * r6 = processor ID | |
524 | * r7 = architecture ID | |
f4619025 RK |
525 | * r8 = atags pointer |
526 | * r9-r14 = corrupted | |
1da177e4 LT |
527 | */ |
528 | .align 5 | |
f4619025 | 529 | reloc_start: add r9, r5, r0 |
c7341d43 | 530 | sub r9, r9, #128 @ do not copy the stack |
1da177e4 LT |
531 | debug_reloc_start |
532 | mov r1, r4 | |
533 | 1: | |
534 | .rept 4 | |
f4619025 RK |
535 | ldmia r5!, {r0, r2, r3, r10 - r14} @ relocate kernel |
536 | stmia r1!, {r0, r2, r3, r10 - r14} | |
1da177e4 LT |
537 | .endr |
538 | ||
f4619025 | 539 | cmp r5, r9 |
1da177e4 | 540 | blo 1b |
c7341d43 | 541 | add sp, r1, #128 @ relocate the stack |
1da177e4 LT |
542 | debug_reloc_end |
543 | ||
544 | call_kernel: bl cache_clean_flush | |
545 | bl cache_off | |
f4619025 | 546 | mov r0, #0 @ must be zero |
1da177e4 | 547 | mov r1, r7 @ restore architecture number |
f4619025 | 548 | mov r2, r8 @ restore atags pointer |
1da177e4 LT |
549 | mov pc, r4 @ call kernel |
550 | ||
551 | /* | |
552 | * Here follow the relocatable cache support functions for the | |
553 | * various processors. This is a generic hook for locating an | |
554 | * entry and jumping to an instruction at the specified offset | |
555 | * from the start of the block. Please note this is all position | |
556 | * independent code. | |
557 | * | |
558 | * r1 = corrupted | |
559 | * r2 = corrupted | |
560 | * r3 = block offset | |
561 | * r6 = corrupted | |
562 | * r12 = corrupted | |
563 | */ | |
564 | ||
565 | call_cache_fn: adr r12, proc_types | |
f12d0d7c | 566 | #ifdef CONFIG_CPU_CP15 |
1da177e4 | 567 | mrc p15, 0, r6, c0, c0 @ get processor ID |
f12d0d7c HC |
568 | #else |
569 | ldr r6, =CONFIG_PROCESSOR_ID | |
570 | #endif | |
1da177e4 LT |
571 | 1: ldr r1, [r12, #0] @ get value |
572 | ldr r2, [r12, #4] @ get mask | |
573 | eor r1, r1, r6 @ (real ^ match) | |
574 | tst r1, r2 @ & mask | |
575 | addeq pc, r12, r3 @ call cache function | |
576 | add r12, r12, #4*5 | |
577 | b 1b | |
578 | ||
579 | /* | |
580 | * Table for cache operations. This is basically: | |
581 | * - CPU ID match | |
582 | * - CPU ID mask | |
583 | * - 'cache on' method instruction | |
584 | * - 'cache off' method instruction | |
585 | * - 'cache flush' method instruction | |
586 | * | |
587 | * We match an entry using: ((real_id ^ match) & mask) == 0 | |
588 | * | |
589 | * Writethrough caches generally only need 'on' and 'off' | |
590 | * methods. Writeback caches _must_ have the flush method | |
591 | * defined. | |
592 | */ | |
88987ef9 | 593 | .align 2 |
1da177e4 LT |
594 | .type proc_types,#object |
595 | proc_types: | |
596 | .word 0x41560600 @ ARM6/610 | |
597 | .word 0xffffffe0 | |
c76b6b41 HC |
598 | b __arm6_mmu_cache_off @ works, but slow |
599 | b __arm6_mmu_cache_off | |
1da177e4 | 600 | mov pc, lr |
c76b6b41 HC |
601 | @ b __arm6_mmu_cache_on @ untested |
602 | @ b __arm6_mmu_cache_off | |
603 | @ b __armv3_mmu_cache_flush | |
1da177e4 LT |
604 | |
605 | .word 0x00000000 @ old ARM ID | |
606 | .word 0x0000f000 | |
607 | mov pc, lr | |
608 | mov pc, lr | |
609 | mov pc, lr | |
610 | ||
611 | .word 0x41007000 @ ARM7/710 | |
612 | .word 0xfff8fe00 | |
c76b6b41 HC |
613 | b __arm7_mmu_cache_off |
614 | b __arm7_mmu_cache_off | |
1da177e4 LT |
615 | mov pc, lr |
616 | ||
617 | .word 0x41807200 @ ARM720T (writethrough) | |
618 | .word 0xffffff00 | |
c76b6b41 HC |
619 | b __armv4_mmu_cache_on |
620 | b __armv4_mmu_cache_off | |
1da177e4 LT |
621 | mov pc, lr |
622 | ||
10c2df65 HC |
623 | .word 0x41007400 @ ARM74x |
624 | .word 0xff00ff00 | |
625 | b __armv3_mpu_cache_on | |
626 | b __armv3_mpu_cache_off | |
627 | b __armv3_mpu_cache_flush | |
628 | ||
629 | .word 0x41009400 @ ARM94x | |
630 | .word 0xff00ff00 | |
631 | b __armv4_mpu_cache_on | |
632 | b __armv4_mpu_cache_off | |
633 | b __armv4_mpu_cache_flush | |
634 | ||
1da177e4 LT |
635 | .word 0x00007000 @ ARM7 IDs |
636 | .word 0x0000f000 | |
637 | mov pc, lr | |
638 | mov pc, lr | |
639 | mov pc, lr | |
640 | ||
641 | @ Everything from here on will be the new ID system. | |
642 | ||
643 | .word 0x4401a100 @ sa110 / sa1100 | |
644 | .word 0xffffffe0 | |
c76b6b41 HC |
645 | b __armv4_mmu_cache_on |
646 | b __armv4_mmu_cache_off | |
647 | b __armv4_mmu_cache_flush | |
1da177e4 LT |
648 | |
649 | .word 0x6901b110 @ sa1110 | |
650 | .word 0xfffffff0 | |
c76b6b41 HC |
651 | b __armv4_mmu_cache_on |
652 | b __armv4_mmu_cache_off | |
653 | b __armv4_mmu_cache_flush | |
1da177e4 | 654 | |
59c7bcd4 EM |
655 | .word 0x56056930 |
656 | .word 0xff0ffff0 @ PXA935 | |
657 | b __armv4_mmu_cache_on | |
49cbe786 EM |
658 | b __armv4_mmu_cache_off |
659 | b __armv4_mmu_cache_flush | |
660 | ||
661 | .word 0x56158000 @ PXA168 | |
662 | .word 0xfffff000 | |
663 | b __armv4_mmu_cache_on | |
664 | b __armv4_mmu_cache_off | |
665 | b __armv5tej_mmu_cache_flush | |
666 | ||
667 | .word 0x56056930 | |
668 | .word 0xff0ffff0 @ PXA935 | |
669 | b __armv4_mmu_cache_on | |
c76b6b41 HC |
670 | b __armv4_mmu_cache_off |
671 | b __armv4_mmu_cache_flush | |
1da177e4 | 672 | |
2e2023fe NP |
673 | .word 0x56050000 @ Feroceon |
674 | .word 0xff0f0000 | |
3ebb5a2b NP |
675 | b __armv4_mmu_cache_on |
676 | b __armv4_mmu_cache_off | |
677 | b __armv5tej_mmu_cache_flush | |
678 | ||
5587931c JS |
679 | #ifdef CONFIG_CPU_FEROCEON_OLD_ID |
680 | /* this conflicts with the standard ARMv5TE entry */ | |
681 | .long 0x41009260 @ Old Feroceon | |
682 | .long 0xff00fff0 | |
683 | b __armv4_mmu_cache_on | |
684 | b __armv4_mmu_cache_off | |
685 | b __armv5tej_mmu_cache_flush | |
686 | #endif | |
687 | ||
28853ac8 PZ |
688 | .word 0x66015261 @ FA526 |
689 | .word 0xff01fff1 | |
690 | b __fa526_cache_on | |
691 | b __armv4_mmu_cache_off | |
692 | b __fa526_cache_flush | |
693 | ||
1da177e4 LT |
694 | @ These match on the architecture ID |
695 | ||
696 | .word 0x00020000 @ ARMv4T | |
697 | .word 0x000f0000 | |
c76b6b41 HC |
698 | b __armv4_mmu_cache_on |
699 | b __armv4_mmu_cache_off | |
700 | b __armv4_mmu_cache_flush | |
1da177e4 LT |
701 | |
702 | .word 0x00050000 @ ARMv5TE | |
703 | .word 0x000f0000 | |
c76b6b41 HC |
704 | b __armv4_mmu_cache_on |
705 | b __armv4_mmu_cache_off | |
706 | b __armv4_mmu_cache_flush | |
1da177e4 LT |
707 | |
708 | .word 0x00060000 @ ARMv5TEJ | |
709 | .word 0x000f0000 | |
c76b6b41 HC |
710 | b __armv4_mmu_cache_on |
711 | b __armv4_mmu_cache_off | |
15754bf9 | 712 | b __armv5tej_mmu_cache_flush |
1da177e4 | 713 | |
45a7b9cf | 714 | .word 0x0007b000 @ ARMv6 |
7d09e854 | 715 | .word 0x000ff000 |
c76b6b41 HC |
716 | b __armv4_mmu_cache_on |
717 | b __armv4_mmu_cache_off | |
718 | b __armv6_mmu_cache_flush | |
1da177e4 | 719 | |
7d09e854 CM |
720 | .word 0x000f0000 @ new CPU Id |
721 | .word 0x000f0000 | |
722 | b __armv7_mmu_cache_on | |
723 | b __armv7_mmu_cache_off | |
724 | b __armv7_mmu_cache_flush | |
725 | ||
1da177e4 LT |
726 | .word 0 @ unrecognised type |
727 | .word 0 | |
728 | mov pc, lr | |
729 | mov pc, lr | |
730 | mov pc, lr | |
731 | ||
732 | .size proc_types, . - proc_types | |
733 | ||
734 | /* | |
735 | * Turn off the Cache and MMU. ARMv3 does not support | |
736 | * reading the control register, but ARMv4 does. | |
737 | * | |
738 | * On entry, r6 = processor ID | |
739 | * On exit, r0, r1, r2, r3, r12 corrupted | |
740 | * This routine must preserve: r4, r6, r7 | |
741 | */ | |
742 | .align 5 | |
743 | cache_off: mov r3, #12 @ cache_off function | |
744 | b call_cache_fn | |
745 | ||
10c2df65 HC |
746 | __armv4_mpu_cache_off: |
747 | mrc p15, 0, r0, c1, c0 | |
748 | bic r0, r0, #0x000d | |
749 | mcr p15, 0, r0, c1, c0 @ turn MPU and cache off | |
750 | mov r0, #0 | |
751 | mcr p15, 0, r0, c7, c10, 4 @ drain write buffer | |
752 | mcr p15, 0, r0, c7, c6, 0 @ flush D-Cache | |
753 | mcr p15, 0, r0, c7, c5, 0 @ flush I-Cache | |
754 | mov pc, lr | |
755 | ||
756 | __armv3_mpu_cache_off: | |
757 | mrc p15, 0, r0, c1, c0 | |
758 | bic r0, r0, #0x000d | |
759 | mcr p15, 0, r0, c1, c0, 0 @ turn MPU and cache off | |
760 | mov r0, #0 | |
761 | mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3 | |
762 | mov pc, lr | |
763 | ||
c76b6b41 | 764 | __armv4_mmu_cache_off: |
1da177e4 LT |
765 | mrc p15, 0, r0, c1, c0 |
766 | bic r0, r0, #0x000d | |
767 | mcr p15, 0, r0, c1, c0 @ turn MMU and cache off | |
768 | mov r0, #0 | |
769 | mcr p15, 0, r0, c7, c7 @ invalidate whole cache v4 | |
770 | mcr p15, 0, r0, c8, c7 @ invalidate whole TLB v4 | |
771 | mov pc, lr | |
772 | ||
7d09e854 CM |
773 | __armv7_mmu_cache_off: |
774 | mrc p15, 0, r0, c1, c0 | |
775 | bic r0, r0, #0x000d | |
776 | mcr p15, 0, r0, c1, c0 @ turn MMU and cache off | |
777 | mov r12, lr | |
778 | bl __armv7_mmu_cache_flush | |
779 | mov r0, #0 | |
780 | mcr p15, 0, r0, c8, c7, 0 @ invalidate whole TLB | |
c30c2f99 CM |
781 | mcr p15, 0, r0, c7, c5, 6 @ invalidate BTC |
782 | mcr p15, 0, r0, c7, c10, 4 @ DSB | |
783 | mcr p15, 0, r0, c7, c5, 4 @ ISB | |
7d09e854 CM |
784 | mov pc, r12 |
785 | ||
c76b6b41 | 786 | __arm6_mmu_cache_off: |
1da177e4 | 787 | mov r0, #0x00000030 @ ARM6 control reg. |
c76b6b41 | 788 | b __armv3_mmu_cache_off |
1da177e4 | 789 | |
c76b6b41 | 790 | __arm7_mmu_cache_off: |
1da177e4 | 791 | mov r0, #0x00000070 @ ARM7 control reg. |
c76b6b41 | 792 | b __armv3_mmu_cache_off |
1da177e4 | 793 | |
c76b6b41 | 794 | __armv3_mmu_cache_off: |
1da177e4 LT |
795 | mcr p15, 0, r0, c1, c0, 0 @ turn MMU and cache off |
796 | mov r0, #0 | |
797 | mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3 | |
798 | mcr p15, 0, r0, c5, c0, 0 @ invalidate whole TLB v3 | |
799 | mov pc, lr | |
800 | ||
801 | /* | |
802 | * Clean and flush the cache to maintain consistency. | |
803 | * | |
804 | * On entry, | |
805 | * r6 = processor ID | |
806 | * On exit, | |
807 | * r1, r2, r3, r11, r12 corrupted | |
808 | * This routine must preserve: | |
809 | * r0, r4, r5, r6, r7 | |
810 | */ | |
811 | .align 5 | |
812 | cache_clean_flush: | |
813 | mov r3, #16 | |
814 | b call_cache_fn | |
815 | ||
10c2df65 HC |
816 | __armv4_mpu_cache_flush: |
817 | mov r2, #1 | |
818 | mov r3, #0 | |
819 | mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache | |
820 | mov r1, #7 << 5 @ 8 segments | |
821 | 1: orr r3, r1, #63 << 26 @ 64 entries | |
822 | 2: mcr p15, 0, r3, c7, c14, 2 @ clean & invalidate D index | |
823 | subs r3, r3, #1 << 26 | |
824 | bcs 2b @ entries 63 to 0 | |
825 | subs r1, r1, #1 << 5 | |
826 | bcs 1b @ segments 7 to 0 | |
827 | ||
828 | teq r2, #0 | |
829 | mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache | |
830 | mcr p15, 0, ip, c7, c10, 4 @ drain WB | |
831 | mov pc, lr | |
832 | ||
28853ac8 PZ |
833 | __fa526_cache_flush: |
834 | mov r1, #0 | |
835 | mcr p15, 0, r1, c7, c14, 0 @ clean and invalidate D cache | |
836 | mcr p15, 0, r1, c7, c5, 0 @ flush I cache | |
837 | mcr p15, 0, r1, c7, c10, 4 @ drain WB | |
838 | mov pc, lr | |
10c2df65 | 839 | |
c76b6b41 | 840 | __armv6_mmu_cache_flush: |
1da177e4 LT |
841 | mov r1, #0 |
842 | mcr p15, 0, r1, c7, c14, 0 @ clean+invalidate D | |
843 | mcr p15, 0, r1, c7, c5, 0 @ invalidate I+BTB | |
844 | mcr p15, 0, r1, c7, c15, 0 @ clean+invalidate unified | |
845 | mcr p15, 0, r1, c7, c10, 4 @ drain WB | |
846 | mov pc, lr | |
847 | ||
7d09e854 CM |
848 | __armv7_mmu_cache_flush: |
849 | mrc p15, 0, r10, c0, c1, 5 @ read ID_MMFR1 | |
850 | tst r10, #0xf << 16 @ hierarchical cache (ARMv7) | |
7d09e854 | 851 | mov r10, #0 |
c30c2f99 | 852 | beq hierarchical |
7d09e854 CM |
853 | mcr p15, 0, r10, c7, c14, 0 @ clean+invalidate D |
854 | b iflush | |
855 | hierarchical: | |
c30c2f99 CM |
856 | mcr p15, 0, r10, c7, c10, 5 @ DMB |
857 | stmfd sp!, {r0-r5, r7, r9, r11} | |
7d09e854 CM |
858 | mrc p15, 1, r0, c0, c0, 1 @ read clidr |
859 | ands r3, r0, #0x7000000 @ extract loc from clidr | |
860 | mov r3, r3, lsr #23 @ left align loc bit field | |
861 | beq finished @ if loc is 0, then no need to clean | |
862 | mov r10, #0 @ start clean at cache level 0 | |
863 | loop1: | |
864 | add r2, r10, r10, lsr #1 @ work out 3x current cache level | |
865 | mov r1, r0, lsr r2 @ extract cache type bits from clidr | |
866 | and r1, r1, #7 @ mask of the bits for current cache only | |
867 | cmp r1, #2 @ see what cache we have at this level | |
868 | blt skip @ skip if no cache, or just i-cache | |
869 | mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr | |
870 | mcr p15, 0, r10, c7, c5, 4 @ isb to sych the new cssr&csidr | |
871 | mrc p15, 1, r1, c0, c0, 0 @ read the new csidr | |
872 | and r2, r1, #7 @ extract the length of the cache lines | |
873 | add r2, r2, #4 @ add 4 (line length offset) | |
874 | ldr r4, =0x3ff | |
875 | ands r4, r4, r1, lsr #3 @ find maximum number on the way size | |
000b5025 | 876 | clz r5, r4 @ find bit position of way size increment |
7d09e854 CM |
877 | ldr r7, =0x7fff |
878 | ands r7, r7, r1, lsr #13 @ extract max number of the index size | |
879 | loop2: | |
880 | mov r9, r4 @ create working copy of max way size | |
881 | loop3: | |
882 | orr r11, r10, r9, lsl r5 @ factor way and cache number into r11 | |
883 | orr r11, r11, r7, lsl r2 @ factor index number into r11 | |
884 | mcr p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way | |
885 | subs r9, r9, #1 @ decrement the way | |
886 | bge loop3 | |
887 | subs r7, r7, #1 @ decrement the index | |
888 | bge loop2 | |
889 | skip: | |
890 | add r10, r10, #2 @ increment cache number | |
891 | cmp r3, r10 | |
892 | bgt loop1 | |
893 | finished: | |
c30c2f99 | 894 | ldmfd sp!, {r0-r5, r7, r9, r11} |
7d09e854 CM |
895 | mov r10, #0 @ swith back to cache level 0 |
896 | mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr | |
7d09e854 | 897 | iflush: |
c30c2f99 | 898 | mcr p15, 0, r10, c7, c10, 4 @ DSB |
7d09e854 | 899 | mcr p15, 0, r10, c7, c5, 0 @ invalidate I+BTB |
c30c2f99 CM |
900 | mcr p15, 0, r10, c7, c10, 4 @ DSB |
901 | mcr p15, 0, r10, c7, c5, 4 @ ISB | |
7d09e854 CM |
902 | mov pc, lr |
903 | ||
15754bf9 NP |
904 | __armv5tej_mmu_cache_flush: |
905 | 1: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate D cache | |
906 | bne 1b | |
907 | mcr p15, 0, r0, c7, c5, 0 @ flush I cache | |
908 | mcr p15, 0, r0, c7, c10, 4 @ drain WB | |
909 | mov pc, lr | |
910 | ||
c76b6b41 | 911 | __armv4_mmu_cache_flush: |
1da177e4 LT |
912 | mov r2, #64*1024 @ default: 32K dcache size (*2) |
913 | mov r11, #32 @ default: 32 byte line size | |
914 | mrc p15, 0, r3, c0, c0, 1 @ read cache type | |
915 | teq r3, r6 @ cache ID register present? | |
916 | beq no_cache_id | |
917 | mov r1, r3, lsr #18 | |
918 | and r1, r1, #7 | |
919 | mov r2, #1024 | |
920 | mov r2, r2, lsl r1 @ base dcache size *2 | |
921 | tst r3, #1 << 14 @ test M bit | |
922 | addne r2, r2, r2, lsr #1 @ +1/2 size if M == 1 | |
923 | mov r3, r3, lsr #12 | |
924 | and r3, r3, #3 | |
925 | mov r11, #8 | |
926 | mov r11, r11, lsl r3 @ cache line size in bytes | |
927 | no_cache_id: | |
928 | bic r1, pc, #63 @ align to longest cache line | |
929 | add r2, r1, r2 | |
930 | 1: ldr r3, [r1], r11 @ s/w flush D cache | |
931 | teq r1, r2 | |
932 | bne 1b | |
933 | ||
934 | mcr p15, 0, r1, c7, c5, 0 @ flush I cache | |
935 | mcr p15, 0, r1, c7, c6, 0 @ flush D cache | |
936 | mcr p15, 0, r1, c7, c10, 4 @ drain WB | |
937 | mov pc, lr | |
938 | ||
c76b6b41 | 939 | __armv3_mmu_cache_flush: |
10c2df65 | 940 | __armv3_mpu_cache_flush: |
1da177e4 LT |
941 | mov r1, #0 |
942 | mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3 | |
943 | mov pc, lr | |
944 | ||
945 | /* | |
946 | * Various debugging routines for printing hex characters and | |
947 | * memory, which again must be relocatable. | |
948 | */ | |
949 | #ifdef DEBUG | |
88987ef9 | 950 | .align 2 |
1da177e4 LT |
951 | .type phexbuf,#object |
952 | phexbuf: .space 12 | |
953 | .size phexbuf, . - phexbuf | |
954 | ||
955 | phex: adr r3, phexbuf | |
956 | mov r2, #0 | |
957 | strb r2, [r3, r1] | |
958 | 1: subs r1, r1, #1 | |
959 | movmi r0, r3 | |
960 | bmi puts | |
961 | and r2, r0, #15 | |
962 | mov r0, r0, lsr #4 | |
963 | cmp r2, #10 | |
964 | addge r2, r2, #7 | |
965 | add r2, r2, #'0' | |
966 | strb r2, [r3, r1] | |
967 | b 1b | |
968 | ||
969 | puts: loadsp r3 | |
970 | 1: ldrb r2, [r0], #1 | |
971 | teq r2, #0 | |
972 | moveq pc, lr | |
5cd0c344 | 973 | 2: writeb r2, r3 |
1da177e4 LT |
974 | mov r1, #0x00020000 |
975 | 3: subs r1, r1, #1 | |
976 | bne 3b | |
977 | teq r2, #'\n' | |
978 | moveq r2, #'\r' | |
979 | beq 2b | |
980 | teq r0, #0 | |
981 | bne 1b | |
982 | mov pc, lr | |
983 | putc: | |
984 | mov r2, r0 | |
985 | mov r0, #0 | |
986 | loadsp r3 | |
987 | b 2b | |
988 | ||
989 | memdump: mov r12, r0 | |
990 | mov r10, lr | |
991 | mov r11, #0 | |
992 | 2: mov r0, r11, lsl #2 | |
993 | add r0, r0, r12 | |
994 | mov r1, #8 | |
995 | bl phex | |
996 | mov r0, #':' | |
997 | bl putc | |
998 | 1: mov r0, #' ' | |
999 | bl putc | |
1000 | ldr r0, [r12, r11, lsl #2] | |
1001 | mov r1, #8 | |
1002 | bl phex | |
1003 | and r0, r11, #7 | |
1004 | teq r0, #3 | |
1005 | moveq r0, #' ' | |
1006 | bleq putc | |
1007 | and r0, r11, #7 | |
1008 | add r11, r11, #1 | |
1009 | teq r0, #7 | |
1010 | bne 1b | |
1011 | mov r0, #'\n' | |
1012 | bl putc | |
1013 | cmp r11, #64 | |
1014 | blt 2b | |
1015 | mov pc, r10 | |
1016 | #endif | |
1017 | ||
92c83ff1 | 1018 | .ltorg |
1da177e4 LT |
1019 | reloc_end: |
1020 | ||
1021 | .align | |
1022 | .section ".stack", "w" | |
1023 | user_stack: .space 4096 |