Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * linux/arch/arm/boot/compressed/head.S | |
3 | * | |
4 | * Copyright (C) 1996-2002 Russell King | |
10c2df65 | 5 | * Copyright (C) 2004 Hyok S. Choi (MPU support) |
1da177e4 LT |
6 | * |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
1da177e4 | 11 | #include <linux/linkage.h> |
424e5994 | 12 | #include <asm/assembler.h> |
1da177e4 | 13 | |
da94a829 | 14 | .arch armv7-a |
1da177e4 LT |
15 | /* |
16 | * Debugging stuff | |
17 | * | |
18 | * Note that these macros must not contain any code which is not | |
19 | * 100% relocatable. Any attempt to do so will result in a crash. | |
20 | * Please select one of the following when turning on debugging. | |
21 | */ | |
22 | #ifdef DEBUG | |
5cd0c344 | 23 | |
5cd0c344 | 24 | #if defined(CONFIG_DEBUG_ICEDCC) |
7d95ded9 | 25 | |
dfad549d | 26 | #if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K) || defined(CONFIG_CPU_V7) |
4e6d488a | 27 | .macro loadsp, rb, tmp |
7d95ded9 TL |
28 | .endm |
29 | .macro writeb, ch, rb | |
30 | mcr p14, 0, \ch, c0, c5, 0 | |
31 | .endm | |
c633c3cf | 32 | #elif defined(CONFIG_CPU_XSCALE) |
4e6d488a | 33 | .macro loadsp, rb, tmp |
c633c3cf JCPV |
34 | .endm |
35 | .macro writeb, ch, rb | |
36 | mcr p14, 0, \ch, c8, c0, 0 | |
37 | .endm | |
7d95ded9 | 38 | #else |
4e6d488a | 39 | .macro loadsp, rb, tmp |
1da177e4 | 40 | .endm |
224b5be6 | 41 | .macro writeb, ch, rb |
41a9e680 | 42 | mcr p14, 0, \ch, c1, c0, 0 |
1da177e4 | 43 | .endm |
7d95ded9 TL |
44 | #endif |
45 | ||
5cd0c344 | 46 | #else |
224b5be6 | 47 | |
4beba08b | 48 | #include CONFIG_DEBUG_LL_INCLUDE |
224b5be6 | 49 | |
5cd0c344 RK |
50 | .macro writeb, ch, rb |
51 | senduart \ch, \rb | |
1da177e4 | 52 | .endm |
5cd0c344 | 53 | |
224b5be6 | 54 | #if defined(CONFIG_ARCH_SA1100) |
4e6d488a | 55 | .macro loadsp, rb, tmp |
1da177e4 | 56 | mov \rb, #0x80000000 @ physical base address |
224b5be6 | 57 | #ifdef CONFIG_DEBUG_LL_SER3 |
1da177e4 | 58 | add \rb, \rb, #0x00050000 @ Ser3 |
224b5be6 | 59 | #else |
1da177e4 | 60 | add \rb, \rb, #0x00010000 @ Ser1 |
224b5be6 | 61 | #endif |
1da177e4 | 62 | .endm |
1da177e4 | 63 | #else |
4e6d488a TL |
64 | .macro loadsp, rb, tmp |
65 | addruart \rb, \tmp | |
224b5be6 | 66 | .endm |
1da177e4 | 67 | #endif |
5cd0c344 | 68 | #endif |
1da177e4 LT |
69 | #endif |
70 | ||
71 | .macro kputc,val | |
72 | mov r0, \val | |
73 | bl putc | |
74 | .endm | |
75 | ||
76 | .macro kphex,val,len | |
77 | mov r0, \val | |
78 | mov r1, #\len | |
79 | bl phex | |
80 | .endm | |
81 | ||
82 | .macro debug_reloc_start | |
83 | #ifdef DEBUG | |
84 | kputc #'\n' | |
85 | kphex r6, 8 /* processor id */ | |
86 | kputc #':' | |
87 | kphex r7, 8 /* architecture id */ | |
f12d0d7c | 88 | #ifdef CONFIG_CPU_CP15 |
1da177e4 LT |
89 | kputc #':' |
90 | mrc p15, 0, r0, c1, c0 | |
91 | kphex r0, 8 /* control reg */ | |
f12d0d7c | 92 | #endif |
1da177e4 LT |
93 | kputc #'\n' |
94 | kphex r5, 8 /* decompressed kernel start */ | |
95 | kputc #'-' | |
f4619025 | 96 | kphex r9, 8 /* decompressed kernel end */ |
1da177e4 LT |
97 | kputc #'>' |
98 | kphex r4, 8 /* kernel execution address */ | |
99 | kputc #'\n' | |
100 | #endif | |
101 | .endm | |
102 | ||
103 | .macro debug_reloc_end | |
104 | #ifdef DEBUG | |
105 | kphex r5, 8 /* end of kernel */ | |
106 | kputc #'\n' | |
107 | mov r0, r4 | |
108 | bl memdump /* dump 256 bytes at start of kernel */ | |
109 | #endif | |
110 | .endm | |
111 | ||
112 | .section ".start", #alloc, #execinstr | |
113 | /* | |
114 | * sort out different calling conventions | |
115 | */ | |
116 | .align | |
26e5ca93 | 117 | .arm @ Always enter in ARM state |
1da177e4 LT |
118 | start: |
119 | .type start,#function | |
b11fe388 | 120 | .rept 7 |
1da177e4 LT |
121 | mov r0, r0 |
122 | .endr | |
b11fe388 NP |
123 | ARM( mov r0, r0 ) |
124 | ARM( b 1f ) | |
125 | THUMB( adr r12, BSYM(1f) ) | |
126 | THUMB( bx r12 ) | |
1da177e4 | 127 | |
33656d56 NP |
128 | .word _magic_sig @ Magic numbers to help the loader |
129 | .word _magic_start @ absolute load/run zImage address | |
130 | .word _magic_end @ zImage end address | |
131 | ||
26e5ca93 | 132 | THUMB( .thumb ) |
424e5994 | 133 | 1: |
97bcb0fe | 134 | ARM_BE8( setend be ) @ go BE8 if compiled for BE8 |
424e5994 DM |
135 | mrs r9, cpsr |
136 | #ifdef CONFIG_ARM_VIRT_EXT | |
137 | bl __hyp_stub_install @ get into SVC mode, reversibly | |
138 | #endif | |
139 | mov r7, r1 @ save architecture ID | |
f4619025 | 140 | mov r8, r2 @ save atags pointer |
1da177e4 | 141 | |
1da177e4 LT |
142 | /* |
143 | * Booting from Angel - need to enter SVC mode and disable | |
144 | * FIQs/IRQs (numeric definitions from angel arm.h source). | |
145 | * We only do this if we were in user mode on entry. | |
146 | */ | |
147 | mrs r2, cpsr @ get current mode | |
148 | tst r2, #3 @ not user? | |
149 | bne not_angel | |
150 | mov r0, #0x17 @ angel_SWIreason_EnterSVC | |
0e056f20 CM |
151 | ARM( swi 0x123456 ) @ angel_SWI_ARM |
152 | THUMB( svc 0xab ) @ angel_SWI_THUMB | |
1da177e4 | 153 | not_angel: |
424e5994 DM |
154 | safe_svcmode_maskall r0 |
155 | msr spsr_cxsf, r9 @ Save the CPU boot mode in | |
156 | @ SPSR | |
1da177e4 LT |
157 | /* |
158 | * Note that some cache flushing and other stuff may | |
159 | * be needed here - is there an Angel SWI call for this? | |
160 | */ | |
161 | ||
162 | /* | |
163 | * some architecture specific code can be inserted | |
f4619025 | 164 | * by the linker here, but it should preserve r7, r8, and r9. |
1da177e4 LT |
165 | */ |
166 | ||
167 | .text | |
6d7d0ae5 | 168 | |
e69edc79 EM |
169 | #ifdef CONFIG_AUTO_ZRELADDR |
170 | @ determine final kernel image address | |
bfa64c4a DM |
171 | mov r4, pc |
172 | and r4, r4, #0xf8000000 | |
e69edc79 EM |
173 | add r4, r4, #TEXT_OFFSET |
174 | #else | |
9e84ed63 | 175 | ldr r4, =zreladdr |
e69edc79 | 176 | #endif |
1da177e4 | 177 | |
2874865c NP |
178 | /* |
179 | * Set up a page table only if it won't overwrite ourself. | |
180 | * That means r4 < pc && r4 - 16k page directory > &_end. | |
181 | * Given that r4 > &_end is most unfrequent, we add a rough | |
182 | * additional 1MB of room for a possible appended DTB. | |
183 | */ | |
184 | mov r0, pc | |
185 | cmp r0, r4 | |
186 | ldrcc r0, LC0+32 | |
187 | addcc r0, r0, pc | |
188 | cmpcc r4, r0 | |
189 | orrcc r4, r4, #1 @ remember we skipped cache_on | |
190 | blcs cache_on | |
6d7d0ae5 NP |
191 | |
192 | restart: adr r0, LC0 | |
34cc1a8f | 193 | ldmia r0, {r1, r2, r3, r6, r10, r11, r12} |
adcc2591 | 194 | ldr sp, [r0, #28] |
6d7d0ae5 NP |
195 | |
196 | /* | |
197 | * We might be running at a different address. We need | |
198 | * to fix up various pointers. | |
199 | */ | |
200 | sub r0, r0, r1 @ calculate the delta offset | |
6d7d0ae5 | 201 | add r6, r6, r0 @ _edata |
34cc1a8f NP |
202 | add r10, r10, r0 @ inflated kernel size location |
203 | ||
204 | /* | |
205 | * The kernel build system appends the size of the | |
206 | * decompressed kernel at the end of the compressed data | |
207 | * in little-endian form. | |
208 | */ | |
209 | ldrb r9, [r10, #0] | |
210 | ldrb lr, [r10, #1] | |
211 | orr r9, r9, lr, lsl #8 | |
212 | ldrb lr, [r10, #2] | |
213 | ldrb r10, [r10, #3] | |
214 | orr r9, r9, lr, lsl #16 | |
215 | orr r9, r9, r10, lsl #24 | |
1da177e4 | 216 | |
6d7d0ae5 NP |
217 | #ifndef CONFIG_ZBOOT_ROM |
218 | /* malloc space is above the relocated stack (64k max) */ | |
219 | add sp, sp, r0 | |
220 | add r10, sp, #0x10000 | |
221 | #else | |
1da177e4 | 222 | /* |
6d7d0ae5 NP |
223 | * With ZBOOT_ROM the bss/stack is non relocatable, |
224 | * but someone could still run this code from RAM, | |
225 | * in which case our reference is _edata. | |
1da177e4 | 226 | */ |
6d7d0ae5 NP |
227 | mov r10, r6 |
228 | #endif | |
229 | ||
e2a6a3aa JB |
230 | mov r5, #0 @ init dtb size to 0 |
231 | #ifdef CONFIG_ARM_APPENDED_DTB | |
232 | /* | |
233 | * r0 = delta | |
234 | * r2 = BSS start | |
235 | * r3 = BSS end | |
2874865c | 236 | * r4 = final kernel address (possibly with LSB set) |
e2a6a3aa JB |
237 | * r5 = appended dtb size (still unknown) |
238 | * r6 = _edata | |
239 | * r7 = architecture ID | |
240 | * r8 = atags/device tree pointer | |
241 | * r9 = size of decompressed image | |
242 | * r10 = end of this image, including bss/stack/malloc space if non XIP | |
243 | * r11 = GOT start | |
244 | * r12 = GOT end | |
245 | * sp = stack pointer | |
246 | * | |
247 | * if there are device trees (dtb) appended to zImage, advance r10 so that the | |
248 | * dtb data will get relocated along with the kernel if necessary. | |
249 | */ | |
250 | ||
251 | ldr lr, [r6, #0] | |
252 | #ifndef __ARMEB__ | |
253 | ldr r1, =0xedfe0dd0 @ sig is 0xd00dfeed big endian | |
254 | #else | |
255 | ldr r1, =0xd00dfeed | |
256 | #endif | |
257 | cmp lr, r1 | |
258 | bne dtb_check_done @ not found | |
259 | ||
b90b9a38 NP |
260 | #ifdef CONFIG_ARM_ATAG_DTB_COMPAT |
261 | /* | |
262 | * OK... Let's do some funky business here. | |
263 | * If we do have a DTB appended to zImage, and we do have | |
264 | * an ATAG list around, we want the later to be translated | |
265 | * and folded into the former here. To be on the safe side, | |
266 | * let's temporarily move the stack away into the malloc | |
267 | * area. No GOT fixup has occurred yet, but none of the | |
268 | * code we're about to call uses any global variable. | |
269 | */ | |
270 | add sp, sp, #0x10000 | |
271 | stmfd sp!, {r0-r3, ip, lr} | |
272 | mov r0, r8 | |
273 | mov r1, r6 | |
274 | sub r2, sp, r6 | |
275 | bl atags_to_fdt | |
276 | ||
277 | /* | |
278 | * If returned value is 1, there is no ATAG at the location | |
279 | * pointed by r8. Try the typical 0x100 offset from start | |
280 | * of RAM and hope for the best. | |
281 | */ | |
282 | cmp r0, #1 | |
531a6a94 | 283 | sub r0, r4, #TEXT_OFFSET |
2874865c | 284 | bic r0, r0, #1 |
531a6a94 | 285 | add r0, r0, #0x100 |
b90b9a38 NP |
286 | mov r1, r6 |
287 | sub r2, sp, r6 | |
9c5fd9e8 | 288 | bleq atags_to_fdt |
b90b9a38 NP |
289 | |
290 | ldmfd sp!, {r0-r3, ip, lr} | |
291 | sub sp, sp, #0x10000 | |
292 | #endif | |
293 | ||
e2a6a3aa JB |
294 | mov r8, r6 @ use the appended device tree |
295 | ||
5ffb04f6 NP |
296 | /* |
297 | * Make sure that the DTB doesn't end up in the final | |
298 | * kernel's .bss area. To do so, we adjust the decompressed | |
299 | * kernel size to compensate if that .bss size is larger | |
300 | * than the relocated code. | |
301 | */ | |
302 | ldr r5, =_kernel_bss_size | |
303 | adr r1, wont_overwrite | |
304 | sub r1, r6, r1 | |
305 | subs r1, r5, r1 | |
306 | addhi r9, r9, r1 | |
307 | ||
e2a6a3aa JB |
308 | /* Get the dtb's size */ |
309 | ldr r5, [r6, #4] | |
310 | #ifndef __ARMEB__ | |
311 | /* convert r5 (dtb size) to little endian */ | |
312 | eor r1, r5, r5, ror #16 | |
313 | bic r1, r1, #0x00ff0000 | |
314 | mov r5, r5, ror #8 | |
315 | eor r5, r5, r1, lsr #8 | |
316 | #endif | |
317 | ||
318 | /* preserve 64-bit alignment */ | |
319 | add r5, r5, #7 | |
320 | bic r5, r5, #7 | |
321 | ||
322 | /* relocate some pointers past the appended dtb */ | |
323 | add r6, r6, r5 | |
324 | add r10, r10, r5 | |
325 | add sp, sp, r5 | |
326 | dtb_check_done: | |
327 | #endif | |
328 | ||
6d7d0ae5 NP |
329 | /* |
330 | * Check to see if we will overwrite ourselves. | |
2874865c | 331 | * r4 = final kernel address (possibly with LSB set) |
6d7d0ae5 NP |
332 | * r9 = size of decompressed image |
333 | * r10 = end of this image, including bss/stack/malloc space if non XIP | |
334 | * We basically want: | |
ea9df3b1 | 335 | * r4 - 16k page directory >= r10 -> OK |
5ffb04f6 | 336 | * r4 + image length <= address of wont_overwrite -> OK |
2874865c | 337 | * Note: the possible LSB in r4 is harmless here. |
6d7d0ae5 | 338 | */ |
ea9df3b1 | 339 | add r10, r10, #16384 |
6d7d0ae5 NP |
340 | cmp r4, r10 |
341 | bhs wont_overwrite | |
342 | add r10, r4, r9 | |
5ffb04f6 NP |
343 | adr r9, wont_overwrite |
344 | cmp r10, r9 | |
6d7d0ae5 NP |
345 | bls wont_overwrite |
346 | ||
347 | /* | |
348 | * Relocate ourselves past the end of the decompressed kernel. | |
6d7d0ae5 NP |
349 | * r6 = _edata |
350 | * r10 = end of the decompressed kernel | |
351 | * Because we always copy ahead, we need to do it from the end and go | |
352 | * backward in case the source and destination overlap. | |
353 | */ | |
adcc2591 NP |
354 | /* |
355 | * Bump to the next 256-byte boundary with the size of | |
356 | * the relocation code added. This avoids overwriting | |
357 | * ourself when the offset is small. | |
358 | */ | |
359 | add r10, r10, #((reloc_code_end - restart + 256) & ~255) | |
6d7d0ae5 NP |
360 | bic r10, r10, #255 |
361 | ||
adcc2591 NP |
362 | /* Get start of code we want to copy and align it down. */ |
363 | adr r5, restart | |
364 | bic r5, r5, #31 | |
365 | ||
424e5994 DM |
366 | /* Relocate the hyp vector base if necessary */ |
367 | #ifdef CONFIG_ARM_VIRT_EXT | |
368 | mrs r0, spsr | |
369 | and r0, r0, #MODE_MASK | |
370 | cmp r0, #HYP_MODE | |
371 | bne 1f | |
372 | ||
373 | bl __hyp_get_vectors | |
374 | sub r0, r0, r5 | |
375 | add r0, r0, r10 | |
376 | bl __hyp_set_vectors | |
377 | 1: | |
378 | #endif | |
379 | ||
6d7d0ae5 NP |
380 | sub r9, r6, r5 @ size to copy |
381 | add r9, r9, #31 @ rounded up to a multiple | |
382 | bic r9, r9, #31 @ ... of 32 bytes | |
383 | add r6, r9, r5 | |
384 | add r9, r9, r10 | |
385 | ||
386 | 1: ldmdb r6!, {r0 - r3, r10 - r12, lr} | |
387 | cmp r6, r5 | |
388 | stmdb r9!, {r0 - r3, r10 - r12, lr} | |
389 | bhi 1b | |
390 | ||
391 | /* Preserve offset to relocated code. */ | |
392 | sub r6, r9, r6 | |
393 | ||
7c2527f0 TL |
394 | #ifndef CONFIG_ZBOOT_ROM |
395 | /* cache_clean_flush may use the stack, so relocate it */ | |
396 | add sp, sp, r6 | |
397 | #endif | |
398 | ||
2874865c NP |
399 | tst r4, #1 |
400 | bleq cache_clean_flush | |
6d7d0ae5 NP |
401 | |
402 | adr r0, BSYM(restart) | |
403 | add r0, r0, r6 | |
404 | mov pc, r0 | |
405 | ||
406 | wont_overwrite: | |
407 | /* | |
408 | * If delta is zero, we are running at the address we were linked at. | |
409 | * r0 = delta | |
410 | * r2 = BSS start | |
411 | * r3 = BSS end | |
2874865c | 412 | * r4 = kernel execution address (possibly with LSB set) |
e2a6a3aa | 413 | * r5 = appended dtb size (0 if not present) |
6d7d0ae5 NP |
414 | * r7 = architecture ID |
415 | * r8 = atags pointer | |
416 | * r11 = GOT start | |
417 | * r12 = GOT end | |
418 | * sp = stack pointer | |
419 | */ | |
e2a6a3aa | 420 | orrs r1, r0, r5 |
6d7d0ae5 | 421 | beq not_relocated |
e2a6a3aa | 422 | |
98e12b5a | 423 | add r11, r11, r0 |
6d7d0ae5 | 424 | add r12, r12, r0 |
1da177e4 LT |
425 | |
426 | #ifndef CONFIG_ZBOOT_ROM | |
427 | /* | |
428 | * If we're running fully PIC === CONFIG_ZBOOT_ROM = n, | |
429 | * we need to fix up pointers into the BSS region. | |
6d7d0ae5 | 430 | * Note that the stack pointer has already been fixed up. |
1da177e4 LT |
431 | */ |
432 | add r2, r2, r0 | |
433 | add r3, r3, r0 | |
1da177e4 LT |
434 | |
435 | /* | |
436 | * Relocate all entries in the GOT table. | |
e2a6a3aa | 437 | * Bump bss entries to _edata + dtb size |
1da177e4 | 438 | */ |
98e12b5a | 439 | 1: ldr r1, [r11, #0] @ relocate entries in the GOT |
e2a6a3aa JB |
440 | add r1, r1, r0 @ This fixes up C references |
441 | cmp r1, r2 @ if entry >= bss_start && | |
442 | cmphs r3, r1 @ bss_end > entry | |
443 | addhi r1, r1, r5 @ entry += dtb size | |
444 | str r1, [r11], #4 @ next entry | |
6d7d0ae5 | 445 | cmp r11, r12 |
1da177e4 | 446 | blo 1b |
e2a6a3aa JB |
447 | |
448 | /* bump our bss pointers too */ | |
449 | add r2, r2, r5 | |
450 | add r3, r3, r5 | |
451 | ||
1da177e4 LT |
452 | #else |
453 | ||
454 | /* | |
455 | * Relocate entries in the GOT table. We only relocate | |
456 | * the entries that are outside the (relocated) BSS region. | |
457 | */ | |
98e12b5a | 458 | 1: ldr r1, [r11, #0] @ relocate entries in the GOT |
1da177e4 LT |
459 | cmp r1, r2 @ entry < bss_start || |
460 | cmphs r3, r1 @ _end < entry | |
461 | addlo r1, r1, r0 @ table. This fixes up the | |
98e12b5a | 462 | str r1, [r11], #4 @ C references. |
6d7d0ae5 | 463 | cmp r11, r12 |
1da177e4 LT |
464 | blo 1b |
465 | #endif | |
466 | ||
467 | not_relocated: mov r0, #0 | |
468 | 1: str r0, [r2], #4 @ clear bss | |
469 | str r0, [r2], #4 | |
470 | str r0, [r2], #4 | |
471 | str r0, [r2], #4 | |
472 | cmp r2, r3 | |
473 | blo 1b | |
474 | ||
2874865c NP |
475 | /* |
476 | * Did we skip the cache setup earlier? | |
477 | * That is indicated by the LSB in r4. | |
478 | * Do it now if so. | |
479 | */ | |
480 | tst r4, #1 | |
481 | bic r4, r4, #1 | |
482 | blne cache_on | |
483 | ||
1da177e4 | 484 | /* |
6d7d0ae5 NP |
485 | * The C runtime environment should now be setup sufficiently. |
486 | * Set up some pointers, and start decompressing. | |
487 | * r4 = kernel execution address | |
488 | * r7 = architecture ID | |
489 | * r8 = atags pointer | |
1da177e4 | 490 | */ |
6d7d0ae5 NP |
491 | mov r0, r4 |
492 | mov r1, sp @ malloc space above stack | |
493 | add r2, sp, #0x10000 @ 64k max | |
1da177e4 LT |
494 | mov r3, r7 |
495 | bl decompress_kernel | |
1da177e4 | 496 | bl cache_clean_flush |
6d7d0ae5 | 497 | bl cache_off |
6d7d0ae5 NP |
498 | mov r1, r7 @ restore architecture number |
499 | mov r2, r8 @ restore atags pointer | |
424e5994 DM |
500 | |
501 | #ifdef CONFIG_ARM_VIRT_EXT | |
502 | mrs r0, spsr @ Get saved CPU boot mode | |
503 | and r0, r0, #MODE_MASK | |
504 | cmp r0, #HYP_MODE @ if not booted in HYP mode... | |
505 | bne __enter_kernel @ boot kernel directly | |
506 | ||
507 | adr r12, .L__hyp_reentry_vectors_offset | |
508 | ldr r0, [r12] | |
509 | add r0, r0, r12 | |
510 | ||
511 | bl __hyp_set_vectors | |
512 | __HVC(0) @ otherwise bounce to hyp mode | |
513 | ||
514 | b . @ should never be reached | |
515 | ||
516 | .align 2 | |
517 | .L__hyp_reentry_vectors_offset: .long __hyp_reentry_vectors - . | |
518 | #else | |
519 | b __enter_kernel | |
520 | #endif | |
1da177e4 | 521 | |
88987ef9 | 522 | .align 2 |
1da177e4 LT |
523 | .type LC0, #object |
524 | LC0: .word LC0 @ r1 | |
525 | .word __bss_start @ r2 | |
526 | .word _end @ r3 | |
6d7d0ae5 | 527 | .word _edata @ r6 |
34cc1a8f | 528 | .word input_data_end - 4 @ r10 (inflated size location) |
98e12b5a | 529 | .word _got_start @ r11 |
1da177e4 | 530 | .word _got_end @ ip |
8d7e4cc2 | 531 | .word .L_user_stack_end @ sp |
2874865c | 532 | .word _end - restart + 16384 + 1024*1024 |
1da177e4 LT |
533 | .size LC0, . - LC0 |
534 | ||
535 | #ifdef CONFIG_ARCH_RPC | |
536 | .globl params | |
db7b2b4b | 537 | params: ldr r0, =0x10000100 @ params_phys for RPC |
1da177e4 LT |
538 | mov pc, lr |
539 | .ltorg | |
540 | .align | |
541 | #endif | |
542 | ||
543 | /* | |
544 | * Turn on the cache. We need to setup some page tables so that we | |
545 | * can have both the I and D caches on. | |
546 | * | |
547 | * We place the page tables 16k down from the kernel execution address, | |
548 | * and we hope that nothing else is using it. If we're using it, we | |
549 | * will go pop! | |
550 | * | |
551 | * On entry, | |
552 | * r4 = kernel execution address | |
1da177e4 | 553 | * r7 = architecture number |
f4619025 | 554 | * r8 = atags pointer |
1da177e4 | 555 | * On exit, |
21b2841d | 556 | * r0, r1, r2, r3, r9, r10, r12 corrupted |
1da177e4 | 557 | * This routine must preserve: |
6d7d0ae5 | 558 | * r4, r7, r8 |
1da177e4 LT |
559 | */ |
560 | .align 5 | |
561 | cache_on: mov r3, #8 @ cache_on function | |
562 | b call_cache_fn | |
563 | ||
10c2df65 HC |
564 | /* |
565 | * Initialize the highest priority protection region, PR7 | |
566 | * to cover all 32bit address and cacheable and bufferable. | |
567 | */ | |
568 | __armv4_mpu_cache_on: | |
569 | mov r0, #0x3f @ 4G, the whole | |
570 | mcr p15, 0, r0, c6, c7, 0 @ PR7 Area Setting | |
571 | mcr p15, 0, r0, c6, c7, 1 | |
572 | ||
573 | mov r0, #0x80 @ PR7 | |
574 | mcr p15, 0, r0, c2, c0, 0 @ D-cache on | |
575 | mcr p15, 0, r0, c2, c0, 1 @ I-cache on | |
576 | mcr p15, 0, r0, c3, c0, 0 @ write-buffer on | |
577 | ||
578 | mov r0, #0xc000 | |
579 | mcr p15, 0, r0, c5, c0, 1 @ I-access permission | |
580 | mcr p15, 0, r0, c5, c0, 0 @ D-access permission | |
581 | ||
582 | mov r0, #0 | |
583 | mcr p15, 0, r0, c7, c10, 4 @ drain write buffer | |
584 | mcr p15, 0, r0, c7, c5, 0 @ flush(inval) I-Cache | |
585 | mcr p15, 0, r0, c7, c6, 0 @ flush(inval) D-Cache | |
586 | mrc p15, 0, r0, c1, c0, 0 @ read control reg | |
587 | @ ...I .... ..D. WC.M | |
588 | orr r0, r0, #0x002d @ .... .... ..1. 11.1 | |
589 | orr r0, r0, #0x1000 @ ...1 .... .... .... | |
590 | ||
591 | mcr p15, 0, r0, c1, c0, 0 @ write control reg | |
592 | ||
593 | mov r0, #0 | |
594 | mcr p15, 0, r0, c7, c5, 0 @ flush(inval) I-Cache | |
595 | mcr p15, 0, r0, c7, c6, 0 @ flush(inval) D-Cache | |
596 | mov pc, lr | |
597 | ||
598 | __armv3_mpu_cache_on: | |
599 | mov r0, #0x3f @ 4G, the whole | |
600 | mcr p15, 0, r0, c6, c7, 0 @ PR7 Area Setting | |
601 | ||
602 | mov r0, #0x80 @ PR7 | |
603 | mcr p15, 0, r0, c2, c0, 0 @ cache on | |
604 | mcr p15, 0, r0, c3, c0, 0 @ write-buffer on | |
605 | ||
606 | mov r0, #0xc000 | |
607 | mcr p15, 0, r0, c5, c0, 0 @ access permission | |
608 | ||
609 | mov r0, #0 | |
610 | mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3 | |
4a8d57a5 UKK |
611 | /* |
612 | * ?? ARMv3 MMU does not allow reading the control register, | |
613 | * does this really work on ARMv3 MPU? | |
614 | */ | |
10c2df65 HC |
615 | mrc p15, 0, r0, c1, c0, 0 @ read control reg |
616 | @ .... .... .... WC.M | |
617 | orr r0, r0, #0x000d @ .... .... .... 11.1 | |
4a8d57a5 | 618 | /* ?? this overwrites the value constructed above? */ |
10c2df65 HC |
619 | mov r0, #0 |
620 | mcr p15, 0, r0, c1, c0, 0 @ write control reg | |
621 | ||
4a8d57a5 | 622 | /* ?? invalidate for the second time? */ |
10c2df65 HC |
623 | mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3 |
624 | mov pc, lr | |
625 | ||
1fdc08ab RK |
626 | #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH |
627 | #define CB_BITS 0x08 | |
628 | #else | |
629 | #define CB_BITS 0x0c | |
630 | #endif | |
631 | ||
1da177e4 LT |
632 | __setup_mmu: sub r3, r4, #16384 @ Page directory size |
633 | bic r3, r3, #0xff @ Align the pointer | |
634 | bic r3, r3, #0x3f00 | |
635 | /* | |
636 | * Initialise the page tables, turning on the cacheable and bufferable | |
637 | * bits for the RAM area only. | |
638 | */ | |
639 | mov r0, r3 | |
f4619025 RK |
640 | mov r9, r0, lsr #18 |
641 | mov r9, r9, lsl #18 @ start of RAM | |
642 | add r10, r9, #0x10000000 @ a reasonable RAM size | |
1fdc08ab RK |
643 | mov r1, #0x12 @ XN|U + section mapping |
644 | orr r1, r1, #3 << 10 @ AP=11 | |
1da177e4 | 645 | add r2, r3, #16384 |
265d5e48 | 646 | 1: cmp r1, r9 @ if virt > start of RAM |
1fdc08ab RK |
647 | cmphs r10, r1 @ && end of RAM > virt |
648 | bic r1, r1, #0x1c @ clear XN|U + C + B | |
649 | orrlo r1, r1, #0x10 @ Set XN|U for non-RAM | |
650 | orrhs r1, r1, r6 @ set RAM section settings | |
1da177e4 LT |
651 | str r1, [r0], #4 @ 1:1 mapping |
652 | add r1, r1, #1048576 | |
653 | teq r0, r2 | |
654 | bne 1b | |
655 | /* | |
656 | * If ever we are running from Flash, then we surely want the cache | |
657 | * to be enabled also for our execution instance... We map 2MB of it | |
658 | * so there is no map overlap problem for up to 1 MB compressed kernel. | |
659 | * If the execution is in RAM then we would only be duplicating the above. | |
660 | */ | |
1fdc08ab | 661 | orr r1, r6, #0x04 @ ensure B is set for this |
1da177e4 | 662 | orr r1, r1, #3 << 10 |
bfa64c4a DM |
663 | mov r2, pc |
664 | mov r2, r2, lsr #20 | |
1da177e4 LT |
665 | orr r1, r1, r2, lsl #20 |
666 | add r0, r3, r2, lsl #2 | |
667 | str r1, [r0], #4 | |
668 | add r1, r1, #1048576 | |
669 | str r1, [r0] | |
670 | mov pc, lr | |
93ed3970 | 671 | ENDPROC(__setup_mmu) |
1da177e4 | 672 | |
5010192d DM |
673 | @ Enable unaligned access on v6, to allow better code generation |
674 | @ for the decompressor C code: | |
675 | __armv6_mmu_cache_on: | |
676 | mrc p15, 0, r0, c1, c0, 0 @ read SCTLR | |
677 | bic r0, r0, #2 @ A (no unaligned access fault) | |
678 | orr r0, r0, #1 << 22 @ U (v6 unaligned access model) | |
679 | mcr p15, 0, r0, c1, c0, 0 @ write SCTLR | |
680 | b __armv4_mmu_cache_on | |
681 | ||
af3e4fd3 MG |
682 | __arm926ejs_mmu_cache_on: |
683 | #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH | |
684 | mov r0, #4 @ put dcache in WT mode | |
685 | mcr p15, 7, r0, c15, c0, 0 | |
686 | #endif | |
687 | ||
c76b6b41 | 688 | __armv4_mmu_cache_on: |
1da177e4 | 689 | mov r12, lr |
8bdca0ac | 690 | #ifdef CONFIG_MMU |
1fdc08ab | 691 | mov r6, #CB_BITS | 0x12 @ U |
1da177e4 LT |
692 | bl __setup_mmu |
693 | mov r0, #0 | |
694 | mcr p15, 0, r0, c7, c10, 4 @ drain write buffer | |
695 | mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs | |
696 | mrc p15, 0, r0, c1, c0, 0 @ read control reg | |
697 | orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement | |
698 | orr r0, r0, #0x0030 | |
457c2403 | 699 | ARM_BE8( orr r0, r0, #1 << 25 ) @ big-endian page tables |
c76b6b41 | 700 | bl __common_mmu_cache_on |
1da177e4 LT |
701 | mov r0, #0 |
702 | mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs | |
8bdca0ac | 703 | #endif |
1da177e4 LT |
704 | mov pc, r12 |
705 | ||
7d09e854 CM |
706 | __armv7_mmu_cache_on: |
707 | mov r12, lr | |
8bdca0ac | 708 | #ifdef CONFIG_MMU |
7d09e854 CM |
709 | mrc p15, 0, r11, c0, c1, 4 @ read ID_MMFR0 |
710 | tst r11, #0xf @ VMSA | |
1fdc08ab | 711 | movne r6, #CB_BITS | 0x02 @ !XN |
7d09e854 CM |
712 | blne __setup_mmu |
713 | mov r0, #0 | |
714 | mcr p15, 0, r0, c7, c10, 4 @ drain write buffer | |
715 | tst r11, #0xf @ VMSA | |
716 | mcrne p15, 0, r0, c8, c7, 0 @ flush I,D TLBs | |
8bdca0ac | 717 | #endif |
7d09e854 | 718 | mrc p15, 0, r0, c1, c0, 0 @ read control reg |
e1e5b7e4 | 719 | bic r0, r0, #1 << 28 @ clear SCTLR.TRE |
7d09e854 CM |
720 | orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement |
721 | orr r0, r0, #0x003c @ write buffer | |
5010192d DM |
722 | bic r0, r0, #2 @ A (no unaligned access fault) |
723 | orr r0, r0, #1 << 22 @ U (v6 unaligned access model) | |
724 | @ (needed for ARM1176) | |
8bdca0ac | 725 | #ifdef CONFIG_MMU |
457c2403 | 726 | ARM_BE8( orr r0, r0, #1 << 25 ) @ big-endian page tables |
dbece458 | 727 | mrcne p15, 0, r6, c2, c0, 2 @ read ttb control reg |
7d09e854 | 728 | orrne r0, r0, #1 @ MMU enabled |
1fdc08ab | 729 | movne r1, #0xfffffffd @ domain 0 = client |
dbece458 WD |
730 | bic r6, r6, #1 << 31 @ 32-bit translation system |
731 | bic r6, r6, #3 << 0 @ use only ttbr0 | |
7d09e854 CM |
732 | mcrne p15, 0, r3, c2, c0, 0 @ load page table pointer |
733 | mcrne p15, 0, r1, c3, c0, 0 @ load domain access control | |
dbece458 | 734 | mcrne p15, 0, r6, c2, c0, 2 @ load ttb control |
8bdca0ac | 735 | #endif |
d675d0bc | 736 | mcr p15, 0, r0, c7, c5, 4 @ ISB |
7d09e854 CM |
737 | mcr p15, 0, r0, c1, c0, 0 @ load control register |
738 | mrc p15, 0, r0, c1, c0, 0 @ and read it back | |
739 | mov r0, #0 | |
740 | mcr p15, 0, r0, c7, c5, 4 @ ISB | |
741 | mov pc, r12 | |
742 | ||
28853ac8 PZ |
743 | __fa526_cache_on: |
744 | mov r12, lr | |
1fdc08ab | 745 | mov r6, #CB_BITS | 0x12 @ U |
28853ac8 PZ |
746 | bl __setup_mmu |
747 | mov r0, #0 | |
748 | mcr p15, 0, r0, c7, c7, 0 @ Invalidate whole cache | |
749 | mcr p15, 0, r0, c7, c10, 4 @ drain write buffer | |
750 | mcr p15, 0, r0, c8, c7, 0 @ flush UTLB | |
751 | mrc p15, 0, r0, c1, c0, 0 @ read control reg | |
752 | orr r0, r0, #0x1000 @ I-cache enable | |
753 | bl __common_mmu_cache_on | |
754 | mov r0, #0 | |
755 | mcr p15, 0, r0, c8, c7, 0 @ flush UTLB | |
756 | mov pc, r12 | |
757 | ||
c76b6b41 | 758 | __common_mmu_cache_on: |
0e056f20 | 759 | #ifndef CONFIG_THUMB2_KERNEL |
1da177e4 LT |
760 | #ifndef DEBUG |
761 | orr r0, r0, #0x000d @ Write buffer, mmu | |
762 | #endif | |
763 | mov r1, #-1 | |
764 | mcr p15, 0, r3, c2, c0, 0 @ load page table pointer | |
765 | mcr p15, 0, r1, c3, c0, 0 @ load domain access control | |
2dc7667b NP |
766 | b 1f |
767 | .align 5 @ cache line aligned | |
768 | 1: mcr p15, 0, r0, c1, c0, 0 @ load control register | |
769 | mrc p15, 0, r0, c1, c0, 0 @ and read it back to | |
770 | sub pc, lr, r0, lsr #32 @ properly flush pipeline | |
0e056f20 | 771 | #endif |
1da177e4 | 772 | |
946a105e DM |
773 | #define PROC_ENTRY_SIZE (4*5) |
774 | ||
1da177e4 LT |
775 | /* |
776 | * Here follow the relocatable cache support functions for the | |
777 | * various processors. This is a generic hook for locating an | |
778 | * entry and jumping to an instruction at the specified offset | |
779 | * from the start of the block. Please note this is all position | |
780 | * independent code. | |
781 | * | |
782 | * r1 = corrupted | |
783 | * r2 = corrupted | |
784 | * r3 = block offset | |
98e12b5a | 785 | * r9 = corrupted |
1da177e4 LT |
786 | * r12 = corrupted |
787 | */ | |
788 | ||
789 | call_cache_fn: adr r12, proc_types | |
f12d0d7c | 790 | #ifdef CONFIG_CPU_CP15 |
98e12b5a | 791 | mrc p15, 0, r9, c0, c0 @ get processor ID |
f12d0d7c | 792 | #else |
98e12b5a | 793 | ldr r9, =CONFIG_PROCESSOR_ID |
f12d0d7c | 794 | #endif |
1da177e4 LT |
795 | 1: ldr r1, [r12, #0] @ get value |
796 | ldr r2, [r12, #4] @ get mask | |
98e12b5a | 797 | eor r1, r1, r9 @ (real ^ match) |
1da177e4 | 798 | tst r1, r2 @ & mask |
0e056f20 CM |
799 | ARM( addeq pc, r12, r3 ) @ call cache function |
800 | THUMB( addeq r12, r3 ) | |
801 | THUMB( moveq pc, r12 ) @ call cache function | |
946a105e | 802 | add r12, r12, #PROC_ENTRY_SIZE |
1da177e4 LT |
803 | b 1b |
804 | ||
805 | /* | |
806 | * Table for cache operations. This is basically: | |
807 | * - CPU ID match | |
808 | * - CPU ID mask | |
809 | * - 'cache on' method instruction | |
810 | * - 'cache off' method instruction | |
811 | * - 'cache flush' method instruction | |
812 | * | |
813 | * We match an entry using: ((real_id ^ match) & mask) == 0 | |
814 | * | |
815 | * Writethrough caches generally only need 'on' and 'off' | |
816 | * methods. Writeback caches _must_ have the flush method | |
817 | * defined. | |
818 | */ | |
88987ef9 | 819 | .align 2 |
1da177e4 LT |
820 | .type proc_types,#object |
821 | proc_types: | |
ced2a3b8 M |
822 | .word 0x41000000 @ old ARM ID |
823 | .word 0xff00f000 | |
1da177e4 | 824 | mov pc, lr |
0e056f20 | 825 | THUMB( nop ) |
1da177e4 | 826 | mov pc, lr |
0e056f20 | 827 | THUMB( nop ) |
1da177e4 | 828 | mov pc, lr |
0e056f20 | 829 | THUMB( nop ) |
1da177e4 LT |
830 | |
831 | .word 0x41007000 @ ARM7/710 | |
832 | .word 0xfff8fe00 | |
4cdfc2ec RK |
833 | mov pc, lr |
834 | THUMB( nop ) | |
835 | mov pc, lr | |
836 | THUMB( nop ) | |
1da177e4 | 837 | mov pc, lr |
0e056f20 | 838 | THUMB( nop ) |
1da177e4 LT |
839 | |
840 | .word 0x41807200 @ ARM720T (writethrough) | |
841 | .word 0xffffff00 | |
0e056f20 CM |
842 | W(b) __armv4_mmu_cache_on |
843 | W(b) __armv4_mmu_cache_off | |
1da177e4 | 844 | mov pc, lr |
0e056f20 | 845 | THUMB( nop ) |
1da177e4 | 846 | |
10c2df65 HC |
847 | .word 0x41007400 @ ARM74x |
848 | .word 0xff00ff00 | |
0e056f20 CM |
849 | W(b) __armv3_mpu_cache_on |
850 | W(b) __armv3_mpu_cache_off | |
851 | W(b) __armv3_mpu_cache_flush | |
10c2df65 HC |
852 | |
853 | .word 0x41009400 @ ARM94x | |
854 | .word 0xff00ff00 | |
0e056f20 CM |
855 | W(b) __armv4_mpu_cache_on |
856 | W(b) __armv4_mpu_cache_off | |
857 | W(b) __armv4_mpu_cache_flush | |
10c2df65 | 858 | |
af3e4fd3 MG |
859 | .word 0x41069260 @ ARM926EJ-S (v5TEJ) |
860 | .word 0xff0ffff0 | |
720c60e1 NP |
861 | W(b) __arm926ejs_mmu_cache_on |
862 | W(b) __armv4_mmu_cache_off | |
863 | W(b) __armv5tej_mmu_cache_flush | |
10c2df65 | 864 | |
1da177e4 LT |
865 | .word 0x00007000 @ ARM7 IDs |
866 | .word 0x0000f000 | |
867 | mov pc, lr | |
0e056f20 | 868 | THUMB( nop ) |
1da177e4 | 869 | mov pc, lr |
0e056f20 | 870 | THUMB( nop ) |
1da177e4 | 871 | mov pc, lr |
0e056f20 | 872 | THUMB( nop ) |
1da177e4 LT |
873 | |
874 | @ Everything from here on will be the new ID system. | |
875 | ||
876 | .word 0x4401a100 @ sa110 / sa1100 | |
877 | .word 0xffffffe0 | |
0e056f20 CM |
878 | W(b) __armv4_mmu_cache_on |
879 | W(b) __armv4_mmu_cache_off | |
880 | W(b) __armv4_mmu_cache_flush | |
1da177e4 LT |
881 | |
882 | .word 0x6901b110 @ sa1110 | |
883 | .word 0xfffffff0 | |
0e056f20 CM |
884 | W(b) __armv4_mmu_cache_on |
885 | W(b) __armv4_mmu_cache_off | |
886 | W(b) __armv4_mmu_cache_flush | |
1da177e4 | 887 | |
4157d317 HZ |
888 | .word 0x56056900 |
889 | .word 0xffffff00 @ PXA9xx | |
0e056f20 CM |
890 | W(b) __armv4_mmu_cache_on |
891 | W(b) __armv4_mmu_cache_off | |
892 | W(b) __armv4_mmu_cache_flush | |
49cbe786 EM |
893 | |
894 | .word 0x56158000 @ PXA168 | |
895 | .word 0xfffff000 | |
0e056f20 CM |
896 | W(b) __armv4_mmu_cache_on |
897 | W(b) __armv4_mmu_cache_off | |
898 | W(b) __armv5tej_mmu_cache_flush | |
49cbe786 | 899 | |
2e2023fe NP |
900 | .word 0x56050000 @ Feroceon |
901 | .word 0xff0f0000 | |
0e056f20 CM |
902 | W(b) __armv4_mmu_cache_on |
903 | W(b) __armv4_mmu_cache_off | |
904 | W(b) __armv5tej_mmu_cache_flush | |
3ebb5a2b | 905 | |
5587931c JS |
906 | #ifdef CONFIG_CPU_FEROCEON_OLD_ID |
907 | /* this conflicts with the standard ARMv5TE entry */ | |
908 | .long 0x41009260 @ Old Feroceon | |
909 | .long 0xff00fff0 | |
910 | b __armv4_mmu_cache_on | |
911 | b __armv4_mmu_cache_off | |
912 | b __armv5tej_mmu_cache_flush | |
913 | #endif | |
914 | ||
28853ac8 PZ |
915 | .word 0x66015261 @ FA526 |
916 | .word 0xff01fff1 | |
0e056f20 CM |
917 | W(b) __fa526_cache_on |
918 | W(b) __armv4_mmu_cache_off | |
919 | W(b) __fa526_cache_flush | |
28853ac8 | 920 | |
1da177e4 LT |
921 | @ These match on the architecture ID |
922 | ||
923 | .word 0x00020000 @ ARMv4T | |
924 | .word 0x000f0000 | |
0e056f20 CM |
925 | W(b) __armv4_mmu_cache_on |
926 | W(b) __armv4_mmu_cache_off | |
927 | W(b) __armv4_mmu_cache_flush | |
1da177e4 LT |
928 | |
929 | .word 0x00050000 @ ARMv5TE | |
930 | .word 0x000f0000 | |
0e056f20 CM |
931 | W(b) __armv4_mmu_cache_on |
932 | W(b) __armv4_mmu_cache_off | |
933 | W(b) __armv4_mmu_cache_flush | |
1da177e4 LT |
934 | |
935 | .word 0x00060000 @ ARMv5TEJ | |
936 | .word 0x000f0000 | |
0e056f20 CM |
937 | W(b) __armv4_mmu_cache_on |
938 | W(b) __armv4_mmu_cache_off | |
75216859 | 939 | W(b) __armv5tej_mmu_cache_flush |
1da177e4 | 940 | |
45a7b9cf | 941 | .word 0x0007b000 @ ARMv6 |
7d09e854 | 942 | .word 0x000ff000 |
5010192d | 943 | W(b) __armv6_mmu_cache_on |
0e056f20 CM |
944 | W(b) __armv4_mmu_cache_off |
945 | W(b) __armv6_mmu_cache_flush | |
1da177e4 | 946 | |
7d09e854 CM |
947 | .word 0x000f0000 @ new CPU Id |
948 | .word 0x000f0000 | |
0e056f20 CM |
949 | W(b) __armv7_mmu_cache_on |
950 | W(b) __armv7_mmu_cache_off | |
951 | W(b) __armv7_mmu_cache_flush | |
7d09e854 | 952 | |
1da177e4 LT |
953 | .word 0 @ unrecognised type |
954 | .word 0 | |
955 | mov pc, lr | |
0e056f20 | 956 | THUMB( nop ) |
1da177e4 | 957 | mov pc, lr |
0e056f20 | 958 | THUMB( nop ) |
1da177e4 | 959 | mov pc, lr |
0e056f20 | 960 | THUMB( nop ) |
1da177e4 LT |
961 | |
962 | .size proc_types, . - proc_types | |
963 | ||
946a105e DM |
964 | /* |
965 | * If you get a "non-constant expression in ".if" statement" | |
966 | * error from the assembler on this line, check that you have | |
967 | * not accidentally written a "b" instruction where you should | |
968 | * have written W(b). | |
969 | */ | |
970 | .if (. - proc_types) % PROC_ENTRY_SIZE != 0 | |
971 | .error "The size of one or more proc_types entries is wrong." | |
972 | .endif | |
973 | ||
1da177e4 LT |
974 | /* |
975 | * Turn off the Cache and MMU. ARMv3 does not support | |
976 | * reading the control register, but ARMv4 does. | |
977 | * | |
21b2841d UKK |
978 | * On exit, |
979 | * r0, r1, r2, r3, r9, r12 corrupted | |
980 | * This routine must preserve: | |
6d7d0ae5 | 981 | * r4, r7, r8 |
1da177e4 LT |
982 | */ |
983 | .align 5 | |
984 | cache_off: mov r3, #12 @ cache_off function | |
985 | b call_cache_fn | |
986 | ||
10c2df65 HC |
987 | __armv4_mpu_cache_off: |
988 | mrc p15, 0, r0, c1, c0 | |
989 | bic r0, r0, #0x000d | |
990 | mcr p15, 0, r0, c1, c0 @ turn MPU and cache off | |
991 | mov r0, #0 | |
992 | mcr p15, 0, r0, c7, c10, 4 @ drain write buffer | |
993 | mcr p15, 0, r0, c7, c6, 0 @ flush D-Cache | |
994 | mcr p15, 0, r0, c7, c5, 0 @ flush I-Cache | |
995 | mov pc, lr | |
996 | ||
997 | __armv3_mpu_cache_off: | |
998 | mrc p15, 0, r0, c1, c0 | |
999 | bic r0, r0, #0x000d | |
1000 | mcr p15, 0, r0, c1, c0, 0 @ turn MPU and cache off | |
1001 | mov r0, #0 | |
1002 | mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3 | |
1003 | mov pc, lr | |
1004 | ||
c76b6b41 | 1005 | __armv4_mmu_cache_off: |
8bdca0ac | 1006 | #ifdef CONFIG_MMU |
1da177e4 LT |
1007 | mrc p15, 0, r0, c1, c0 |
1008 | bic r0, r0, #0x000d | |
1009 | mcr p15, 0, r0, c1, c0 @ turn MMU and cache off | |
1010 | mov r0, #0 | |
1011 | mcr p15, 0, r0, c7, c7 @ invalidate whole cache v4 | |
1012 | mcr p15, 0, r0, c8, c7 @ invalidate whole TLB v4 | |
8bdca0ac | 1013 | #endif |
1da177e4 LT |
1014 | mov pc, lr |
1015 | ||
7d09e854 CM |
1016 | __armv7_mmu_cache_off: |
1017 | mrc p15, 0, r0, c1, c0 | |
8bdca0ac | 1018 | #ifdef CONFIG_MMU |
7d09e854 | 1019 | bic r0, r0, #0x000d |
8bdca0ac CM |
1020 | #else |
1021 | bic r0, r0, #0x000c | |
1022 | #endif | |
7d09e854 CM |
1023 | mcr p15, 0, r0, c1, c0 @ turn MMU and cache off |
1024 | mov r12, lr | |
1025 | bl __armv7_mmu_cache_flush | |
1026 | mov r0, #0 | |
8bdca0ac | 1027 | #ifdef CONFIG_MMU |
7d09e854 | 1028 | mcr p15, 0, r0, c8, c7, 0 @ invalidate whole TLB |
8bdca0ac | 1029 | #endif |
c30c2f99 CM |
1030 | mcr p15, 0, r0, c7, c5, 6 @ invalidate BTC |
1031 | mcr p15, 0, r0, c7, c10, 4 @ DSB | |
1032 | mcr p15, 0, r0, c7, c5, 4 @ ISB | |
7d09e854 CM |
1033 | mov pc, r12 |
1034 | ||
1da177e4 LT |
1035 | /* |
1036 | * Clean and flush the cache to maintain consistency. | |
1037 | * | |
1da177e4 | 1038 | * On exit, |
21b2841d | 1039 | * r1, r2, r3, r9, r10, r11, r12 corrupted |
1da177e4 | 1040 | * This routine must preserve: |
6d7d0ae5 | 1041 | * r4, r6, r7, r8 |
1da177e4 LT |
1042 | */ |
1043 | .align 5 | |
1044 | cache_clean_flush: | |
1045 | mov r3, #16 | |
1046 | b call_cache_fn | |
1047 | ||
10c2df65 HC |
1048 | __armv4_mpu_cache_flush: |
1049 | mov r2, #1 | |
1050 | mov r3, #0 | |
1051 | mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache | |
1052 | mov r1, #7 << 5 @ 8 segments | |
1053 | 1: orr r3, r1, #63 << 26 @ 64 entries | |
1054 | 2: mcr p15, 0, r3, c7, c14, 2 @ clean & invalidate D index | |
1055 | subs r3, r3, #1 << 26 | |
1056 | bcs 2b @ entries 63 to 0 | |
1057 | subs r1, r1, #1 << 5 | |
1058 | bcs 1b @ segments 7 to 0 | |
1059 | ||
1060 | teq r2, #0 | |
1061 | mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache | |
1062 | mcr p15, 0, ip, c7, c10, 4 @ drain WB | |
1063 | mov pc, lr | |
1064 | ||
28853ac8 PZ |
1065 | __fa526_cache_flush: |
1066 | mov r1, #0 | |
1067 | mcr p15, 0, r1, c7, c14, 0 @ clean and invalidate D cache | |
1068 | mcr p15, 0, r1, c7, c5, 0 @ flush I cache | |
1069 | mcr p15, 0, r1, c7, c10, 4 @ drain WB | |
1070 | mov pc, lr | |
10c2df65 | 1071 | |
c76b6b41 | 1072 | __armv6_mmu_cache_flush: |
1da177e4 LT |
1073 | mov r1, #0 |
1074 | mcr p15, 0, r1, c7, c14, 0 @ clean+invalidate D | |
1075 | mcr p15, 0, r1, c7, c5, 0 @ invalidate I+BTB | |
1076 | mcr p15, 0, r1, c7, c15, 0 @ clean+invalidate unified | |
1077 | mcr p15, 0, r1, c7, c10, 4 @ drain WB | |
1078 | mov pc, lr | |
1079 | ||
7d09e854 CM |
1080 | __armv7_mmu_cache_flush: |
1081 | mrc p15, 0, r10, c0, c1, 5 @ read ID_MMFR1 | |
1082 | tst r10, #0xf << 16 @ hierarchical cache (ARMv7) | |
7d09e854 | 1083 | mov r10, #0 |
c30c2f99 | 1084 | beq hierarchical |
7d09e854 CM |
1085 | mcr p15, 0, r10, c7, c14, 0 @ clean+invalidate D |
1086 | b iflush | |
1087 | hierarchical: | |
c30c2f99 | 1088 | mcr p15, 0, r10, c7, c10, 5 @ DMB |
0e056f20 | 1089 | stmfd sp!, {r0-r7, r9-r11} |
7d09e854 CM |
1090 | mrc p15, 1, r0, c0, c0, 1 @ read clidr |
1091 | ands r3, r0, #0x7000000 @ extract loc from clidr | |
1092 | mov r3, r3, lsr #23 @ left align loc bit field | |
1093 | beq finished @ if loc is 0, then no need to clean | |
1094 | mov r10, #0 @ start clean at cache level 0 | |
1095 | loop1: | |
1096 | add r2, r10, r10, lsr #1 @ work out 3x current cache level | |
1097 | mov r1, r0, lsr r2 @ extract cache type bits from clidr | |
1098 | and r1, r1, #7 @ mask of the bits for current cache only | |
1099 | cmp r1, #2 @ see what cache we have at this level | |
1100 | blt skip @ skip if no cache, or just i-cache | |
1101 | mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr | |
1102 | mcr p15, 0, r10, c7, c5, 4 @ isb to sych the new cssr&csidr | |
1103 | mrc p15, 1, r1, c0, c0, 0 @ read the new csidr | |
1104 | and r2, r1, #7 @ extract the length of the cache lines | |
1105 | add r2, r2, #4 @ add 4 (line length offset) | |
1106 | ldr r4, =0x3ff | |
1107 | ands r4, r4, r1, lsr #3 @ find maximum number on the way size | |
000b5025 | 1108 | clz r5, r4 @ find bit position of way size increment |
7d09e854 CM |
1109 | ldr r7, =0x7fff |
1110 | ands r7, r7, r1, lsr #13 @ extract max number of the index size | |
1111 | loop2: | |
1112 | mov r9, r4 @ create working copy of max way size | |
1113 | loop3: | |
0e056f20 CM |
1114 | ARM( orr r11, r10, r9, lsl r5 ) @ factor way and cache number into r11 |
1115 | ARM( orr r11, r11, r7, lsl r2 ) @ factor index number into r11 | |
1116 | THUMB( lsl r6, r9, r5 ) | |
1117 | THUMB( orr r11, r10, r6 ) @ factor way and cache number into r11 | |
1118 | THUMB( lsl r6, r7, r2 ) | |
1119 | THUMB( orr r11, r11, r6 ) @ factor index number into r11 | |
7d09e854 CM |
1120 | mcr p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way |
1121 | subs r9, r9, #1 @ decrement the way | |
1122 | bge loop3 | |
1123 | subs r7, r7, #1 @ decrement the index | |
1124 | bge loop2 | |
1125 | skip: | |
1126 | add r10, r10, #2 @ increment cache number | |
1127 | cmp r3, r10 | |
1128 | bgt loop1 | |
1129 | finished: | |
0e056f20 | 1130 | ldmfd sp!, {r0-r7, r9-r11} |
7d09e854 CM |
1131 | mov r10, #0 @ swith back to cache level 0 |
1132 | mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr | |
7d09e854 | 1133 | iflush: |
c30c2f99 | 1134 | mcr p15, 0, r10, c7, c10, 4 @ DSB |
7d09e854 | 1135 | mcr p15, 0, r10, c7, c5, 0 @ invalidate I+BTB |
c30c2f99 CM |
1136 | mcr p15, 0, r10, c7, c10, 4 @ DSB |
1137 | mcr p15, 0, r10, c7, c5, 4 @ ISB | |
7d09e854 CM |
1138 | mov pc, lr |
1139 | ||
15754bf9 NP |
1140 | __armv5tej_mmu_cache_flush: |
1141 | 1: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate D cache | |
1142 | bne 1b | |
1143 | mcr p15, 0, r0, c7, c5, 0 @ flush I cache | |
1144 | mcr p15, 0, r0, c7, c10, 4 @ drain WB | |
1145 | mov pc, lr | |
1146 | ||
c76b6b41 | 1147 | __armv4_mmu_cache_flush: |
1da177e4 LT |
1148 | mov r2, #64*1024 @ default: 32K dcache size (*2) |
1149 | mov r11, #32 @ default: 32 byte line size | |
1150 | mrc p15, 0, r3, c0, c0, 1 @ read cache type | |
98e12b5a | 1151 | teq r3, r9 @ cache ID register present? |
1da177e4 LT |
1152 | beq no_cache_id |
1153 | mov r1, r3, lsr #18 | |
1154 | and r1, r1, #7 | |
1155 | mov r2, #1024 | |
1156 | mov r2, r2, lsl r1 @ base dcache size *2 | |
1157 | tst r3, #1 << 14 @ test M bit | |
1158 | addne r2, r2, r2, lsr #1 @ +1/2 size if M == 1 | |
1159 | mov r3, r3, lsr #12 | |
1160 | and r3, r3, #3 | |
1161 | mov r11, #8 | |
1162 | mov r11, r11, lsl r3 @ cache line size in bytes | |
1163 | no_cache_id: | |
0e056f20 CM |
1164 | mov r1, pc |
1165 | bic r1, r1, #63 @ align to longest cache line | |
1da177e4 | 1166 | add r2, r1, r2 |
0e056f20 CM |
1167 | 1: |
1168 | ARM( ldr r3, [r1], r11 ) @ s/w flush D cache | |
1169 | THUMB( ldr r3, [r1] ) @ s/w flush D cache | |
1170 | THUMB( add r1, r1, r11 ) | |
1da177e4 LT |
1171 | teq r1, r2 |
1172 | bne 1b | |
1173 | ||
1174 | mcr p15, 0, r1, c7, c5, 0 @ flush I cache | |
1175 | mcr p15, 0, r1, c7, c6, 0 @ flush D cache | |
1176 | mcr p15, 0, r1, c7, c10, 4 @ drain WB | |
1177 | mov pc, lr | |
1178 | ||
c76b6b41 | 1179 | __armv3_mmu_cache_flush: |
10c2df65 | 1180 | __armv3_mpu_cache_flush: |
1da177e4 | 1181 | mov r1, #0 |
63fa7187 | 1182 | mcr p15, 0, r1, c7, c0, 0 @ invalidate whole cache v3 |
1da177e4 LT |
1183 | mov pc, lr |
1184 | ||
1185 | /* | |
1186 | * Various debugging routines for printing hex characters and | |
1187 | * memory, which again must be relocatable. | |
1188 | */ | |
1189 | #ifdef DEBUG | |
88987ef9 | 1190 | .align 2 |
1da177e4 LT |
1191 | .type phexbuf,#object |
1192 | phexbuf: .space 12 | |
1193 | .size phexbuf, . - phexbuf | |
1194 | ||
be6f9f00 | 1195 | @ phex corrupts {r0, r1, r2, r3} |
1da177e4 LT |
1196 | phex: adr r3, phexbuf |
1197 | mov r2, #0 | |
1198 | strb r2, [r3, r1] | |
1199 | 1: subs r1, r1, #1 | |
1200 | movmi r0, r3 | |
1201 | bmi puts | |
1202 | and r2, r0, #15 | |
1203 | mov r0, r0, lsr #4 | |
1204 | cmp r2, #10 | |
1205 | addge r2, r2, #7 | |
1206 | add r2, r2, #'0' | |
1207 | strb r2, [r3, r1] | |
1208 | b 1b | |
1209 | ||
be6f9f00 | 1210 | @ puts corrupts {r0, r1, r2, r3} |
4e6d488a | 1211 | puts: loadsp r3, r1 |
1da177e4 LT |
1212 | 1: ldrb r2, [r0], #1 |
1213 | teq r2, #0 | |
1214 | moveq pc, lr | |
5cd0c344 | 1215 | 2: writeb r2, r3 |
1da177e4 LT |
1216 | mov r1, #0x00020000 |
1217 | 3: subs r1, r1, #1 | |
1218 | bne 3b | |
1219 | teq r2, #'\n' | |
1220 | moveq r2, #'\r' | |
1221 | beq 2b | |
1222 | teq r0, #0 | |
1223 | bne 1b | |
1224 | mov pc, lr | |
be6f9f00 | 1225 | @ putc corrupts {r0, r1, r2, r3} |
1da177e4 LT |
1226 | putc: |
1227 | mov r2, r0 | |
1228 | mov r0, #0 | |
4e6d488a | 1229 | loadsp r3, r1 |
1da177e4 LT |
1230 | b 2b |
1231 | ||
be6f9f00 | 1232 | @ memdump corrupts {r0, r1, r2, r3, r10, r11, r12, lr} |
1da177e4 LT |
1233 | memdump: mov r12, r0 |
1234 | mov r10, lr | |
1235 | mov r11, #0 | |
1236 | 2: mov r0, r11, lsl #2 | |
1237 | add r0, r0, r12 | |
1238 | mov r1, #8 | |
1239 | bl phex | |
1240 | mov r0, #':' | |
1241 | bl putc | |
1242 | 1: mov r0, #' ' | |
1243 | bl putc | |
1244 | ldr r0, [r12, r11, lsl #2] | |
1245 | mov r1, #8 | |
1246 | bl phex | |
1247 | and r0, r11, #7 | |
1248 | teq r0, #3 | |
1249 | moveq r0, #' ' | |
1250 | bleq putc | |
1251 | and r0, r11, #7 | |
1252 | add r11, r11, #1 | |
1253 | teq r0, #7 | |
1254 | bne 1b | |
1255 | mov r0, #'\n' | |
1256 | bl putc | |
1257 | cmp r11, #64 | |
1258 | blt 2b | |
1259 | mov pc, r10 | |
1260 | #endif | |
1261 | ||
92c83ff1 | 1262 | .ltorg |
424e5994 DM |
1263 | |
1264 | #ifdef CONFIG_ARM_VIRT_EXT | |
1265 | .align 5 | |
1266 | __hyp_reentry_vectors: | |
1267 | W(b) . @ reset | |
1268 | W(b) . @ undef | |
1269 | W(b) . @ svc | |
1270 | W(b) . @ pabort | |
1271 | W(b) . @ dabort | |
1272 | W(b) __enter_kernel @ hyp | |
1273 | W(b) . @ irq | |
1274 | W(b) . @ fiq | |
1275 | #endif /* CONFIG_ARM_VIRT_EXT */ | |
1276 | ||
1277 | __enter_kernel: | |
1278 | mov r0, #0 @ must be 0 | |
1279 | ARM( mov pc, r4 ) @ call kernel | |
1280 | THUMB( bx r4 ) @ entry point is always ARM | |
1281 | ||
adcc2591 | 1282 | reloc_code_end: |
1da177e4 LT |
1283 | |
1284 | .align | |
b0c4d4ee | 1285 | .section ".stack", "aw", %nobits |
8d7e4cc2 NP |
1286 | .L_user_stack: .space 4096 |
1287 | .L_user_stack_end: |