projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 5fc0b42a AC |
1 | /* |
| 2 | * Device Tree Source for AM33XX SoC | |
| 3 | * | |
| 4 | * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ | |
| 5 | * | |
| 6 | * This file is licensed under the terms of the GNU General Public License | |
| 7 | * version 2. This program is licensed "as is" without any warranty of any | |
| 8 | * kind, whether express or implied. | |
| 9 | */ | |
| 10 | ||
| 11 | /include/ "skeleton.dtsi" | |
| 12 | ||
| 13 | / { | |
| 14 | compatible = "ti,am33xx"; | |
| 15 | ||
| 16 | aliases { | |
| 17 | serial0 = &uart1; | |
| 18 | serial1 = &uart2; | |
| 19 | serial2 = &uart3; | |
| 20 | serial3 = &uart4; | |
| 21 | serial4 = &uart5; | |
| 22 | serial5 = &uart6; | |
| 23 | }; | |
| 24 | ||
| 25 | cpus { | |
| 26 | cpu@0 { | |
| 27 | compatible = "arm,cortex-a8"; | |
| 28 | }; | |
| 29 | }; | |
| 30 | ||
| 31 | /* | |
| 32 | * The soc node represents the soc top level view. It is uses for IPs | |
| 33 | * that are not memory mapped in the MPU view or for the MPU itself. | |
| 34 | */ | |
| 35 | soc { | |
| 36 | compatible = "ti,omap-infra"; | |
| 37 | mpu { | |
| 38 | compatible = "ti,omap3-mpu"; | |
| 39 | ti,hwmods = "mpu"; | |
| 40 | }; | |
| 41 | }; | |
| 42 | ||
| 43 | /* | |
| 44 | * XXX: Use a flat representation of the AM33XX interconnect. | |
| 45 | * The real AM33XX interconnect network is quite complex.Since | |
| 46 | * that will not bring real advantage to represent that in DT | |
| 47 | * for the moment, just use a fake OCP bus entry to represent | |
| 48 | * the whole bus hierarchy. | |
| 49 | */ | |
| 50 | ocp { | |
| 51 | compatible = "simple-bus"; | |
| 52 | #address-cells = <1>; | |
| 53 | #size-cells = <1>; | |
| 54 | ranges; | |
| 55 | ti,hwmods = "l3_main"; | |
| 56 | ||
| 57 | intc: interrupt-controller@48200000 { | |
| 58 | compatible = "ti,omap2-intc"; | |
| 59 | interrupt-controller; | |
| 60 | #interrupt-cells = <1>; | |
| 61 | ti,intc-size = <128>; | |
| 62 | reg = <0x48200000 0x1000>; | |
| 63 | }; | |
| 64 | ||
| 65 | gpio1: gpio@44e07000 { | |
| 66 | compatible = "ti,omap4-gpio"; | |
| 67 | ti,hwmods = "gpio1"; | |
| 68 | gpio-controller; | |
| 69 | #gpio-cells = <2>; | |
| 70 | interrupt-controller; | |
| 71 | #interrupt-cells = <1>; | |
| 72 | }; | |
| 73 | ||
| 74 | gpio2: gpio@4804C000 { | |
| 75 | compatible = "ti,omap4-gpio"; | |
| 76 | ti,hwmods = "gpio2"; | |
| 77 | gpio-controller; | |
| 78 | #gpio-cells = <2>; | |
| 79 | interrupt-controller; | |
| 80 | #interrupt-cells = <1>; | |
| 81 | }; | |
| 82 | ||
| 83 | gpio3: gpio@481AC000 { | |
| 84 | compatible = "ti,omap4-gpio"; | |
| 85 | ti,hwmods = "gpio3"; | |
| 86 | gpio-controller; | |
| 87 | #gpio-cells = <2>; | |
| 88 | interrupt-controller; | |
| 89 | #interrupt-cells = <1>; | |
| 90 | }; | |
| 91 | ||
| 92 | gpio4: gpio@481AE000 { | |
| 93 | compatible = "ti,omap4-gpio"; | |
| 94 | ti,hwmods = "gpio4"; | |
| 95 | gpio-controller; | |
| 96 | #gpio-cells = <2>; | |
| 97 | interrupt-controller; | |
| 98 | #interrupt-cells = <1>; | |
| 99 | }; | |
| 100 | ||
| 101 | uart1: serial@44E09000 { | |
| 102 | compatible = "ti,omap3-uart"; | |
| 103 | ti,hwmods = "uart1"; | |
| 104 | clock-frequency = <48000000>; | |
| 105 | }; | |
| 106 | ||
| 107 | uart2: serial@48022000 { | |
| 108 | compatible = "ti,omap3-uart"; | |
| 109 | ti,hwmods = "uart2"; | |
| 110 | clock-frequency = <48000000>; | |
| 111 | }; | |
| 112 | ||
| 113 | uart3: serial@48024000 { | |
| 114 | compatible = "ti,omap3-uart"; | |
| 115 | ti,hwmods = "uart3"; | |
| 116 | clock-frequency = <48000000>; | |
| 117 | }; | |
| 118 | ||
| 119 | uart4: serial@481A6000 { | |
| 120 | compatible = "ti,omap3-uart"; | |
| 121 | ti,hwmods = "uart4"; | |
| 122 | clock-frequency = <48000000>; | |
| 123 | }; | |
| 124 | ||
| 125 | uart5: serial@481A8000 { | |
| 126 | compatible = "ti,omap3-uart"; | |
| 127 | ti,hwmods = "uart5"; | |
| 128 | clock-frequency = <48000000>; | |
| 129 | }; | |
| 130 | ||
| 131 | uart6: serial@481AA000 { | |
| 132 | compatible = "ti,omap3-uart"; | |
| 133 | ti,hwmods = "uart6"; | |
| 134 | clock-frequency = <48000000>; | |
| 135 | }; | |
| 136 | ||
| 137 | i2c1: i2c@44E0B000 { | |
| 138 | compatible = "ti,omap4-i2c"; | |
| 139 | #address-cells = <1>; | |
| 140 | #size-cells = <0>; | |
| 141 | ti,hwmods = "i2c1"; | |
| 142 | }; | |
| 143 | ||
| 144 | i2c2: i2c@4802A000 { | |
| 145 | compatible = "ti,omap4-i2c"; | |
| 146 | #address-cells = <1>; | |
| 147 | #size-cells = <0>; | |
| 148 | ti,hwmods = "i2c2"; | |
| 149 | }; | |
| 150 | ||
| 151 | i2c3: i2c@4819C000 { | |
| 152 | compatible = "ti,omap4-i2c"; | |
| 153 | #address-cells = <1>; | |
| 154 | #size-cells = <0>; | |
| 155 | ti,hwmods = "i2c3"; | |
| 156 | }; | |
| 5fc0b42a AC |
157 | }; |
| 158 | }; |