[deliverable/linux.git] / arch / arm / boot / dts / am33xx.dtsi

/*
 * Device Tree Source for AM33XX SoC
 *
 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
 *
 * This file is licensed under the terms of the GNU General Public License
 * version 2.  This program is licensed "as is" without any warranty of any
 * kind, whether express or implied.
 */

/include/ "skeleton.dtsi"

/ {
	compatible = "ti,am33xx";

	aliases {
		serial0 = &uart1;
		serial1 = &uart2;
		serial2 = &uart3;
		serial3 = &uart4;
		serial4 = &uart5;
		serial5 = &uart6;
	};

	cpus {
		cpu@0 {
			compatible = "arm,cortex-a8";
		};
	};

	/*
	 * The soc node represents the soc top level view. It is uses for IPs
	 * that are not memory mapped in the MPU view or for the MPU itself.
	 */
	soc {
		compatible = "ti,omap-infra";
		mpu {
			compatible = "ti,omap3-mpu";
			ti,hwmods = "mpu";
		};
	};

	/*
	 * XXX: Use a flat representation of the AM33XX interconnect.
	 * The real AM33XX interconnect network is quite complex.Since
	 * that will not bring real advantage to represent that in DT
	 * for the moment, just use a fake OCP bus entry to represent
	 * the whole bus hierarchy.
	 */
	ocp {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;
		ti,hwmods = "l3_main";

		intc: interrupt-controller@48200000 {
			compatible = "ti,omap2-intc";
			interrupt-controller;
			#interrupt-cells = <1>;
			ti,intc-size = <128>;
			reg = <0x48200000 0x1000>;
		};

		gpio1: gpio@44e07000 {
			compatible = "ti,omap4-gpio";
			ti,hwmods = "gpio1";
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <1>;
			reg = <0x44e07000 0x1000>;
			interrupt-parent = <&intc>;
			interrupts = <96>;
		};

		gpio2: gpio@4804c000 {
			compatible = "ti,omap4-gpio";
			ti,hwmods = "gpio2";
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <1>;
			reg = <0x4804c000 0x1000>;
			interrupt-parent = <&intc>;
			interrupts = <98>;
		};

		gpio3: gpio@481ac000 {
			compatible = "ti,omap4-gpio";
			ti,hwmods = "gpio3";
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <1>;
			reg = <0x481ac000 0x1000>;
			interrupt-parent = <&intc>;
			interrupts = <32>;
		};

		gpio4: gpio@481ae000 {
			compatible = "ti,omap4-gpio";
			ti,hwmods = "gpio4";
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <1>;
			reg = <0x481ae000 0x1000>;
			interrupt-parent = <&intc>;
			interrupts = <62>;
		};

		uart1: serial@44e09000 {
			compatible = "ti,omap3-uart";
			ti,hwmods = "uart1";
			clock-frequency = <48000000>;
			reg = <0x44e09000 0x2000>;
			interrupt-parent = <&intc>;
			interrupts = <72>;
			status = "disabled";
		};

		uart2: serial@48022000 {
			compatible = "ti,omap3-uart";
			ti,hwmods = "uart2";
			clock-frequency = <48000000>;
			reg = <0x48022000 0x2000>;
			interrupt-parent = <&intc>;
			interrupts = <73>;
			status = "disabled";
		};

		uart3: serial@48024000 {
			compatible = "ti,omap3-uart";
			ti,hwmods = "uart3";
			clock-frequency = <48000000>;
			reg = <0x48024000 0x2000>;
			interrupt-parent = <&intc>;
			interrupts = <74>;
			status = "disabled";
		};

		uart4: serial@481a6000 {
			compatible = "ti,omap3-uart";
			ti,hwmods = "uart4";
			clock-frequency = <48000000>;
			reg = <0x481a6000 0x2000>;
			interrupt-parent = <&intc>;
			interrupts = <44>;
			status = "disabled";
		};

		uart5: serial@481a8000 {
			compatible = "ti,omap3-uart";
			ti,hwmods = "uart5";
			clock-frequency = <48000000>;
			reg = <0x481a8000 0x2000>;
			interrupt-parent = <&intc>;
			interrupts = <45>;
			status = "disabled";
		};

		uart6: serial@481aa000 {
			compatible = "ti,omap3-uart";
			ti,hwmods = "uart6";
			clock-frequency = <48000000>;
			reg = <0x481aa000 0x2000>;
			interrupt-parent = <&intc>;
			interrupts = <46>;
			status = "disabled";
		};

		i2c1: i2c@44e0b000 {
			compatible = "ti,omap4-i2c";
			#address-cells = <1>;
			#size-cells = <0>;
			ti,hwmods = "i2c1";
			reg = <0x44e0b000 0x1000>;
			interrupt-parent = <&intc>;
			interrupts = <70>;
			status = "disabled";
		};

		i2c2: i2c@4802a000 {
			compatible = "ti,omap4-i2c";
			#address-cells = <1>;
			#size-cells = <0>;
			ti,hwmods = "i2c2";
			reg = <0x4802a000 0x1000>;
			interrupt-parent = <&intc>;
			interrupts = <71>;
			status = "disabled";
		};

		i2c3: i2c@4819c000 {
			compatible = "ti,omap4-i2c";
			#address-cells = <1>;
			#size-cells = <0>;
			ti,hwmods = "i2c3";
			reg = <0x4819c000 0x1000>;
			interrupt-parent = <&intc>;
			interrupts = <30>;
			status = "disabled";
		};

		wdt2: wdt@44e35000 {
			compatible = "ti,omap3-wdt";
			ti,hwmods = "wd_timer2";
			reg = <0x44e35000 0x1000>;
			interrupt-parent = <&intc>;
			interrupts = <91>;
		};
	};
};
Commit	Line	Data
5fc0b42a AC	1	/*
	2	* Device Tree Source for AM33XX SoC
	3	*
	4	* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
	5	*
	6	* This file is licensed under the terms of the GNU General Public License
	7	* version 2. This program is licensed "as is" without any warranty of any
	8	* kind, whether express or implied.
	9	*/
	10
	11	/include/ "skeleton.dtsi"
	12
	13	/ {
	14	compatible = "ti,am33xx";
	15
	16	aliases {
	17	serial0 = &uart1;
	18	serial1 = &uart2;
	19	serial2 = &uart3;
	20	serial3 = &uart4;
	21	serial4 = &uart5;
	22	serial5 = &uart6;
	23	};
	24
	25	cpus {
	26	cpu@0 {
	27	compatible = "arm,cortex-a8";
	28	};
	29	};
	30
	31	/*
	32	* The soc node represents the soc top level view. It is uses for IPs
	33	* that are not memory mapped in the MPU view or for the MPU itself.
	34	*/
	35	soc {
	36	compatible = "ti,omap-infra";
	37	mpu {
	38	compatible = "ti,omap3-mpu";
	39	ti,hwmods = "mpu";
	40	};
	41	};
	42
	43	/*
	44	* XXX: Use a flat representation of the AM33XX interconnect.
	45	* The real AM33XX interconnect network is quite complex.Since
	46	* that will not bring real advantage to represent that in DT
	47	* for the moment, just use a fake OCP bus entry to represent
	48	* the whole bus hierarchy.
	49	*/
	50	ocp {
	51	compatible = "simple-bus";
	52	#address-cells = <1>;
	53	#size-cells = <1>;
	54	ranges;
	55	ti,hwmods = "l3_main";
	56
	57	intc: interrupt-controller@48200000 {
	58	compatible = "ti,omap2-intc";
	59	interrupt-controller;
	60	#interrupt-cells = <1>;
	61	ti,intc-size = <128>;
	62	reg = <0x48200000 0x1000>;
	63	};
	64
65	gpio1: gpio@44e07000 {
66	compatible = "ti,omap4-gpio";
67	ti,hwmods = "gpio1";
68	gpio-controller;
69	#gpio-cells = <2>;
70	interrupt-controller;
71	#interrupt-cells = <1>;
4462b31c VH	72	reg = <0x44e07000 0x1000>;
	73	interrupt-parent = <&intc>;
	74	interrupts = <96>;
5fc0b42a AC	75	};
5fc0b42a AC	76
5d83cb86	77	gpio2: gpio@4804c000 {
5fc0b42a AC	78	compatible = "ti,omap4-gpio";
	79	ti,hwmods = "gpio2";
	80	gpio-controller;
	81	#gpio-cells = <2>;
	82	interrupt-controller;
	83	#interrupt-cells = <1>;
4462b31c VH	84	reg = <0x4804c000 0x1000>;
	85	interrupt-parent = <&intc>;
	86	interrupts = <98>;
5fc0b42a AC	87	};
5fc0b42a AC	88
5d83cb86	89	gpio3: gpio@481ac000 {
5fc0b42a AC	90	compatible = "ti,omap4-gpio";
	91	ti,hwmods = "gpio3";
	92	gpio-controller;
	93	#gpio-cells = <2>;
	94	interrupt-controller;
	95	#interrupt-cells = <1>;
4462b31c VH	96	reg = <0x481ac000 0x1000>;
	97	interrupt-parent = <&intc>;
	98	interrupts = <32>;
5fc0b42a AC	99	};
5fc0b42a AC	100
5d83cb86	101	gpio4: gpio@481ae000 {
5fc0b42a AC	102	compatible = "ti,omap4-gpio";
	103	ti,hwmods = "gpio4";
	104	gpio-controller;
	105	#gpio-cells = <2>;
	106	interrupt-controller;
	107	#interrupt-cells = <1>;
4462b31c VH	108	reg = <0x481ae000 0x1000>;
	109	interrupt-parent = <&intc>;
	110	interrupts = <62>;
5fc0b42a AC	111	};
5fc0b42a AC	112
5d83cb86	113	uart1: serial@44e09000 {
5fc0b42a AC	114	compatible = "ti,omap3-uart";
	115	ti,hwmods = "uart1";
	116	clock-frequency = <48000000>;
4462b31c VH	117	reg = <0x44e09000 0x2000>;
	118	interrupt-parent = <&intc>;
	119	interrupts = <72>;
53d91034	120	status = "disabled";
5fc0b42a AC	121	};
	122
	123	uart2: serial@48022000 {
	124	compatible = "ti,omap3-uart";
	125	ti,hwmods = "uart2";
	126	clock-frequency = <48000000>;
4462b31c VH	127	reg = <0x48022000 0x2000>;
	128	interrupt-parent = <&intc>;
	129	interrupts = <73>;
53d91034	130	status = "disabled";
5fc0b42a AC	131	};
	132
	133	uart3: serial@48024000 {
	134	compatible = "ti,omap3-uart";
	135	ti,hwmods = "uart3";
	136	clock-frequency = <48000000>;
4462b31c VH	137	reg = <0x48024000 0x2000>;
	138	interrupt-parent = <&intc>;
	139	interrupts = <74>;
53d91034	140	status = "disabled";
5fc0b42a AC	141	};
5fc0b42a AC	142
5d83cb86	143	uart4: serial@481a6000 {
5fc0b42a AC	144	compatible = "ti,omap3-uart";
	145	ti,hwmods = "uart4";
	146	clock-frequency = <48000000>;
4462b31c VH	147	reg = <0x481a6000 0x2000>;
	148	interrupt-parent = <&intc>;
	149	interrupts = <44>;
53d91034	150	status = "disabled";
5fc0b42a AC	151	};
5fc0b42a AC	152
5d83cb86	153	uart5: serial@481a8000 {
5fc0b42a AC	154	compatible = "ti,omap3-uart";
	155	ti,hwmods = "uart5";
	156	clock-frequency = <48000000>;
4462b31c VH	157	reg = <0x481a8000 0x2000>;
	158	interrupt-parent = <&intc>;
	159	interrupts = <45>;
53d91034	160	status = "disabled";
5fc0b42a AC	161	};
5fc0b42a AC	162
5d83cb86	163	uart6: serial@481aa000 {
5fc0b42a AC	164	compatible = "ti,omap3-uart";
	165	ti,hwmods = "uart6";
	166	clock-frequency = <48000000>;
4462b31c VH	167	reg = <0x481aa000 0x2000>;
	168	interrupt-parent = <&intc>;
	169	interrupts = <46>;
53d91034	170	status = "disabled";
5fc0b42a AC	171	};
5fc0b42a AC	172
5d83cb86	173	i2c1: i2c@44e0b000 {
5fc0b42a AC	174	compatible = "ti,omap4-i2c";
	175	#address-cells = <1>;
	176	#size-cells = <0>;
	177	ti,hwmods = "i2c1";
4462b31c VH	178	reg = <0x44e0b000 0x1000>;
	179	interrupt-parent = <&intc>;
	180	interrupts = <70>;
53d91034	181	status = "disabled";
5fc0b42a AC	182	};
5fc0b42a AC	183
5d83cb86	184	i2c2: i2c@4802a000 {
5fc0b42a AC	185	compatible = "ti,omap4-i2c";
	186	#address-cells = <1>;
	187	#size-cells = <0>;
	188	ti,hwmods = "i2c2";
4462b31c VH	189	reg = <0x4802a000 0x1000>;
	190	interrupt-parent = <&intc>;
	191	interrupts = <71>;
53d91034	192	status = "disabled";
5fc0b42a AC	193	};
5fc0b42a AC	194
5d83cb86	195	i2c3: i2c@4819c000 {
5fc0b42a AC	196	compatible = "ti,omap4-i2c";
	197	#address-cells = <1>;
	198	#size-cells = <0>;
	199	ti,hwmods = "i2c3";
4462b31c VH	200	reg = <0x4819c000 0x1000>;
	201	interrupt-parent = <&intc>;
	202	interrupts = <30>;
53d91034	203	status = "disabled";
5fc0b42a	204	};
5f789ebc AM	205
	206	wdt2: wdt@44e35000 {
	207	compatible = "ti,omap3-wdt";
	208	ti,hwmods = "wd_timer2";
4462b31c VH	209	reg = <0x44e35000 0x1000>;
	210	interrupt-parent = <&intc>;
	211	interrupts = <91>;
5f789ebc	212	};
5fc0b42a AC	213	};
5fc0b42a AC	214	};