[deliverable/linux.git] / arch / arm / boot / dts / am33xx.dtsi

/*
 * Device Tree Source for AM33XX SoC
 *
 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
 *
 * This file is licensed under the terms of the GNU General Public License
 * version 2.  This program is licensed "as is" without any warranty of any
 * kind, whether express or implied.
 */

#include "skeleton.dtsi"

/ {
	compatible = "ti,am33xx";
	interrupt-parent = <&intc>;

	aliases {
		serial0 = &uart0;
		serial1 = &uart1;
		serial2 = &uart2;
		serial3 = &uart3;
		serial4 = &uart4;
		serial5 = &uart5;
		d_can0 = &dcan0;
		d_can1 = &dcan1;
	};

	cpus {
		cpu@0 {
			compatible = "arm,cortex-a8";

			/*
			 * To consider voltage drop between PMIC and SoC,
			 * tolerance value is reduced to 2% from 4% and
			 * voltage value is increased as a precaution.
			 */
			operating-points = <
				/* kHz    uV */
				720000  1285000
				600000  1225000
				500000  1125000
				275000  1125000
			>;
			voltage-tolerance = <2>; /* 2 percentage */
			clock-latency = <300000>; /* From omap-cpufreq driver */
		};
	};

	/*
	 * The soc node represents the soc top level view. It is uses for IPs
	 * that are not memory mapped in the MPU view or for the MPU itself.
	 */
	soc {
		compatible = "ti,omap-infra";
		mpu {
			compatible = "ti,omap3-mpu";
			ti,hwmods = "mpu";
		};
	};

	am33xx_pinmux: pinmux@44e10800 {
		compatible = "pinctrl-single";
		reg = <0x44e10800 0x0238>;
		#address-cells = <1>;
		#size-cells = <0>;
		pinctrl-single,register-width = <32>;
		pinctrl-single,function-mask = <0x7f>;
	};

	/*
	 * XXX: Use a flat representation of the AM33XX interconnect.
	 * The real AM33XX interconnect network is quite complex.Since
	 * that will not bring real advantage to represent that in DT
	 * for the moment, just use a fake OCP bus entry to represent
	 * the whole bus hierarchy.
	 */
	ocp {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;
		ti,hwmods = "l3_main";

		intc: interrupt-controller@48200000 {
			compatible = "ti,omap2-intc";
			interrupt-controller;
			#interrupt-cells = <1>;
			ti,intc-size = <128>;
			reg = <0x48200000 0x1000>;
		};

		gpio0: gpio@44e07000 {
			compatible = "ti,omap4-gpio";
			ti,hwmods = "gpio1";
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <1>;
			reg = <0x44e07000 0x1000>;
			interrupts = <96>;
		};

		gpio1: gpio@4804c000 {
			compatible = "ti,omap4-gpio";
			ti,hwmods = "gpio2";
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <1>;
			reg = <0x4804c000 0x1000>;
			interrupts = <98>;
		};

		gpio2: gpio@481ac000 {
			compatible = "ti,omap4-gpio";
			ti,hwmods = "gpio3";
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <1>;
			reg = <0x481ac000 0x1000>;
			interrupts = <32>;
		};

		gpio3: gpio@481ae000 {
			compatible = "ti,omap4-gpio";
			ti,hwmods = "gpio4";
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <1>;
			reg = <0x481ae000 0x1000>;
			interrupts = <62>;
		};

		uart0: serial@44e09000 {
			compatible = "ti,omap3-uart";
			ti,hwmods = "uart1";
			clock-frequency = <48000000>;
			reg = <0x44e09000 0x2000>;
			interrupts = <72>;
			status = "disabled";
		};

		uart1: serial@48022000 {
			compatible = "ti,omap3-uart";
			ti,hwmods = "uart2";
			clock-frequency = <48000000>;
			reg = <0x48022000 0x2000>;
			interrupts = <73>;
			status = "disabled";
		};

		uart2: serial@48024000 {
			compatible = "ti,omap3-uart";
			ti,hwmods = "uart3";
			clock-frequency = <48000000>;
			reg = <0x48024000 0x2000>;
			interrupts = <74>;
			status = "disabled";
		};

		uart3: serial@481a6000 {
			compatible = "ti,omap3-uart";
			ti,hwmods = "uart4";
			clock-frequency = <48000000>;
			reg = <0x481a6000 0x2000>;
			interrupts = <44>;
			status = "disabled";
		};

		uart4: serial@481a8000 {
			compatible = "ti,omap3-uart";
			ti,hwmods = "uart5";
			clock-frequency = <48000000>;
			reg = <0x481a8000 0x2000>;
			interrupts = <45>;
			status = "disabled";
		};

		uart5: serial@481aa000 {
			compatible = "ti,omap3-uart";
			ti,hwmods = "uart6";
			clock-frequency = <48000000>;
			reg = <0x481aa000 0x2000>;
			interrupts = <46>;
			status = "disabled";
		};

		i2c0: i2c@44e0b000 {
			compatible = "ti,omap4-i2c";
			#address-cells = <1>;
			#size-cells = <0>;
			ti,hwmods = "i2c1";
			reg = <0x44e0b000 0x1000>;
			interrupts = <70>;
			status = "disabled";
		};

		i2c1: i2c@4802a000 {
			compatible = "ti,omap4-i2c";
			#address-cells = <1>;
			#size-cells = <0>;
			ti,hwmods = "i2c2";
			reg = <0x4802a000 0x1000>;
			interrupts = <71>;
			status = "disabled";
		};

		i2c2: i2c@4819c000 {
			compatible = "ti,omap4-i2c";
			#address-cells = <1>;
			#size-cells = <0>;
			ti,hwmods = "i2c3";
			reg = <0x4819c000 0x1000>;
			interrupts = <30>;
			status = "disabled";
		};

		wdt2: wdt@44e35000 {
			compatible = "ti,omap3-wdt";
			ti,hwmods = "wd_timer2";
			reg = <0x44e35000 0x1000>;
			interrupts = <91>;
		};

		dcan0: d_can@481cc000 {
			compatible = "bosch,d_can";
			ti,hwmods = "d_can0";
			reg = <0x481cc000 0x2000
				0x44e10644 0x4>;
			interrupts = <52>;
			status = "disabled";
		};

		dcan1: d_can@481d0000 {
			compatible = "bosch,d_can";
			ti,hwmods = "d_can1";
			reg = <0x481d0000 0x2000
				0x44e10644 0x4>;
			interrupts = <55>;
			status = "disabled";
		};

		timer1: timer@44e31000 {
			compatible = "ti,am335x-timer-1ms";
			reg = <0x44e31000 0x400>;
			interrupts = <67>;
			ti,hwmods = "timer1";
			ti,timer-alwon;
		};

		timer2: timer@48040000 {
			compatible = "ti,am335x-timer";
			reg = <0x48040000 0x400>;
			interrupts = <68>;
			ti,hwmods = "timer2";
		};

		timer3: timer@48042000 {
			compatible = "ti,am335x-timer";
			reg = <0x48042000 0x400>;
			interrupts = <69>;
			ti,hwmods = "timer3";
		};

		timer4: timer@48044000 {
			compatible = "ti,am335x-timer";
			reg = <0x48044000 0x400>;
			interrupts = <92>;
			ti,hwmods = "timer4";
			ti,timer-pwm;
		};

		timer5: timer@48046000 {
			compatible = "ti,am335x-timer";
			reg = <0x48046000 0x400>;
			interrupts = <93>;
			ti,hwmods = "timer5";
			ti,timer-pwm;
		};

		timer6: timer@48048000 {
			compatible = "ti,am335x-timer";
			reg = <0x48048000 0x400>;
			interrupts = <94>;
			ti,hwmods = "timer6";
			ti,timer-pwm;
		};

		timer7: timer@4804a000 {
			compatible = "ti,am335x-timer";
			reg = <0x4804a000 0x400>;
			interrupts = <95>;
			ti,hwmods = "timer7";
			ti,timer-pwm;
		};

		rtc@44e3e000 {
			compatible = "ti,da830-rtc";
			reg = <0x44e3e000 0x1000>;
			interrupts = <75
				      76>;
			ti,hwmods = "rtc";
		};

		spi0: spi@48030000 {
			compatible = "ti,omap4-mcspi";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x48030000 0x400>;
			interrupts = <65>;
			ti,spi-num-cs = <2>;
			ti,hwmods = "spi0";
			status = "disabled";
		};

		spi1: spi@481a0000 {
			compatible = "ti,omap4-mcspi";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x481a0000 0x400>;
			interrupts = <125>;
			ti,spi-num-cs = <2>;
			ti,hwmods = "spi1";
			status = "disabled";
		};

		usb@47400000 {
			compatible = "ti,musb-am33xx";
			reg = <0x47400000 0x1000	/* usbss */
			       0x47401000 0x800		/* musb instance 0 */
			       0x47401800 0x800>;	/* musb instance 1 */
			interrupts = <17		/* usbss */
				      18		/* musb instance 0 */
				      19>;		/* musb instance 1 */
			multipoint = <1>;
			num-eps = <16>;
			ram-bits = <12>;
			port0-mode = <3>;
			port1-mode = <3>;
			power = <250>;
			ti,hwmods = "usb_otg_hs";
		};

		mac: ethernet@4a100000 {
			compatible = "ti,cpsw";
			ti,hwmods = "cpgmac0";
			cpdma_channels = <8>;
			ale_entries = <1024>;
			bd_ram_size = <0x2000>;
			no_bd_ram = <0>;
			rx_descs = <64>;
			mac_control = <0x20>;
			slaves = <2>;
			active_slave = <0>;
			cpts_clock_mult = <0x80000000>;
			cpts_clock_shift = <29>;
			reg = <0x4a100000 0x800
			       0x4a101200 0x100>;
			#address-cells = <1>;
			#size-cells = <1>;
			interrupt-parent = <&intc>;
			/*
			 * c0_rx_thresh_pend
			 * c0_rx_pend
			 * c0_tx_pend
			 * c0_misc_pend
			 */
			interrupts = <40 41 42 43>;
			ranges;

			davinci_mdio: mdio@4a101000 {
				compatible = "ti,davinci_mdio";
				#address-cells = <1>;
				#size-cells = <0>;
				ti,hwmods = "davinci_mdio";
				bus_freq = <1000000>;
				reg = <0x4a101000 0x100>;
			};

			cpsw_emac0: slave@4a100200 {
				/* Filled in by U-Boot */
				mac-address = [ 00 00 00 00 00 00 ];
			};

			cpsw_emac1: slave@4a100300 {
				/* Filled in by U-Boot */
				mac-address = [ 00 00 00 00 00 00 ];
			};
		};

		ocmcram: ocmcram@40300000 {
			compatible = "ti,am3352-ocmcram";
			reg = <0x40300000 0x10000>;
			ti,hwmods = "ocmcram";
			ti,no_idle_on_suspend;
		};

		wkup_m3: wkup_m3@44d00000 {
			compatible = "ti,am3353-wkup-m3";
			reg = <0x44d00000 0x4000	/* M3 UMEM */
			       0x44d80000 0x2000>;	/* M3 DMEM */
			ti,hwmods = "wkup_m3";
		};

		elm: elm@48080000 {
			compatible = "ti,am3352-elm";
			reg = <0x48080000 0x2000>;
			interrupts = <4>;
			ti,hwmods = "elm";
			status = "disabled";
		};

		gpmc: gpmc@50000000 {
			compatible = "ti,am3352-gpmc";
			ti,hwmods = "gpmc";
			reg = <0x50000000 0x2000>;
			interrupts = <100>;
			gpmc,num-cs = <7>;
			gpmc,num-waitpins = <2>;
			#address-cells = <2>;
			#size-cells = <1>;
			status = "disabled";
		};
	};
};
Commit	Line	Data
5fc0b42a AC	1	/*
	2	* Device Tree Source for AM33XX SoC
	3	*
	4	* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
	5	*
	6	* This file is licensed under the terms of the GNU General Public License
	7	* version 2. This program is licensed "as is" without any warranty of any
	8	* kind, whether express or implied.
	9	*/
	10
eb33ef66	11	#include "skeleton.dtsi"
5fc0b42a AC	12
	13	/ {
	14	compatible = "ti,am33xx";
4c94ac29	15	interrupt-parent = <&intc>;
5fc0b42a AC	16
5fc0b42a AC	17	aliases {
dde3b0d6 VH	18	serial0 = &uart0;
	19	serial1 = &uart1;
	20	serial2 = &uart2;
	21	serial3 = &uart3;
	22	serial4 = &uart4;
	23	serial5 = &uart5;
7a57ee87 AC	24	d_can0 = &dcan0;
7a57ee87 AC	25	d_can1 = &dcan1;
5fc0b42a AC	26	};
	27
	28	cpus {
	29	cpu@0 {
	30	compatible = "arm,cortex-a8";
efeedcf2 AC	31
	32	/*
	33	* To consider voltage drop between PMIC and SoC,
	34	* tolerance value is reduced to 2% from 4% and
	35	* voltage value is increased as a precaution.
	36	*/
	37	operating-points = <
	38	/* kHz uV */
	39	720000 1285000
	40	600000 1225000
	41	500000 1125000
	42	275000 1125000
	43	>;
	44	voltage-tolerance = <2>; /* 2 percentage */
	45	clock-latency = <300000>; /* From omap-cpufreq driver */
5fc0b42a AC	46	};
	47	};
	48
	49	/*
	50	* The soc node represents the soc top level view. It is uses for IPs
	51	* that are not memory mapped in the MPU view or for the MPU itself.
	52	*/
	53	soc {
	54	compatible = "ti,omap-infra";
	55	mpu {
	56	compatible = "ti,omap3-mpu";
	57	ti,hwmods = "mpu";
	58	};
	59	};
	60
b552dfc4 AC	61	am33xx_pinmux: pinmux@44e10800 {
	62	compatible = "pinctrl-single";
	63	reg = <0x44e10800 0x0238>;
	64	#address-cells = <1>;
	65	#size-cells = <0>;
	66	pinctrl-single,register-width = <32>;
	67	pinctrl-single,function-mask = <0x7f>;
	68	};
	69
5fc0b42a AC	70	/*
	71	* XXX: Use a flat representation of the AM33XX interconnect.
	72	* The real AM33XX interconnect network is quite complex.Since
	73	* that will not bring real advantage to represent that in DT
	74	* for the moment, just use a fake OCP bus entry to represent
	75	* the whole bus hierarchy.
	76	*/
	77	ocp {
	78	compatible = "simple-bus";
	79	#address-cells = <1>;
	80	#size-cells = <1>;
	81	ranges;
	82	ti,hwmods = "l3_main";
	83
	84	intc: interrupt-controller@48200000 {
	85	compatible = "ti,omap2-intc";
	86	interrupt-controller;
	87	#interrupt-cells = <1>;
	88	ti,intc-size = <128>;
	89	reg = <0x48200000 0x1000>;
	90	};
	91
b918e2c0	92	gpio0: gpio@44e07000 {
5fc0b42a AC	93	compatible = "ti,omap4-gpio";
	94	ti,hwmods = "gpio1";
	95	gpio-controller;
	96	#gpio-cells = <2>;
	97	interrupt-controller;
	98	#interrupt-cells = <1>;
4462b31c	99	reg = <0x44e07000 0x1000>;
4462b31c	100	interrupts = <96>;
5fc0b42a AC	101	};
5fc0b42a AC	102
b918e2c0	103	gpio1: gpio@4804c000 {
5fc0b42a AC	104	compatible = "ti,omap4-gpio";
	105	ti,hwmods = "gpio2";
	106	gpio-controller;
	107	#gpio-cells = <2>;
	108	interrupt-controller;
	109	#interrupt-cells = <1>;
4462b31c	110	reg = <0x4804c000 0x1000>;
4462b31c	111	interrupts = <98>;
5fc0b42a AC	112	};
5fc0b42a AC	113
b918e2c0	114	gpio2: gpio@481ac000 {
5fc0b42a AC	115	compatible = "ti,omap4-gpio";
	116	ti,hwmods = "gpio3";
	117	gpio-controller;
	118	#gpio-cells = <2>;
	119	interrupt-controller;
	120	#interrupt-cells = <1>;
4462b31c	121	reg = <0x481ac000 0x1000>;
4462b31c	122	interrupts = <32>;
5fc0b42a AC	123	};
5fc0b42a AC	124
b918e2c0	125	gpio3: gpio@481ae000 {
5fc0b42a AC	126	compatible = "ti,omap4-gpio";
	127	ti,hwmods = "gpio4";
	128	gpio-controller;
	129	#gpio-cells = <2>;
	130	interrupt-controller;
	131	#interrupt-cells = <1>;
4462b31c	132	reg = <0x481ae000 0x1000>;
4462b31c	133	interrupts = <62>;
5fc0b42a AC	134	};
5fc0b42a AC	135
dde3b0d6	136	uart0: serial@44e09000 {
5fc0b42a AC	137	compatible = "ti,omap3-uart";
	138	ti,hwmods = "uart1";
	139	clock-frequency = <48000000>;
4462b31c	140	reg = <0x44e09000 0x2000>;
4462b31c	141	interrupts = <72>;
53d91034	142	status = "disabled";
5fc0b42a AC	143	};
5fc0b42a AC	144
dde3b0d6	145	uart1: serial@48022000 {
5fc0b42a AC	146	compatible = "ti,omap3-uart";
	147	ti,hwmods = "uart2";
	148	clock-frequency = <48000000>;
4462b31c	149	reg = <0x48022000 0x2000>;
4462b31c	150	interrupts = <73>;
53d91034	151	status = "disabled";
5fc0b42a AC	152	};
5fc0b42a AC	153
dde3b0d6	154	uart2: serial@48024000 {
5fc0b42a AC	155	compatible = "ti,omap3-uart";
	156	ti,hwmods = "uart3";
	157	clock-frequency = <48000000>;
4462b31c	158	reg = <0x48024000 0x2000>;
4462b31c	159	interrupts = <74>;
53d91034	160	status = "disabled";
5fc0b42a AC	161	};
5fc0b42a AC	162
dde3b0d6	163	uart3: serial@481a6000 {
5fc0b42a AC	164	compatible = "ti,omap3-uart";
	165	ti,hwmods = "uart4";
	166	clock-frequency = <48000000>;
4462b31c	167	reg = <0x481a6000 0x2000>;
4462b31c	168	interrupts = <44>;
53d91034	169	status = "disabled";
5fc0b42a AC	170	};
5fc0b42a AC	171
dde3b0d6	172	uart4: serial@481a8000 {
5fc0b42a AC	173	compatible = "ti,omap3-uart";
	174	ti,hwmods = "uart5";
	175	clock-frequency = <48000000>;
4462b31c	176	reg = <0x481a8000 0x2000>;
4462b31c	177	interrupts = <45>;
53d91034	178	status = "disabled";
5fc0b42a AC	179	};
5fc0b42a AC	180
dde3b0d6	181	uart5: serial@481aa000 {
5fc0b42a AC	182	compatible = "ti,omap3-uart";
	183	ti,hwmods = "uart6";
	184	clock-frequency = <48000000>;
4462b31c	185	reg = <0x481aa000 0x2000>;
4462b31c	186	interrupts = <46>;
53d91034	187	status = "disabled";
5fc0b42a AC	188	};
5fc0b42a AC	189
b918e2c0	190	i2c0: i2c@44e0b000 {
5fc0b42a AC	191	compatible = "ti,omap4-i2c";
	192	#address-cells = <1>;
	193	#size-cells = <0>;
	194	ti,hwmods = "i2c1";
4462b31c	195	reg = <0x44e0b000 0x1000>;
4462b31c	196	interrupts = <70>;
53d91034	197	status = "disabled";
5fc0b42a AC	198	};
5fc0b42a AC	199
b918e2c0	200	i2c1: i2c@4802a000 {
5fc0b42a AC	201	compatible = "ti,omap4-i2c";
	202	#address-cells = <1>;
	203	#size-cells = <0>;
	204	ti,hwmods = "i2c2";
4462b31c	205	reg = <0x4802a000 0x1000>;
4462b31c	206	interrupts = <71>;
53d91034	207	status = "disabled";
5fc0b42a AC	208	};
5fc0b42a AC	209
b918e2c0	210	i2c2: i2c@4819c000 {
5fc0b42a AC	211	compatible = "ti,omap4-i2c";
	212	#address-cells = <1>;
	213	#size-cells = <0>;
	214	ti,hwmods = "i2c3";
4462b31c	215	reg = <0x4819c000 0x1000>;
4462b31c	216	interrupts = <30>;
53d91034	217	status = "disabled";
5fc0b42a	218	};
5f789ebc AM	219
	220	wdt2: wdt@44e35000 {
	221	compatible = "ti,omap3-wdt";
	222	ti,hwmods = "wd_timer2";
4462b31c	223	reg = <0x44e35000 0x1000>;
4462b31c	224	interrupts = <91>;
5f789ebc	225	};
059b185d AC	226
	227	dcan0: d_can@481cc000 {
	228	compatible = "bosch,d_can";
	229	ti,hwmods = "d_can0";
f178c015 AC	230	reg = <0x481cc000 0x2000
f178c015 AC	231	0x44e10644 0x4>;
059b185d	232	interrupts = <52>;
059b185d AC	233	status = "disabled";
	234	};
	235
	236	dcan1: d_can@481d0000 {
	237	compatible = "bosch,d_can";
	238	ti,hwmods = "d_can1";
f178c015 AC	239	reg = <0x481d0000 0x2000
f178c015 AC	240	0x44e10644 0x4>;
059b185d	241	interrupts = <55>;
059b185d AC	242	status = "disabled";
059b185d AC	243	};
fab8ad0b JH	244
fab8ad0b JH	245	timer1: timer@44e31000 {
002e1ec5	246	compatible = "ti,am335x-timer-1ms";
fab8ad0b JH	247	reg = <0x44e31000 0x400>;
	248	interrupts = <67>;
	249	ti,hwmods = "timer1";
	250	ti,timer-alwon;
	251	};
	252
	253	timer2: timer@48040000 {
002e1ec5	254	compatible = "ti,am335x-timer";
fab8ad0b JH	255	reg = <0x48040000 0x400>;
	256	interrupts = <68>;
	257	ti,hwmods = "timer2";
	258	};
	259
	260	timer3: timer@48042000 {
002e1ec5	261	compatible = "ti,am335x-timer";
fab8ad0b JH	262	reg = <0x48042000 0x400>;
	263	interrupts = <69>;
	264	ti,hwmods = "timer3";
	265	};
	266
	267	timer4: timer@48044000 {
002e1ec5	268	compatible = "ti,am335x-timer";
fab8ad0b JH	269	reg = <0x48044000 0x400>;
	270	interrupts = <92>;
	271	ti,hwmods = "timer4";
	272	ti,timer-pwm;
	273	};
	274
	275	timer5: timer@48046000 {
002e1ec5	276	compatible = "ti,am335x-timer";
fab8ad0b JH	277	reg = <0x48046000 0x400>;
	278	interrupts = <93>;
	279	ti,hwmods = "timer5";
	280	ti,timer-pwm;
	281	};
	282
	283	timer6: timer@48048000 {
002e1ec5	284	compatible = "ti,am335x-timer";
fab8ad0b JH	285	reg = <0x48048000 0x400>;
	286	interrupts = <94>;
	287	ti,hwmods = "timer6";
	288	ti,timer-pwm;
	289	};
	290
	291	timer7: timer@4804a000 {
002e1ec5	292	compatible = "ti,am335x-timer";
fab8ad0b JH	293	reg = <0x4804a000 0x400>;
	294	interrupts = <95>;
	295	ti,hwmods = "timer7";
	296	ti,timer-pwm;
	297	};
0d935c16 AM	298
	299	rtc@44e3e000 {
	300	compatible = "ti,da830-rtc";
	301	reg = <0x44e3e000 0x1000>;
	302	interrupts = <75
	303	76>;
	304	ti,hwmods = "rtc";
	305	};
9fd3c748 PA	306
	307	spi0: spi@48030000 {
	308	compatible = "ti,omap4-mcspi";
	309	#address-cells = <1>;
	310	#size-cells = <0>;
	311	reg = <0x48030000 0x400>;
7b3754c6	312	interrupts = <65>;
9fd3c748 PA	313	ti,spi-num-cs = <2>;
	314	ti,hwmods = "spi0";
	315	status = "disabled";
	316	};
	317
	318	spi1: spi@481a0000 {
	319	compatible = "ti,omap4-mcspi";
	320	#address-cells = <1>;
	321	#size-cells = <0>;
	322	reg = <0x481a0000 0x400>;
7b3754c6	323	interrupts = <125>;
9fd3c748 PA	324	ti,spi-num-cs = <2>;
	325	ti,hwmods = "spi1";
	326	status = "disabled";
	327	};
35b47fbb AKG	328
	329	usb@47400000 {
	330	compatible = "ti,musb-am33xx";
	331	reg = <0x47400000 0x1000 /* usbss */
	332	0x47401000 0x800 /* musb instance 0 */
	333	0x47401800 0x800>; /* musb instance 1 */
	334	interrupts = <17 /* usbss */
	335	18 /* musb instance 0 */
	336	19>; /* musb instance 1 */
	337	multipoint = <1>;
	338	num-eps = <16>;
	339	ram-bits = <12>;
	340	port0-mode = <3>;
	341	port1-mode = <3>;
	342	power = <250>;
	343	ti,hwmods = "usb_otg_hs";
	344	};
6be35c70	345
1a39a65c M	346	mac: ethernet@4a100000 {
	347	compatible = "ti,cpsw";
	348	ti,hwmods = "cpgmac0";
	349	cpdma_channels = <8>;
	350	ale_entries = <1024>;
	351	bd_ram_size = <0x2000>;
	352	no_bd_ram = <0>;
	353	rx_descs = <64>;
	354	mac_control = <0x20>;
	355	slaves = <2>;
e86ac13b	356	active_slave = <0>;
1a39a65c M	357	cpts_clock_mult = <0x80000000>;
	358	cpts_clock_shift = <29>;
	359	reg = <0x4a100000 0x800
	360	0x4a101200 0x100>;
	361	#address-cells = <1>;
	362	#size-cells = <1>;
	363	interrupt-parent = <&intc>;
	364	/*
	365	* c0_rx_thresh_pend
	366	* c0_rx_pend
	367	* c0_tx_pend
	368	* c0_misc_pend
	369	*/
	370	interrupts = <40 41 42 43>;
	371	ranges;
	372
	373	davinci_mdio: mdio@4a101000 {
	374	compatible = "ti,davinci_mdio";
	375	#address-cells = <1>;
	376	#size-cells = <0>;
	377	ti,hwmods = "davinci_mdio";
	378	bus_freq = <1000000>;
	379	reg = <0x4a101000 0x100>;
	380	};
	381
	382	cpsw_emac0: slave@4a100200 {
	383	/* Filled in by U-Boot */
	384	mac-address = [ 00 00 00 00 00 00 ];
	385	};
	386
	387	cpsw_emac1: slave@4a100300 {
	388	/* Filled in by U-Boot */
	389	mac-address = [ 00 00 00 00 00 00 ];
	390	};
1a39a65c	391	};
f6575c90 VB	392
	393	ocmcram: ocmcram@40300000 {
	394	compatible = "ti,am3352-ocmcram";
	395	reg = <0x40300000 0x10000>;
	396	ti,hwmods = "ocmcram";
	397	ti,no_idle_on_suspend;
	398	};
	399
	400	wkup_m3: wkup_m3@44d00000 {
	401	compatible = "ti,am3353-wkup-m3";
	402	reg = <0x44d00000 0x4000 /* M3 UMEM */
	403	0x44d80000 0x2000>; /* M3 DMEM */
	404	ti,hwmods = "wkup_m3";
	405	};
e45879ec	406
15e8246b PA	407	elm: elm@48080000 {
	408	compatible = "ti,am3352-elm";
	409	reg = <0x48080000 0x2000>;
	410	interrupts = <4>;
	411	ti,hwmods = "elm";
	412	status = "disabled";
	413	};
	414
e45879ec PA	415	gpmc: gpmc@50000000 {
	416	compatible = "ti,am3352-gpmc";
	417	ti,hwmods = "gpmc";
	418	reg = <0x50000000 0x2000>;
	419	interrupts = <100>;
00dddcaa LP	420	gpmc,num-cs = <7>;
00dddcaa LP	421	gpmc,num-waitpins = <2>;
e45879ec PA	422	#address-cells = <2>;
	423	#size-cells = <1>;
	424	status = "disabled";
	425	};
5fc0b42a AC	426	};
5fc0b42a AC	427	};