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Merge remote-tracking branch 'spi/for-next'
[deliverable/linux.git] / arch / arm / boot / dts / am4372.dtsi
CommitLineData
6cfd8117
AM		 1/*
2 * Device Tree Source for AM4372 SoC
3 *
4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
d2885dbb 11#include <dt-bindings/gpio/gpio.h>
6cfd8117
AM		 12#include <dt-bindings/interrupt-controller/arm-gic.h>
13
6cfd8117
AM		 14/ {
15 compatible = "ti,am4372", "ti,am43";
7136d457 16 interrupt-parent = <&wakeupgen>;
75813028
JMC		 17 #address-cells = <1>;
18 #size-cells = <1>;
6cfd8117 19
9194cf4d 20 memory@0 {
75813028
JMC		 21 device_type = "memory";
22 reg = <0 0>;
23 };
6cfd8117
AM		 24
25 aliases {
6a968678
NM		 26 i2c0 = &i2c0;
27 i2c1 = &i2c1;
28 i2c2 = &i2c2;
6cfd8117 29 serial0 = &uart0;
71256d9d
SN		 30 serial1 = &uart1;
31 serial2 = &uart2;
32 serial3 = &uart3;
33 serial4 = &uart4;
34 serial5 = &uart5;
9e3269b8
LV		 35 ethernet0 = &cpsw_emac0;
36 ethernet1 = &cpsw_emac1;
e05edea4 37 spi0 = &qspi;
6cfd8117
AM		 38 };
39
40 cpus {
738c7409
AM		 41 #address-cells = <1>;
42 #size-cells = <0>;
08ecb28a 43 cpu: cpu@0 {
6cfd8117 44 compatible = "arm,cortex-a9";
738c7409
AM		 45 device_type = "cpu";
46 reg = <0>;
8d766fa2
NM		 47
48 clocks = <&dpll_mpu_ck>;
49 clock-names = "cpu";
50
6da9c792
DG		 51 operating-points-v2 = <&cpu0_opp_table>;
52 ti,syscon-efuse = <&scm_conf 0x610 0x3f 0>;
53 ti,syscon-rev = <&scm_conf 0x600>;
54
8d766fa2 55 clock-latency = <300000>; /* From omap-cpufreq driver */
6cfd8117
AM		 56 };
57 };
58
6da9c792
DG		 59 cpu0_opp_table: opp_table0 {
60 compatible = "operating-points-v2";
61
62 opp50@300000000 {
63 opp-hz = /bits/ 64 <300000000>;
64 opp-microvolt = <950000 931000 969000>;
65 opp-supported-hw = <0xFF 0x01>;
66 opp-suspend;
67 };
68
69 opp100@600000000 {
70 opp-hz = /bits/ 64 <600000000>;
71 opp-microvolt = <1100000 1078000 1122000>;
72 opp-supported-hw = <0xFF 0x04>;
73 };
74
75 opp120@720000000 {
76 opp-hz = /bits/ 64 <720000000>;
77 opp-microvolt = <1200000 1176000 1224000>;
78 opp-supported-hw = <0xFF 0x08>;
79 };
80
81 oppturbo@800000000 {
82 opp-hz = /bits/ 64 <800000000>;
83 opp-microvolt = <1260000 1234800 1285200>;
84 opp-supported-hw = <0xFF 0x10>;
85 };
86
87 oppnitro@1000000000 {
88 opp-hz = /bits/ 64 <1000000000>;
89 opp-microvolt = <1325000 1298500 1351500>;
90 opp-supported-hw = <0xFF 0x20>;
91 };
92 };
93
6cfd8117
AM		 94 gic: interrupt-controller@48241000 {
95 compatible = "arm,cortex-a9-gic";
96 interrupt-controller;
97 #interrupt-cells = <3>;
98 reg = <0x48241000 0x1000>,
99 <0x48240100 0x0100>;
7136d457
MZ		 100 interrupt-parent = <&gic>;
101 };
102
103 wakeupgen: interrupt-controller@48281000 {
104 compatible = "ti,omap4-wugen-mpu";
105 interrupt-controller;
106 #interrupt-cells = <3>;
107 reg = <0x48281000 0x1000>;
108 interrupt-parent = <&gic>;
6cfd8117
AM		 109 };
110
8cbd4c2f
FB		 111 scu: scu@48240000 {
112 compatible = "arm,cortex-a9-scu";
113 reg = <0x48240000 0x100>;
114 };
115
116 global_timer: timer@48240200 {
117 compatible = "arm,cortex-a9-global-timer";
118 reg = <0x48240200 0x100>;
84fb225a 119 interrupts = <GIC_PPI 11 IRQ_TYPE_EDGE_RISING>;
8cbd4c2f 120 interrupt-parent = <&gic>;
14054fb1 121 clocks = <&mpu_periphclk>;
8cbd4c2f
FB		 122 };
123
124 local_timer: timer@48240600 {
125 compatible = "arm,cortex-a9-twd-timer";
126 reg = <0x48240600 0x100>;
84fb225a 127 interrupts = <GIC_PPI 13 IRQ_TYPE_EDGE_RISING>;
8cbd4c2f 128 interrupt-parent = <&gic>;
14054fb1 129 clocks = <&mpu_periphclk>;
8cbd4c2f
FB		 130 };
131
9e3269b8
LV		 132 l2-cache-controller@48242000 {
133 compatible = "arm,pl310-cache";
134 reg = <0x48242000 0x1000>;
135 cache-unified;
136 cache-level = <2>;
137 };
138
f515f814 139 ocp@44000000 {
2eeddb8a 140 compatible = "ti,am4372-l3-noc", "simple-bus";
6cfd8117
AM		 141 #address-cells = <1>;
142 #size-cells = <1>;
143 ranges;
9e3269b8 144 ti,hwmods = "l3_main";
2eeddb8a
AM		 145 reg = <0x44000000 0x400000
146 0x44800000 0x400000>;
147 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
148 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
9e3269b8 149
83a5d6c9
TK		 150 l4_wkup: l4_wkup@44c00000 {
151 compatible = "ti,am4-l4-wkup", "simple-bus";
152 #address-cells = <1>;
153 #size-cells = <1>;
154 ranges = <0 0x44c00000 0x287000>;
6a679208 155
34020422
SA		 156 wkup_m3: wkup_m3@100000 {
157 compatible = "ti,am4372-wkup-m3";
158 reg = <0x100000 0x4000>,
159 <0x180000 0x2000>;
160 reg-names = "umem", "dmem";
161 ti,hwmods = "wkup_m3";
162 ti,pm-firmware = "am335x-pm-firmware.elf";
163 };
164
83a5d6c9
TK		 165 prcm: prcm@1f0000 {
166 compatible = "ti,am4-prcm";
167 reg = <0x1f0000 0x11000>;
6e487001 168 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
6a679208 169
83a5d6c9
TK		 170 prcm_clocks: clocks {
171 #address-cells = <1>;
172 #size-cells = <0>;
173 };
6a679208 174
83a5d6c9
TK		 175 prcm_clockdomains: clockdomains {
176 };
6a679208
TK		 177 };
178
83a5d6c9
TK		 179 scm: scm@210000 {
180 compatible = "ti,am4-scm", "simple-bus";
181 reg = <0x210000 0x4000>;
182 #address-cells = <1>;
183 #size-cells = <1>;
184 ranges = <0 0x210000 0x4000>;
185
186 am43xx_pinmux: pinmux@800 {
187 compatible = "ti,am437-padconf",
188 "pinctrl-single";
189 reg = <0x800 0x31c>;
190 #address-cells = <1>;
191 #size-cells = <0>;
192 #interrupt-cells = <1>;
193 interrupt-controller;
194 pinctrl-single,register-width = <32>;
195 pinctrl-single,function-mask = <0xffffffff>;
196 };
197
198 scm_conf: scm_conf@0 {
199 compatible = "syscon";
200 reg = <0x0 0x800>;
201 #address-cells = <1>;
202 #size-cells = <1>;
203
204 scm_clocks: clocks {
205 #address-cells = <1>;
206 #size-cells = <0>;
207 };
208 };
209
c9ab94df
SA		 210 wkup_m3_ipc: wkup_m3_ipc@1324 {
211 compatible = "ti,am4372-wkup-m3-ipc";
212 reg = <0x1324 0x44>;
213 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
214 ti,rproc = <&wkup_m3>;
215 mboxes = <&mailbox &mbox_wkupm3>;
216 };
217
cce1ee00
PU		 218 edma_xbar: dma-router@f90 {
219 compatible = "ti,am335x-edma-crossbar";
220 reg = <0xf90 0x40>;
221 #dma-cells = <3>;
222 dma-requests = <64>;
223 dma-masters = <&edma>;
224 };
225
83a5d6c9
TK		 226 scm_clockdomains: clockdomains {
227 };
6a679208
TK		 228 };
229 };
230
fff75ee1
DG		 231 emif: emif@4c000000 {
232 compatible = "ti,emif-am4372";
233 reg = <0x4c000000 0x1000000>;
234 ti,hwmods = "emif";
235 };
236
9e3269b8 237 edma: edma@49000000 {
cce1ee00
PU		 238 compatible = "ti,edma3-tpcc";
239 ti,hwmods = "tpcc";
240 reg = <0x49000000 0x10000>;
241 reg-names = "edma3_cc";
9e3269b8 242 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
cce1ee00
PU		 243 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
244 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
a5206553 245 interrupt-names = "edma3_ccint", "edma3_mperr",
cce1ee00
PU		 246 "edma3_ccerrint";
247 dma-requests = <64>;
248 #dma-cells = <2>;
249
250 ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>,
251 <&edma_tptc2 0>;
252
d41676dd 253 ti,edma-memcpy-channels = <58 59>;
cce1ee00
PU		 254 };
255
256 edma_tptc0: tptc@49800000 {
257 compatible = "ti,edma3-tptc";
258 ti,hwmods = "tptc0";
259 reg = <0x49800000 0x100000>;
260 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
261 interrupt-names = "edma3_tcerrint";
262 };
263
264 edma_tptc1: tptc@49900000 {
265 compatible = "ti,edma3-tptc";
266 ti,hwmods = "tptc1";
267 reg = <0x49900000 0x100000>;
268 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
269 interrupt-names = "edma3_tcerrint";
270 };
271
272 edma_tptc2: tptc@49a00000 {
273 compatible = "ti,edma3-tptc";
274 ti,hwmods = "tptc2";
275 reg = <0x49a00000 0x100000>;
276 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
277 interrupt-names = "edma3_tcerrint";
9e3269b8 278 };
6cfd8117
AM		 279
280 uart0: serial@44e09000 {
281 compatible = "ti,am4372-uart","ti,omap2-uart";
282 reg = <0x44e09000 0x2000>;
283 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
73456012
AM		 284 ti,hwmods = "uart1";
285 };
286
287 uart1: serial@48022000 {
288 compatible = "ti,am4372-uart","ti,omap2-uart";
289 reg = <0x48022000 0x2000>;
290 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
291 ti,hwmods = "uart2";
292 status = "disabled";
293 };
294
295 uart2: serial@48024000 {
296 compatible = "ti,am4372-uart","ti,omap2-uart";
297 reg = <0x48024000 0x2000>;
298 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
299 ti,hwmods = "uart3";
300 status = "disabled";
301 };
302
303 uart3: serial@481a6000 {
304 compatible = "ti,am4372-uart","ti,omap2-uart";
305 reg = <0x481a6000 0x2000>;
306 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
307 ti,hwmods = "uart4";
308 status = "disabled";
309 };
310
311 uart4: serial@481a8000 {
312 compatible = "ti,am4372-uart","ti,omap2-uart";
313 reg = <0x481a8000 0x2000>;
314 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
315 ti,hwmods = "uart5";
316 status = "disabled";
317 };
318
319 uart5: serial@481aa000 {
320 compatible = "ti,am4372-uart","ti,omap2-uart";
321 reg = <0x481aa000 0x2000>;
322 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
323 ti,hwmods = "uart6";
324 status = "disabled";
6cfd8117
AM		 325 };
326
9e3269b8
LV		 327 mailbox: mailbox@480C8000 {
328 compatible = "ti,omap4-mailbox";
329 reg = <0x480C8000 0x200>;
330 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
331 ti,hwmods = "mailbox";
24df0453 332 #mbox-cells = <1>;
9e3269b8
LV		 333 ti,mbox-num-users = <4>;
334 ti,mbox-num-fifos = <8>;
d27704d1 335 mbox_wkupm3: wkup_m3 {
cf19f3ab 336 ti,mbox-send-noirq;
d27704d1
SA		 337 ti,mbox-tx = <0 0 0>;
338 ti,mbox-rx = <0 0 3>;
339 };
9e3269b8
LV		 340 };
341
6cfd8117
AM		 342 timer1: timer@44e31000 {
343 compatible = "ti,am4372-timer-1ms","ti,am335x-timer-1ms";
344 reg = <0x44e31000 0x400>;
345 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
346 ti,timer-alwon;
73456012 347 ti,hwmods = "timer1";
6cfd8117
AM		 348 };
349
350 timer2: timer@48040000 {
351 compatible = "ti,am4372-timer","ti,am335x-timer";
352 reg = <0x48040000 0x400>;
353 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
73456012
AM		 354 ti,hwmods = "timer2";
355 };
356
357 timer3: timer@48042000 {
358 compatible = "ti,am4372-timer","ti,am335x-timer";
359 reg = <0x48042000 0x400>;
360 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
361 ti,hwmods = "timer3";
362 status = "disabled";
363 };
364
365 timer4: timer@48044000 {
366 compatible = "ti,am4372-timer","ti,am335x-timer";
367 reg = <0x48044000 0x400>;
368 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
369 ti,timer-pwm;
370 ti,hwmods = "timer4";
371 status = "disabled";
372 };
373
374 timer5: timer@48046000 {
375 compatible = "ti,am4372-timer","ti,am335x-timer";
376 reg = <0x48046000 0x400>;
377 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
378 ti,timer-pwm;
379 ti,hwmods = "timer5";
380 status = "disabled";
381 };
382
383 timer6: timer@48048000 {
384 compatible = "ti,am4372-timer","ti,am335x-timer";
385 reg = <0x48048000 0x400>;
386 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
387 ti,timer-pwm;
388 ti,hwmods = "timer6";
389 status = "disabled";
390 };
391
392 timer7: timer@4804a000 {
393 compatible = "ti,am4372-timer","ti,am335x-timer";
394 reg = <0x4804a000 0x400>;
395 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
396 ti,timer-pwm;
397 ti,hwmods = "timer7";
398 status = "disabled";
399 };
400
401 timer8: timer@481c1000 {
402 compatible = "ti,am4372-timer","ti,am335x-timer";
403 reg = <0x481c1000 0x400>;
404 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
405 ti,hwmods = "timer8";
406 status = "disabled";
407 };
408
409 timer9: timer@4833d000 {
410 compatible = "ti,am4372-timer","ti,am335x-timer";
411 reg = <0x4833d000 0x400>;
412 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
413 ti,hwmods = "timer9";
414 status = "disabled";
415 };
416
417 timer10: timer@4833f000 {
418 compatible = "ti,am4372-timer","ti,am335x-timer";
419 reg = <0x4833f000 0x400>;
420 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
421 ti,hwmods = "timer10";
422 status = "disabled";
423 };
424
425 timer11: timer@48341000 {
426 compatible = "ti,am4372-timer","ti,am335x-timer";
427 reg = <0x48341000 0x400>;
428 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
429 ti,hwmods = "timer11";
430 status = "disabled";
6cfd8117
AM		 431 };
432
433 counter32k: counter@44e86000 {
434 compatible = "ti,am4372-counter32k","ti,omap-counter32k";
435 reg = <0x44e86000 0x40>;
73456012
AM		 436 ti,hwmods = "counter_32k";
437 };
438
08ecb28a 439 rtc: rtc@44e3e000 {
05743b3a
K		 440 compatible = "ti,am4372-rtc", "ti,am3352-rtc",
441 "ti,da830-rtc";
73456012
AM		 442 reg = <0x44e3e000 0x1000>;
443 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH
444 GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
445 ti,hwmods = "rtc";
fff51e77
K		 446 clocks = <&clk_32768_ck>;
447 clock-names = "int-clk";
73456012
AM		 448 status = "disabled";
449 };
450
08ecb28a 451 wdt: wdt@44e35000 {
73456012
AM		 452 compatible = "ti,am4372-wdt","ti,omap3-wdt";
453 reg = <0x44e35000 0x1000>;
454 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
455 ti,hwmods = "wd_timer2";
73456012
AM		 456 };
457
458 gpio0: gpio@44e07000 {
459 compatible = "ti,am4372-gpio","ti,omap4-gpio";
460 reg = <0x44e07000 0x1000>;
461 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
462 gpio-controller;
463 #gpio-cells = <2>;
464 interrupt-controller;
465 #interrupt-cells = <2>;
466 ti,hwmods = "gpio1";
467 status = "disabled";
468 };
469
470 gpio1: gpio@4804c000 {
471 compatible = "ti,am4372-gpio","ti,omap4-gpio";
472 reg = <0x4804c000 0x1000>;
473 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
474 gpio-controller;
475 #gpio-cells = <2>;
476 interrupt-controller;
477 #interrupt-cells = <2>;
478 ti,hwmods = "gpio2";
479 status = "disabled";
480 };
481
482 gpio2: gpio@481ac000 {
483 compatible = "ti,am4372-gpio","ti,omap4-gpio";
484 reg = <0x481ac000 0x1000>;
485 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
486 gpio-controller;
487 #gpio-cells = <2>;
488 interrupt-controller;
489 #interrupt-cells = <2>;
490 ti,hwmods = "gpio3";
491 status = "disabled";
492 };
493
494 gpio3: gpio@481ae000 {
495 compatible = "ti,am4372-gpio","ti,omap4-gpio";
496 reg = <0x481ae000 0x1000>;
497 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
498 gpio-controller;
499 #gpio-cells = <2>;
500 interrupt-controller;
501 #interrupt-cells = <2>;
502 ti,hwmods = "gpio4";
503 status = "disabled";
504 };
505
506 gpio4: gpio@48320000 {
507 compatible = "ti,am4372-gpio","ti,omap4-gpio";
508 reg = <0x48320000 0x1000>;
509 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
510 gpio-controller;
511 #gpio-cells = <2>;
512 interrupt-controller;
513 #interrupt-cells = <2>;
514 ti,hwmods = "gpio5";
515 status = "disabled";
516 };
517
518 gpio5: gpio@48322000 {
519 compatible = "ti,am4372-gpio","ti,omap4-gpio";
520 reg = <0x48322000 0x1000>;
521 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
522 gpio-controller;
523 #gpio-cells = <2>;
524 interrupt-controller;
525 #interrupt-cells = <2>;
526 ti,hwmods = "gpio6";
527 status = "disabled";
528 };
529
fd4a8a68
SA		 530 hwspinlock: spinlock@480ca000 {
531 compatible = "ti,omap4-hwspinlock";
532 reg = <0x480ca000 0x1000>;
533 ti,hwmods = "spinlock";
534 #hwlock-cells = <1>;
535 };
536
73456012
AM		 537 i2c0: i2c@44e0b000 {
538 compatible = "ti,am4372-i2c","ti,omap4-i2c";
539 reg = <0x44e0b000 0x1000>;
540 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
541 ti,hwmods = "i2c1";
542 #address-cells = <1>;
543 #size-cells = <0>;
544 status = "disabled";
545 };
546
547 i2c1: i2c@4802a000 {
548 compatible = "ti,am4372-i2c","ti,omap4-i2c";
549 reg = <0x4802a000 0x1000>;
550 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
551 ti,hwmods = "i2c2";
552 #address-cells = <1>;
553 #size-cells = <0>;
554 status = "disabled";
555 };
556
557 i2c2: i2c@4819c000 {
558 compatible = "ti,am4372-i2c","ti,omap4-i2c";
559 reg = <0x4819c000 0x1000>;
560 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
561 ti,hwmods = "i2c3";
562 #address-cells = <1>;
563 #size-cells = <0>;
564 status = "disabled";
565 };
566
567 spi0: spi@48030000 {
568 compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
569 reg = <0x48030000 0x400>;
570 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
571 ti,hwmods = "spi0";
572 #address-cells = <1>;
573 #size-cells = <0>;
574 status = "disabled";
575 };
576
9e3269b8
LV		 577 mmc1: mmc@48060000 {
578 compatible = "ti,omap4-hsmmc";
579 reg = <0x48060000 0x1000>;
580 ti,hwmods = "mmc1";
581 ti,dual-volt;
582 ti,needs-special-reset;
cce1ee00
PU		 583 dmas = <&edma 24 0>,
584 <&edma 25 0>;
9e3269b8
LV		 585 dma-names = "tx", "rx";
586 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
587 status = "disabled";
588 };
589
590 mmc2: mmc@481d8000 {
591 compatible = "ti,omap4-hsmmc";
592 reg = <0x481d8000 0x1000>;
593 ti,hwmods = "mmc2";
594 ti,needs-special-reset;
cce1ee00
PU		 595 dmas = <&edma 2 0>,
596 <&edma 3 0>;
9e3269b8
LV		 597 dma-names = "tx", "rx";
598 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
599 status = "disabled";
600 };
601
602 mmc3: mmc@47810000 {
603 compatible = "ti,omap4-hsmmc";
604 reg = <0x47810000 0x1000>;
605 ti,hwmods = "mmc3";
606 ti,needs-special-reset;
607 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
608 status = "disabled";
609 };
610
73456012
AM		 611 spi1: spi@481a0000 {
612 compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
613 reg = <0x481a0000 0x400>;
614 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
615 ti,hwmods = "spi1";
616 #address-cells = <1>;
617 #size-cells = <0>;
618 status = "disabled";
619 };
620
621 spi2: spi@481a2000 {
622 compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
623 reg = <0x481a2000 0x400>;
624 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
625 ti,hwmods = "spi2";
626 #address-cells = <1>;
627 #size-cells = <0>;
628 status = "disabled";
629 };
630
631 spi3: spi@481a4000 {
632 compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
633 reg = <0x481a4000 0x400>;
634 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
635 ti,hwmods = "spi3";
636 #address-cells = <1>;
637 #size-cells = <0>;
638 status = "disabled";
639 };
640
641 spi4: spi@48345000 {
642 compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
643 reg = <0x48345000 0x400>;
644 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
645 ti,hwmods = "spi4";
646 #address-cells = <1>;
647 #size-cells = <0>;
648 status = "disabled";
649 };
650
651 mac: ethernet@4a100000 {
652 compatible = "ti,am4372-cpsw","ti,cpsw";
653 reg = <0x4a100000 0x800
654 0x4a101200 0x100>;
655 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH
656 GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH
657 GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH
658 GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
9e3269b8
LV		 659 #address-cells = <1>;
660 #size-cells = <1>;
73456012 661 ti,hwmods = "cpgmac0";
dff8a207
K		 662 clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>,
663 <&dpll_clksel_mac_clk>;
664 clock-names = "fck", "cpts", "50mclk";
665 assigned-clocks = <&dpll_clksel_mac_clk>;
666 assigned-clock-rates = <50000000>;
73456012 667 status = "disabled";
9e3269b8
LV		 668 cpdma_channels = <8>;
669 ale_entries = <1024>;
670 bd_ram_size = <0x2000>;
671 no_bd_ram = <0>;
9e3269b8
LV		 672 mac_control = <0x20>;
673 slaves = <2>;
674 active_slave = <0>;
675 cpts_clock_mult = <0x80000000>;
676 cpts_clock_shift = <29>;
677 ranges;
cec42849 678 syscon = <&scm_conf>;
9e3269b8
LV		 679
680 davinci_mdio: mdio@4a101000 {
9efd1a6f 681 compatible = "ti,am4372-mdio","ti,cpsw-mdio","ti,davinci_mdio";
9e3269b8
LV		 682 reg = <0x4a101000 0x100>;
683 #address-cells = <1>;
684 #size-cells = <0>;
685 ti,hwmods = "davinci_mdio";
686 bus_freq = <1000000>;
687 status = "disabled";
688 };
689
690 cpsw_emac0: slave@4a100200 {
691 /* Filled in by U-Boot */
692 mac-address = [ 00 00 00 00 00 00 ];
693 };
694
695 cpsw_emac1: slave@4a100300 {
696 /* Filled in by U-Boot */
697 mac-address = [ 00 00 00 00 00 00 ];
698 };
a9682cfb
M		 699
700 phy_sel: cpsw-phy-sel@44e10650 {
701 compatible = "ti,am43xx-cpsw-phy-sel";
702 reg= <0x44e10650 0x4>;
703 reg-names = "gmii-sel";
704 };
73456012
AM		 705 };
706
707 epwmss0: epwmss@48300000 {
708 compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
709 reg = <0x48300000 0x10>;
9e3269b8
LV		 710 #address-cells = <1>;
711 #size-cells = <1>;
712 ranges;
73456012
AM		 713 ti,hwmods = "epwmss0";
714 status = "disabled";
9e3269b8
LV		 715
716 ecap0: ecap@48300100 {
229110c1
FCJ		 717 compatible = "ti,am4372-ecap",
718 "ti,am3352-ecap",
719 "ti,am33xx-ecap";
aa842305 720 #pwm-cells = <3>;
9e3269b8 721 reg = <0x48300100 0x80>;
229110c1
FCJ		 722 clocks = <&l4ls_gclk>;
723 clock-names = "fck";
9e3269b8
LV		 724 status = "disabled";
725 };
726
dce2a652 727 ehrpwm0: pwm@48300200 {
229110c1
FCJ		 728 compatible = "ti,am4372-ehrpwm",
729 "ti,am3352-ehrpwm",
730 "ti,am33xx-ehrpwm";
aa842305 731 #pwm-cells = <3>;
9e3269b8 732 reg = <0x48300200 0x80>;
229110c1
FCJ		 733 clocks = <&ehrpwm0_tbclk>, <&l4ls_gclk>;
734 clock-names = "tbclk", "fck";
9e3269b8
LV		 735 status = "disabled";
736 };
73456012
AM		 737 };
738
739 epwmss1: epwmss@48302000 {
740 compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
741 reg = <0x48302000 0x10>;
9e3269b8
LV		 742 #address-cells = <1>;
743 #size-cells = <1>;
744 ranges;
73456012
AM		 745 ti,hwmods = "epwmss1";
746 status = "disabled";
9e3269b8
LV		 747
748 ecap1: ecap@48302100 {
229110c1
FCJ		 749 compatible = "ti,am4372-ecap",
750 "ti,am3352-ecap",
751 "ti,am33xx-ecap";
aa842305 752 #pwm-cells = <3>;
9e3269b8 753 reg = <0x48302100 0x80>;
229110c1
FCJ		 754 clocks = <&l4ls_gclk>;
755 clock-names = "fck";
9e3269b8
LV		 756 status = "disabled";
757 };
758
dce2a652 759 ehrpwm1: pwm@48302200 {
229110c1
FCJ		 760 compatible = "ti,am4372-ehrpwm",
761 "ti,am3352-ehrpwm",
762 "ti,am33xx-ehrpwm";
aa842305 763 #pwm-cells = <3>;
9e3269b8 764 reg = <0x48302200 0x80>;
229110c1
FCJ		 765 clocks = <&ehrpwm1_tbclk>, <&l4ls_gclk>;
766 clock-names = "tbclk", "fck";
9e3269b8
LV		 767 status = "disabled";
768 };
73456012
AM		 769 };
770
771 epwmss2: epwmss@48304000 {
772 compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
773 reg = <0x48304000 0x10>;
9e3269b8
LV		 774 #address-cells = <1>;
775 #size-cells = <1>;
776 ranges;
73456012
AM		 777 ti,hwmods = "epwmss2";
778 status = "disabled";
9e3269b8
LV		 779
780 ecap2: ecap@48304100 {
229110c1
FCJ		 781 compatible = "ti,am4372-ecap",
782 "ti,am3352-ecap",
783 "ti,am33xx-ecap";
aa842305 784 #pwm-cells = <3>;
9e3269b8 785 reg = <0x48304100 0x80>;
229110c1
FCJ		 786 clocks = <&l4ls_gclk>;
787 clock-names = "fck";
9e3269b8
LV		 788 status = "disabled";
789 };
790
dce2a652 791 ehrpwm2: pwm@48304200 {
229110c1
FCJ		 792 compatible = "ti,am4372-ehrpwm",
793 "ti,am3352-ehrpwm",
794 "ti,am33xx-ehrpwm";
aa842305 795 #pwm-cells = <3>;
9e3269b8 796 reg = <0x48304200 0x80>;
229110c1
FCJ		 797 clocks = <&ehrpwm2_tbclk>, <&l4ls_gclk>;
798 clock-names = "tbclk", "fck";
9e3269b8
LV		 799 status = "disabled";
800 };
73456012
AM		 801 };
802
803 epwmss3: epwmss@48306000 {
804 compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
805 reg = <0x48306000 0x10>;
9e3269b8
LV		 806 #address-cells = <1>;
807 #size-cells = <1>;
808 ranges;
73456012
AM		 809 ti,hwmods = "epwmss3";
810 status = "disabled";
9e3269b8 811
dce2a652 812 ehrpwm3: pwm@48306200 {
229110c1
FCJ		 813 compatible = "ti,am4372-ehrpwm",
814 "ti,am3352-ehrpwm",
815 "ti,am33xx-ehrpwm";
aa842305 816 #pwm-cells = <3>;
9e3269b8 817 reg = <0x48306200 0x80>;
229110c1
FCJ		 818 clocks = <&ehrpwm3_tbclk>, <&l4ls_gclk>;
819 clock-names = "tbclk", "fck";
9e3269b8
LV		 820 status = "disabled";
821 };
73456012
AM		 822 };
823
824 epwmss4: epwmss@48308000 {
825 compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
826 reg = <0x48308000 0x10>;
9e3269b8
LV		 827 #address-cells = <1>;
828 #size-cells = <1>;
829 ranges;
73456012
AM		 830 ti,hwmods = "epwmss4";
831 status = "disabled";
9e3269b8 832
dce2a652 833 ehrpwm4: pwm@48308200 {
229110c1
FCJ		 834 compatible = "ti,am4372-ehrpwm",
835 "ti,am3352-ehrpwm",
836 "ti,am33xx-ehrpwm";
aa842305 837 #pwm-cells = <3>;
9e3269b8 838 reg = <0x48308200 0x80>;
229110c1
FCJ		 839 clocks = <&ehrpwm4_tbclk>, <&l4ls_gclk>;
840 clock-names = "tbclk", "fck";
9e3269b8
LV		 841 status = "disabled";
842 };
73456012
AM		 843 };
844
845 epwmss5: epwmss@4830a000 {
846 compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
847 reg = <0x4830a000 0x10>;
9e3269b8
LV		 848 #address-cells = <1>;
849 #size-cells = <1>;
850 ranges;
73456012
AM		 851 ti,hwmods = "epwmss5";
852 status = "disabled";
9e3269b8 853
dce2a652 854 ehrpwm5: pwm@4830a200 {
229110c1
FCJ		 855 compatible = "ti,am4372-ehrpwm",
856 "ti,am3352-ehrpwm",
857 "ti,am33xx-ehrpwm";
aa842305 858 #pwm-cells = <3>;
9e3269b8 859 reg = <0x4830a200 0x80>;
229110c1
FCJ		 860 clocks = <&ehrpwm5_tbclk>, <&l4ls_gclk>;
861 clock-names = "tbclk", "fck";
9e3269b8
LV		 862 status = "disabled";
863 };
864 };
865
0f39f7b9
V		 866 tscadc: tscadc@44e0d000 {
867 compatible = "ti,am3359-tscadc";
868 reg = <0x44e0d000 0x1000>;
869 ti,hwmods = "adc_tsc";
870 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
871 clocks = <&adc_tsc_fck>;
872 clock-names = "fck";
873 status = "disabled";
874
875 tsc {
876 compatible = "ti,am3359-tsc";
877 };
878
879 adc {
880 #io-channel-cells = <1>;
881 compatible = "ti,am3359-adc";
882 };
883
884 };
885
9e3269b8
LV		 886 sham: sham@53100000 {
887 compatible = "ti,omap5-sham";
888 ti,hwmods = "sham";
889 reg = <0x53100000 0x300>;
cce1ee00 890 dmas = <&edma 36 0>;
9e3269b8
LV		 891 dma-names = "rx";
892 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
6cfd8117 893 };
6e70a510
JF		 894
895 aes: aes@53501000 {
896 compatible = "ti,omap4-aes";
897 ti,hwmods = "aes";
898 reg = <0x53501000 0xa0>;
899 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
cce1ee00
PU		 900 dmas = <&edma 6 0>,
901 <&edma 5 0>;
9e3269b8 902 dma-names = "tx", "rx";
6e70a510 903 };
099f3a85
JF		 904
905 des: des@53701000 {
906 compatible = "ti,omap4-des";
907 ti,hwmods = "des";
908 reg = <0x53701000 0xa0>;
909 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
cce1ee00
PU		 910 dmas = <&edma 34 0>,
911 <&edma 33 0>;
9e3269b8 912 dma-names = "tx", "rx";
099f3a85 913 };
9e3269b8 914
52c7c913
LV		 915 rng: rng@48310000 {
916 compatible = "ti,omap4-rng";
917 ti,hwmods = "rng";
918 reg = <0x48310000 0x2000>;
919 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
920 };
921
b9c95bf4
PU		 922 mcasp0: mcasp@48038000 {
923 compatible = "ti,am33xx-mcasp-audio";
924 ti,hwmods = "mcasp0";
925 reg = <0x48038000 0x2000>,
926 <0x46000000 0x400000>;
927 reg-names = "mpu", "dat";
928 interrupts = <80>, <81>;
ae107d06 929 interrupt-names = "tx", "rx";
b9c95bf4 930 status = "disabled";
cce1ee00
PU		 931 dmas = <&edma 8 2>,
932 <&edma 9 2>;
b9c95bf4
PU		 933 dma-names = "tx", "rx";
934 };
935
936 mcasp1: mcasp@4803C000 {
937 compatible = "ti,am33xx-mcasp-audio";
938 ti,hwmods = "mcasp1";
939 reg = <0x4803C000 0x2000>,
940 <0x46400000 0x400000>;
941 reg-names = "mpu", "dat";
942 interrupts = <82>, <83>;
ae107d06 943 interrupt-names = "tx", "rx";
b9c95bf4 944 status = "disabled";
cce1ee00
PU		 945 dmas = <&edma 10 2>,
946 <&edma 11 2>;
b9c95bf4
PU		 947 dma-names = "tx", "rx";
948 };
f68e355c
PG		 949
950 elm: elm@48080000 {
951 compatible = "ti,am3352-elm";
952 reg = <0x48080000 0x2000>;
953 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
954 ti,hwmods = "elm";
955 clocks = <&l4ls_gclk>;
956 clock-names = "fck";
957 status = "disabled";
958 };
959
960 gpmc: gpmc@50000000 {
961 compatible = "ti,am3352-gpmc";
962 ti,hwmods = "gpmc";
883cbc90 963 dmas = <&edma 52 0>;
201c7e33 964 dma-names = "rxtx";
f68e355c
PG		 965 clocks = <&l3s_gclk>;
966 clock-names = "fck";
967 reg = <0x50000000 0x2000>;
968 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
969 gpmc,num-cs = <7>;
970 gpmc,num-waitpins = <2>;
971 #address-cells = <2>;
972 #size-cells = <1>;
be3f39c8
RQ		 973 interrupt-controller;
974 #interrupt-cells = <2>;
9e08c2da
RQ		 975 gpio-controller;
976 #gpio-cells = <2>;
f68e355c
PG		 977 status = "disabled";
978 };
a0ae47ea 979
a0ae47ea 980 ocp2scp0: ocp2scp@483a8000 {
20431db9 981 compatible = "ti,am437x-ocp2scp", "ti,omap-ocp2scp";
a0ae47ea
GC		 982 #address-cells = <1>;
983 #size-cells = <1>;
984 ranges;
985 ti,hwmods = "ocp2scp0";
986
987 usb2_phy1: phy@483a8000 {
988 compatible = "ti,am437x-usb2";
989 reg = <0x483a8000 0x8000>;
2338c76a 990 syscon-phy-power = <&scm_conf 0x620>;
a0ae47ea
GC		 991 clocks = <&usb_phy0_always_on_clk32k>,
992 <&usb_otg_ss0_refclk960m>;
993 clock-names = "wkupclk", "refclk";
994 #phy-cells = <0>;
995 status = "disabled";
996 };
997 };
998
999 ocp2scp1: ocp2scp@483e8000 {
20431db9 1000 compatible = "ti,am437x-ocp2scp", "ti,omap-ocp2scp";
a0ae47ea
GC		 1001 #address-cells = <1>;
1002 #size-cells = <1>;
1003 ranges;
1004 ti,hwmods = "ocp2scp1";
1005
1006 usb2_phy2: phy@483e8000 {
1007 compatible = "ti,am437x-usb2";
1008 reg = <0x483e8000 0x8000>;
2338c76a 1009 syscon-phy-power = <&scm_conf 0x628>;
a0ae47ea
GC		 1010 clocks = <&usb_phy1_always_on_clk32k>,
1011 <&usb_otg_ss1_refclk960m>;
1012 clock-names = "wkupclk", "refclk";
1013 #phy-cells = <0>;
1014 status = "disabled";
1015 };
1016 };
1017
1018 dwc3_1: omap_dwc3@48380000 {
1019 compatible = "ti,am437x-dwc3";
1020 ti,hwmods = "usb_otg_ss0";
1021 reg = <0x48380000 0x10000>;
1022 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
1023 #address-cells = <1>;
1024 #size-cells = <1>;
1025 utmi-mode = <1>;
1026 ranges;
1027
1028 usb1: usb@48390000 {
1029 compatible = "synopsys,dwc3";
4b143f0f 1030 reg = <0x48390000 0x10000>;
1d20e4bf
FB		 1031 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
1032 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
1033 <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
1034 interrupt-names = "peripheral",
1035 "host",
1036 "otg";
a0ae47ea
GC		 1037 phys = <&usb2_phy1>;
1038 phy-names = "usb2-phy";
1039 maximum-speed = "high-speed";
1040 dr_mode = "otg";
1041 status = "disabled";
60f0e628
FB		 1042 snps,dis_u3_susphy_quirk;
1043 snps,dis_u2_susphy_quirk;
a0ae47ea
GC		 1044 };
1045 };
1046
1047 dwc3_2: omap_dwc3@483c0000 {
1048 compatible = "ti,am437x-dwc3";
1049 ti,hwmods = "usb_otg_ss1";
1050 reg = <0x483c0000 0x10000>;
1051 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
1052 #address-cells = <1>;
1053 #size-cells = <1>;
1054 utmi-mode = <1>;
1055 ranges;
1056
1057 usb2: usb@483d0000 {
1058 compatible = "synopsys,dwc3";
4b143f0f 1059 reg = <0x483d0000 0x10000>;
1d20e4bf
FB		 1060 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
1061 <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
1062 <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
1063 interrupt-names = "peripheral",
1064 "host",
1065 "otg";
a0ae47ea
GC		 1066 phys = <&usb2_phy2>;
1067 phy-names = "usb2-phy";
1068 maximum-speed = "high-speed";
1069 dr_mode = "otg";
1070 status = "disabled";
60f0e628
FB		 1071 snps,dis_u3_susphy_quirk;
1072 snps,dis_u2_susphy_quirk;
a0ae47ea
GC		 1073 };
1074 };
2a1a5043
SP		 1075
1076 qspi: qspi@47900000 {
1077 compatible = "ti,am4372-qspi";
2acb6c3e
V		 1078 reg = <0x47900000 0x100>,
1079 <0x30000000 0x4000000>;
1080 reg-names = "qspi_base", "qspi_mmap";
2a1a5043
SP		 1081 #address-cells = <1>;
1082 #size-cells = <0>;
1083 ti,hwmods = "qspi";
1084 interrupts = <0 138 0x4>;
1085 num-cs = <4>;
1086 status = "disabled";
1087 };
741cac5f
SP		 1088
1089 hdq: hdq@48347000 {
a895b8a0 1090 compatible = "ti,am4372-hdq";
741cac5f
SP		 1091 reg = <0x48347000 0x1000>;
1092 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
1093 clocks = <&func_12m_clk>;
1094 clock-names = "fck";
1095 ti,hwmods = "hdq1w";
1096 status = "disabled";
1097 };
8c793367
SP		 1098
1099 dss: dss@4832a000 {
1100 compatible = "ti,omap3-dss";
1101 reg = <0x4832a000 0x200>;
1102 status = "disabled";
1103 ti,hwmods = "dss_core";
1104 clocks = <&disp_clk>;
1105 clock-names = "fck";
1106 #address-cells = <1>;
1107 #size-cells = <1>;
1108 ranges;
1109
08ecb28a 1110 dispc: dispc@4832a400 {
8c793367
SP		 1111 compatible = "ti,omap3-dispc";
1112 reg = <0x4832a400 0x400>;
1113 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
1114 ti,hwmods = "dss_dispc";
1115 clocks = <&disp_clk>;
1116 clock-names = "fck";
1117 };
1118
1119 rfbi: rfbi@4832a800 {
1120 compatible = "ti,omap3-rfbi";
1121 reg = <0x4832a800 0x100>;
1122 ti,hwmods = "dss_rfbi";
1123 clocks = <&disp_clk>;
1124 clock-names = "fck";
22a5dc10 1125 status = "disabled";
8c793367
SP		 1126 };
1127 };
8b9a2810
RN		 1128
1129 ocmcram: ocmcram@40300000 {
1130 compatible = "mmio-sram";
1131 reg = <0x40300000 0x40000>; /* 256k */
1132 };
9e63b0d4
RQ		 1133
1134 dcan0: can@481cc000 {
1135 compatible = "ti,am4372-d_can", "ti,am3352-d_can";
1136 ti,hwmods = "d_can0";
1137 clocks = <&dcan0_fck>;
1138 clock-names = "fck";
1139 reg = <0x481cc000 0x2000>;
83a5d6c9 1140 syscon-raminit = <&scm_conf 0x644 0>;
9e63b0d4
RQ		 1141 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
1142 status = "disabled";
1143 };
1144
1145 dcan1: can@481d0000 {
1146 compatible = "ti,am4372-d_can", "ti,am3352-d_can";
1147 ti,hwmods = "d_can1";
1148 clocks = <&dcan1_fck>;
1149 clock-names = "fck";
1150 reg = <0x481d0000 0x2000>;
83a5d6c9 1151 syscon-raminit = <&scm_conf 0x644 1>;
9e63b0d4
RQ		 1152 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
1153 status = "disabled";
1154 };
9d0df0a6
BP		 1155
1156 vpfe0: vpfe@48326000 {
1157 compatible = "ti,am437x-vpfe";
1158 reg = <0x48326000 0x2000>;
1159 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
1160 ti,hwmods = "vpfe0";
1161 status = "disabled";
1162 };
1163
1164 vpfe1: vpfe@48328000 {
1165 compatible = "ti,am437x-vpfe";
1166 reg = <0x48328000 0x2000>;
1167 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
1168 ti,hwmods = "vpfe1";
1169 status = "disabled";
1170 };
6cfd8117
AM		 1171 };
1172};
6a679208
TK		 1173
1174/include/ "am43xx-clocks.dtsi"
Linux kernel - Deliverables
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