[deliverable/linux.git] / arch / arm / boot / dts / armada-370.dtsi

/*
 * Device Tree Include file for Marvell Armada 370 family SoC
 *
 * Copyright (C) 2012 Marvell
 *
 * Lior Amsalem <alior@marvell.com>
 * Gregory CLEMENT <gregory.clement@free-electrons.com>
 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 *  a) This file is free software; you can redistribute it and/or
 *     modify it under the terms of the GNU General Public License as
 *     published by the Free Software Foundation; either version 2 of the
 *     License, or (at your option) any later version.
 *
 *     This file is distributed in the hope that it will be useful
 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *     GNU General Public License for more details.
 *
 * Or, alternatively
 *
 *  b) Permission is hereby granted, free of charge, to any person
 *     obtaining a copy of this software and associated documentation
 *     files (the "Software"), to deal in the Software without
 *     restriction, including without limitation the rights to use
 *     copy, modify, merge, publish, distribute, sublicense, and/or
 *     sell copies of the Software, and to permit persons to whom the
 *     Software is furnished to do so, subject to the following
 *     conditions:
 *
 *     The above copyright notice and this permission notice shall be
 *     included in all copies or substantial portions of the Software.
 *
 *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 *     OTHER DEALINGS IN THE SOFTWARE.
 *
 * Contains definitions specific to the Armada 370 SoC that are not
 * common to all Armada SoCs.
 */

#include "armada-370-xp.dtsi"
/include/ "skeleton.dtsi"

/ {
	model = "Marvell Armada 370 family SoC";
	compatible = "marvell,armada370", "marvell,armada-370-xp";

	aliases {
		gpio0 = &gpio0;
		gpio1 = &gpio1;
		gpio2 = &gpio2;
	};

	soc {
		compatible = "marvell,armada370-mbus", "simple-bus";

		bootrom {
			compatible = "marvell,bootrom";
			reg = <MBUS_ID(0x01, 0xe0) 0 0x100000>;
		};

		pcie-controller {
			compatible = "marvell,armada-370-pcie";
			status = "disabled";
			device_type = "pci";

			#address-cells = <3>;
			#size-cells = <2>;

			msi-parent = <&mpic>;
			bus-range = <0x00 0xff>;

			ranges =
			       <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
				0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000
				0x82000000 0x1 0     MBUS_ID(0x04, 0xe8) 0       1 0 /* Port 0.0 MEM */
				0x81000000 0x1 0     MBUS_ID(0x04, 0xe0) 0       1 0 /* Port 0.0 IO  */
				0x82000000 0x2 0     MBUS_ID(0x08, 0xe8) 0       1 0 /* Port 1.0 MEM */
				0x81000000 0x2 0     MBUS_ID(0x08, 0xe0) 0       1 0 /* Port 1.0 IO  */>;

			pcie@1,0 {
				device_type = "pci";
				assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
				reg = <0x0800 0 0 0 0>;
				#address-cells = <3>;
				#size-cells = <2>;
				#interrupt-cells = <1>;
                                ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
                                          0x81000000 0 0 0x81000000 0x1 0 1 0>;
				interrupt-map-mask = <0 0 0 0>;
				interrupt-map = <0 0 0 0 &mpic 58>;
				marvell,pcie-port = <0>;
				marvell,pcie-lane = <0>;
				clocks = <&gateclk 5>;
				status = "disabled";
			};

			pcie@2,0 {
				device_type = "pci";
				assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
				reg = <0x1000 0 0 0 0>;
				#address-cells = <3>;
				#size-cells = <2>;
				#interrupt-cells = <1>;
                                ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
                                          0x81000000 0 0 0x81000000 0x2 0 1 0>;
				interrupt-map-mask = <0 0 0 0>;
				interrupt-map = <0 0 0 0 &mpic 62>;
				marvell,pcie-port = <1>;
				marvell,pcie-lane = <0>;
				clocks = <&gateclk 9>;
				status = "disabled";
			};
		};

		internal-regs {
			L2: l2-cache {
				compatible = "marvell,aurora-outer-cache";
				reg = <0x08000 0x1000>;
				cache-id-part = <0x100>;
				cache-level = <2>;
				cache-unified;
				wt-override;
			};

			i2c0: i2c@11000 {
				reg = <0x11000 0x20>;
			};

			i2c1: i2c@11100 {
				reg = <0x11100 0x20>;
			};

			gpio0: gpio@18100 {
				compatible = "marvell,orion-gpio";
				reg = <0x18100 0x40>;
				ngpios = <32>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				interrupts = <82>, <83>, <84>, <85>;
			};

			gpio1: gpio@18140 {
				compatible = "marvell,orion-gpio";
				reg = <0x18140 0x40>;
				ngpios = <32>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				interrupts = <87>, <88>, <89>, <90>;
			};

			gpio2: gpio@18180 {
				compatible = "marvell,orion-gpio";
				reg = <0x18180 0x40>;
				ngpios = <2>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				interrupts = <91>;
			};

			/*
			 * Default UART pinctrl setting without RTS/CTS, can
			 * be overwritten on board level if a different
			 * configuration is used.
			 */
			uart0: serial@12000 {
				pinctrl-0 = <&uart0_pins>;
				pinctrl-names = "default";
			};

			uart1: serial@12100 {
				pinctrl-0 = <&uart1_pins>;
				pinctrl-names = "default";
			};

			system-controller@18200 {
				compatible = "marvell,armada-370-xp-system-controller";
				reg = <0x18200 0x100>;
			};

			gateclk: clock-gating-control@18220 {
				compatible = "marvell,armada-370-gating-clock";
				reg = <0x18220 0x4>;
				clocks = <&coreclk 0>;
				#clock-cells = <1>;
			};

			coreclk: mvebu-sar@18230 {
				compatible = "marvell,armada-370-core-clock";
				reg = <0x18230 0x08>;
				#clock-cells = <1>;
			};

			thermal@18300 {
				compatible = "marvell,armada370-thermal";
				reg = <0x18300 0x4
					0x18304 0x4>;
				status = "okay";
			};

			sscg@18330 {
				reg = <0x18330 0x4>;
			};

			interrupt-controller@20a00 {
				reg = <0x20a00 0x1d0>, <0x21870 0x58>;
			};

			timer@20300 {
				compatible = "marvell,armada-370-timer";
				clocks = <&coreclk 2>;
			};

			watchdog@20300 {
				compatible = "marvell,armada-370-wdt";
				clocks = <&coreclk 2>;
			};

			cpurst@20800 {
				compatible = "marvell,armada-370-cpu-reset";
				reg = <0x20800 0x8>;
			};

			cpu-config@21000 {
				compatible = "marvell,armada-370-cpu-config";
				reg = <0x21000 0x8>;
			};

			audio_controller: audio-controller@30000 {
				#sound-dai-cells = <1>;
				compatible = "marvell,armada370-audio";
				reg = <0x30000 0x4000>;
				interrupts = <93>;
				clocks = <&gateclk 0>;
				clock-names = "internal";
				status = "disabled";
			};

			usb@50000 {
				clocks = <&coreclk 0>;
			};

			usb@51000 {
				clocks = <&coreclk 0>;
			};

			xor@60800 {
				compatible = "marvell,orion-xor";
				reg = <0x60800 0x100
				       0x60A00 0x100>;
				status = "okay";

				xor00 {
					interrupts = <51>;
					dmacap,memcpy;
					dmacap,xor;
				};
				xor01 {
					interrupts = <52>;
					dmacap,memcpy;
					dmacap,xor;
					dmacap,memset;
				};
			};

			xor@60900 {
				compatible = "marvell,orion-xor";
				reg = <0x60900 0x100
				       0x60b00 0x100>;
				status = "okay";

				xor10 {
					interrupts = <94>;
					dmacap,memcpy;
					dmacap,xor;
				};
				xor11 {
					interrupts = <95>;
					dmacap,memcpy;
					dmacap,xor;
					dmacap,memset;
				};
			};

			ethernet@70000 {
				compatible = "marvell,armada-370-neta";
			};

			ethernet@74000 {
				compatible = "marvell,armada-370-neta";
			};

			crypto@90000 {
				compatible = "marvell,armada-370-crypto";
				reg = <0x90000 0x10000>;
				reg-names = "regs";
				interrupts = <48>;
				clocks = <&gateclk 23>;
				clock-names = "cesa0";
				marvell,crypto-srams = <&crypto_sram>;
				marvell,crypto-sram-size = <0x7e0>;
			};
		};

		crypto_sram: sa-sram {
			compatible = "mmio-sram";
			reg = <MBUS_ID(0x09, 0x01) 0 0x800>;
			reg-names = "sram";
			clocks = <&gateclk 23>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 MBUS_ID(0x09, 0x01) 0 0x800>;

			/*
			 * The Armada 370 has an erratum preventing the use of
			 * the standard workflow for CPU idle support (relying
			 * on the BootROM code to enter/exit idle state).
			 * Reserve some amount of the crypto SRAM to put the
			 * cpuidle workaround.
			 */
			idle-sram@0 {
				reg = <0x0 0x20>;
			};
		};
	};
};

&pinctrl {
	compatible = "marvell,mv88f6710-pinctrl";

	spi0_pins1: spi0-pins1 {
		marvell,pins = "mpp33", "mpp34",
			       "mpp35", "mpp36";
		marvell,function = "spi0";
	};

	spi0_pins2: spi0_pins2 {
		marvell,pins = "mpp32", "mpp63",
			       "mpp64", "mpp65";
		marvell,function = "spi0";
	};

	spi1_pins: spi1-pins {
		marvell,pins = "mpp49", "mpp50",
			       "mpp51", "mpp52";
		marvell,function = "spi1";
	};

	uart0_pins: uart0-pins {
		marvell,pins = "mpp0", "mpp1";
		marvell,function = "uart0";
	};

	uart1_pins: uart1-pins {
		marvell,pins = "mpp41", "mpp42";
		marvell,function = "uart1";
	};

	sdio_pins1: sdio-pins1 {
		marvell,pins = "mpp9",  "mpp11", "mpp12",
				"mpp13", "mpp14", "mpp15";
		marvell,function = "sd0";
	};

	sdio_pins2: sdio-pins2 {
		marvell,pins = "mpp47", "mpp48", "mpp49",
				"mpp50", "mpp51", "mpp52";
		marvell,function = "sd0";
	};

	sdio_pins3: sdio-pins3 {
		marvell,pins = "mpp48", "mpp49", "mpp50",
				"mpp51", "mpp52", "mpp53";
		marvell,function = "sd0";
	};

	i2c0_pins: i2c0-pins {
		marvell,pins = "mpp2", "mpp3";
		marvell,function = "i2c0";
	};

	i2s_pins1: i2s-pins1 {
		marvell,pins = "mpp5", "mpp6", "mpp7",
			       "mpp8", "mpp9", "mpp10",
			       "mpp12", "mpp13";
		marvell,function = "audio";
	};

	i2s_pins2: i2s-pins2 {
		marvell,pins = "mpp49", "mpp47", "mpp50",
			       "mpp59", "mpp57", "mpp61",
			       "mpp62", "mpp60", "mpp58";
		marvell,function = "audio";
	};

	mdio_pins: mdio-pins {
		marvell,pins = "mpp17", "mpp18";
		marvell,function = "ge";
	};

	ge0_rgmii_pins: ge0-rgmii-pins {
		marvell,pins = "mpp5", "mpp6", "mpp7", "mpp8",
			       "mpp9", "mpp10", "mpp11", "mpp12",
			       "mpp13", "mpp14", "mpp15", "mpp16";
		marvell,function = "ge0";
	};

	ge1_rgmii_pins: ge1-rgmii-pins {
		marvell,pins = "mpp19", "mpp20", "mpp21", "mpp22",
			       "mpp23", "mpp24", "mpp25", "mpp26",
			       "mpp27", "mpp28", "mpp29", "mpp30";
		marvell,function = "ge1";
	};
};

/*
 * Default SPI pinctrl setting, can be overwritten on
 * board level if a different configuration is used.
 */
&spi0 {
	compatible = "marvell,armada-370-spi", "marvell,orion-spi";
	pinctrl-0 = <&spi0_pins1>;
	pinctrl-names = "default";
};

&spi1 {
	compatible = "marvell,armada-370-spi", "marvell,orion-spi";
	pinctrl-0 = <&spi1_pins>;
	pinctrl-names = "default";
};
Commit	Line	Data
9ae6f740 TP	1	/*
	2	* Device Tree Include file for Marvell Armada 370 family SoC
	3	*
	4	* Copyright (C) 2012 Marvell
	5	*
	6	* Lior Amsalem <alior@marvell.com>
	7	* Gregory CLEMENT <gregory.clement@free-electrons.com>
	8	* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
	9	*
e7ad1fdf GC	10	* This file is dual-licensed: you can use it either under the terms
	11	* of the GPL or the X11 license, at your option. Note that this dual
	12	* licensing only applies to this file, and not this project as a
	13	* whole.
	14	*
	15	* a) This file is free software; you can redistribute it and/or
	16	* modify it under the terms of the GNU General Public License as
	17	* published by the Free Software Foundation; either version 2 of the
	18	* License, or (at your option) any later version.
	19	*
	20	* This file is distributed in the hope that it will be useful
	21	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	22	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	23	* GNU General Public License for more details.
	24	*
	25	* Or, alternatively
	26	*
	27	* b) Permission is hereby granted, free of charge, to any person
	28	* obtaining a copy of this software and associated documentation
	29	* files (the "Software"), to deal in the Software without
	30	* restriction, including without limitation the rights to use
	31	* copy, modify, merge, publish, distribute, sublicense, and/or
	32	* sell copies of the Software, and to permit persons to whom the
	33	* Software is furnished to do so, subject to the following
	34	* conditions:
	35	*
	36	* The above copyright notice and this permission notice shall be
	37	* included in all copies or substantial portions of the Software.
	38	*
	39	* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
	40	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
	41	* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	42	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
	43	* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
	44	* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	45	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	46	* OTHER DEALINGS IN THE SOFTWARE.
9ae6f740 TP	47	*
	48	* Contains definitions specific to the Armada 370 SoC that are not
	49	* common to all Armada SoCs.
	50	*/
	51
38149887	52	#include "armada-370-xp.dtsi"
74898364	53	/include/ "skeleton.dtsi"
9ae6f740 TP	54
	55	/ {
	56	model = "Marvell Armada 370 family SoC";
	57	compatible = "marvell,armada370", "marvell,armada-370-xp";
	58
397d59f3 TP	59	aliases {
	60	gpio0 = &gpio0;
	61	gpio1 = &gpio1;
	62	gpio2 = &gpio2;
	63	};
	64
9ae6f740	65	soc {
5e12a613 EG	66	compatible = "marvell,armada370-mbus", "simple-bus";
5e12a613 EG	67
0cd3754a EG	68	bootrom {
	69	compatible = "marvell,bootrom";
	70	reg = <MBUS_ID(0x01, 0xe0) 0 0x100000>;
	71	};
	72
14fd8ed0 EG	73	pcie-controller {
	74	compatible = "marvell,armada-370-pcie";
	75	status = "disabled";
	76	device_type = "pci";
	77
	78	#address-cells = <3>;
	79	#size-cells = <2>;
	80
d4fa9941	81	msi-parent = <&mpic>;
14fd8ed0 EG	82	bus-range = <0x00 0xff>;
	83
	84	ranges =
	85	<0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
	86	0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000
	87	0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
	88	0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
	89	0x82000000 0x2 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
	90	0x81000000 0x2 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */>;
	91
	92	pcie@1,0 {
	93	device_type = "pci";
	94	assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
	95	reg = <0x0800 0 0 0 0>;
	96	#address-cells = <3>;
	97	#size-cells = <2>;
	98	#interrupt-cells = <1>;
	99	ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
	100	0x81000000 0 0 0x81000000 0x1 0 1 0>;
	101	interrupt-map-mask = <0 0 0 0>;
	102	interrupt-map = <0 0 0 0 &mpic 58>;
	103	marvell,pcie-port = <0>;
	104	marvell,pcie-lane = <0>;
	105	clocks = <&gateclk 5>;
	106	status = "disabled";
	107	};
	108
	109	pcie@2,0 {
	110	device_type = "pci";
	111	assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
	112	reg = <0x1000 0 0 0 0>;
	113	#address-cells = <3>;
	114	#size-cells = <2>;
	115	#interrupt-cells = <1>;
	116	ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
	117	0x81000000 0 0 0x81000000 0x2 0 1 0>;
	118	interrupt-map-mask = <0 0 0 0>;
	119	interrupt-map = <0 0 0 0 &mpic 62>;
	120	marvell,pcie-port = <1>;
	121	marvell,pcie-lane = <0>;
	122	clocks = <&gateclk 9>;
	123	status = "disabled";
	124	};
	125	};
	126
467f54b2	127	internal-regs {
467f54b2 GC	128	L2: l2-cache {
467f54b2 GC	129	compatible = "marvell,aurora-outer-cache";
489e138e	130	reg = <0x08000 0x1000>;
467f54b2	131	cache-id-part = <0x100>;
292a3546	132	cache-level = <2>;
a9ce1afb	133	cache-unified;
467f54b2	134	wt-override;
fa1b21d1	135	};
879d68a4	136
a095b1c7 JC	137	i2c0: i2c@11000 {
	138	reg = <0x11000 0x20>;
	139	};
	140
	141	i2c1: i2c@11100 {
	142	reg = <0x11100 0x20>;
	143	};
	144
467f54b2 GC	145	gpio0: gpio@18100 {
	146	compatible = "marvell,orion-gpio";
	147	reg = <0x18100 0x40>;
	148	ngpios = <32>;
	149	gpio-controller;
	150	#gpio-cells = <2>;
	151	interrupt-controller;
ca60985c	152	#interrupt-cells = <2>;
467f54b2	153	interrupts = <82>, <83>, <84>, <85>;
0122eee8	154	};
b2bb806f	155
467f54b2 GC	156	gpio1: gpio@18140 {
	157	compatible = "marvell,orion-gpio";
	158	reg = <0x18140 0x40>;
	159	ngpios = <32>;
	160	gpio-controller;
	161	#gpio-cells = <2>;
	162	interrupt-controller;
ca60985c	163	#interrupt-cells = <2>;
467f54b2 GC	164	interrupts = <87>, <88>, <89>, <90>;
467f54b2 GC	165	};
b2bb806f	166
467f54b2 GC	167	gpio2: gpio@18180 {
	168	compatible = "marvell,orion-gpio";
	169	reg = <0x18180 0x40>;
	170	ngpios = <2>;
	171	gpio-controller;
	172	#gpio-cells = <2>;
	173	interrupt-controller;
ca60985c	174	#interrupt-cells = <2>;
467f54b2 GC	175	interrupts = <91>;
467f54b2 GC	176	};
a09a0b7c	177
f8afeaea AE	178	/*
	179	* Default UART pinctrl setting without RTS/CTS, can
	180	* be overwritten on board level if a different
	181	* configuration is used.
	182	*/
	183	uart0: serial@12000 {
	184	pinctrl-0 = <&uart0_pins>;
	185	pinctrl-names = "default";
	186	};
	187
	188	uart1: serial@12100 {
	189	pinctrl-0 = <&uart1_pins>;
	190	pinctrl-names = "default";
	191	};
	192
ab1e8537 UKK	193	system-controller@18200 {
	194	compatible = "marvell,armada-370-xp-system-controller";
	195	reg = <0x18200 0x100>;
	196	};
	197
a095b1c7 JC	198	gateclk: clock-gating-control@18220 {
	199	compatible = "marvell,armada-370-gating-clock";
	200	reg = <0x18220 0x4>;
	201	clocks = <&coreclk 0>;
	202	#clock-cells = <1>;
5d3b8830 EG	203	};
5d3b8830 EG	204
467f54b2 GC	205	coreclk: mvebu-sar@18230 {
	206	compatible = "marvell,armada-370-core-clock";
	207	reg = <0x18230 0x08>;
	208	#clock-cells = <1>;
	209	};
a09a0b7c	210
a095b1c7 JC	211	thermal@18300 {
	212	compatible = "marvell,armada370-thermal";
	213	reg = <0x18300 0x4
	214	0x18304 0x4>;
	215	status = "okay";
	216	};
	217
e86ed56a GC	218	sscg@18330 {
	219	reg = <0x18330 0x4>;
	220	};
	221
24c2573b	222	interrupt-controller@20a00 {
a095b1c7 JC	223	reg = <0x20a00 0x1d0>, <0x21870 0x58>;
	224	};
	225
	226	timer@20300 {
	227	compatible = "marvell,armada-370-timer";
	228	clocks = <&coreclk 2>;
	229	};
	230
05afeeb9 EG	231	watchdog@20300 {
	232	compatible = "marvell,armada-370-wdt";
	233	clocks = <&coreclk 2>;
	234	};
	235
b6249d4b GC	236	cpurst@20800 {
	237	compatible = "marvell,armada-370-cpu-reset";
	238	reg = <0x20800 0x8>;
	239	};
	240
97dd823e TP	241	cpu-config@21000 {
	242	compatible = "marvell,armada-370-cpu-config";
	243	reg = <0x21000 0x8>;
	244	};
	245
74839835	246	audio_controller: audio-controller@30000 {
a6b33451	247	#sound-dai-cells = <1>;
74839835 TP	248	compatible = "marvell,armada370-audio";
	249	reg = <0x30000 0x4000>;
	250	interrupts = <93>;
	251	clocks = <&gateclk 0>;
	252	clock-names = "internal";
	253	status = "disabled";
	254	};
	255
a095b1c7 JC	256	usb@50000 {
	257	clocks = <&coreclk 0>;
	258	};
	259
	260	usb@51000 {
467f54b2	261	clocks = <&coreclk 0>;
467f54b2	262	};
a09a0b7c	263
467f54b2 GC	264	xor@60800 {
	265	compatible = "marvell,orion-xor";
	266	reg = <0x60800 0x100
	267	0x60A00 0x100>;
	268	status = "okay";
	269
	270	xor00 {
	271	interrupts = <51>;
	272	dmacap,memcpy;
	273	dmacap,xor;
	274	};
	275	xor01 {
	276	interrupts = <52>;
	277	dmacap,memcpy;
	278	dmacap,xor;
	279	dmacap,memset;
	280	};
	281	};
a09a0b7c	282
467f54b2 GC	283	xor@60900 {
	284	compatible = "marvell,orion-xor";
	285	reg = <0x60900 0x100
	286	0x60b00 0x100>;
	287	status = "okay";
	288
	289	xor10 {
	290	interrupts = <94>;
	291	dmacap,memcpy;
	292	dmacap,xor;
	293	};
	294	xor11 {
	295	interrupts = <95>;
	296	dmacap,memcpy;
	297	dmacap,xor;
	298	dmacap,memset;
	299	};
	300	};
ea3b55fe SG	301
	302	ethernet@70000 {
	303	compatible = "marvell,armada-370-neta";
	304	};
	305
	306	ethernet@74000 {
	307	compatible = "marvell,armada-370-neta";
	308	};
2dbcdb11 AE	309
	310	crypto@90000 {
	311	compatible = "marvell,armada-370-crypto";
	312	reg = <0x90000 0x10000>;
	313	reg-names = "regs";
	314	interrupts = <48>;
	315	clocks = <&gateclk 23>;
	316	clock-names = "cesa0";
	317	marvell,crypto-srams = <&crypto_sram>;
	318	marvell,crypto-sram-size = <0x7e0>;
	319	};
	320	};
	321
	322	crypto_sram: sa-sram {
	323	compatible = "mmio-sram";
	324	reg = <MBUS_ID(0x09, 0x01) 0 0x800>;
	325	reg-names = "sram";
	326	clocks = <&gateclk 23>;
	327	#address-cells = <1>;
	328	#size-cells = <1>;
	329	ranges = <0 MBUS_ID(0x09, 0x01) 0 0x800>;
	330
	331	/*
	332	* The Armada 370 has an erratum preventing the use of
	333	* the standard workflow for CPU idle support (relying
	334	* on the BootROM code to enter/exit idle state).
	335	* Reserve some amount of the crypto SRAM to put the
	336	* cpuidle workaround.
	337	*/
	338	idle-sram@0 {
	339	reg = <0x0 0x20>;
	340	};
a09a0b7c	341	};
9ae6f740 TP	342	};
9ae6f740 TP	343	};
4904a82a AE	344
	345	&pinctrl {
	346	compatible = "marvell,mv88f6710-pinctrl";
	347
a6fa8475 AE	348	spi0_pins1: spi0-pins1 {
	349	marvell,pins = "mpp33", "mpp34",
	350	"mpp35", "mpp36";
	351	marvell,function = "spi0";
	352	};
	353
	354	spi0_pins2: spi0_pins2 {
	355	marvell,pins = "mpp32", "mpp63",
	356	"mpp64", "mpp65";
	357	marvell,function = "spi0";
	358	};
	359
	360	spi1_pins: spi1-pins {
	361	marvell,pins = "mpp49", "mpp50",
	362	"mpp51", "mpp52";
	363	marvell,function = "spi1";
	364	};
	365
f8afeaea AE	366	uart0_pins: uart0-pins {
	367	marvell,pins = "mpp0", "mpp1";
	368	marvell,function = "uart0";
	369	};
	370
	371	uart1_pins: uart1-pins {
	372	marvell,pins = "mpp41", "mpp42";
	373	marvell,function = "uart1";
	374	};
	375
4904a82a AE	376	sdio_pins1: sdio-pins1 {
	377	marvell,pins = "mpp9", "mpp11", "mpp12",
	378	"mpp13", "mpp14", "mpp15";
	379	marvell,function = "sd0";
	380	};
	381
	382	sdio_pins2: sdio-pins2 {
	383	marvell,pins = "mpp47", "mpp48", "mpp49",
	384	"mpp50", "mpp51", "mpp52";
	385	marvell,function = "sd0";
	386	};
	387
	388	sdio_pins3: sdio-pins3 {
	389	marvell,pins = "mpp48", "mpp49", "mpp50",
	390	"mpp51", "mpp52", "mpp53";
	391	marvell,function = "sd0";
	392	};
	393
	394	i2c0_pins: i2c0-pins {
	395	marvell,pins = "mpp2", "mpp3";
	396	marvell,function = "i2c0";
	397	};
	398
	399	i2s_pins1: i2s-pins1 {
	400	marvell,pins = "mpp5", "mpp6", "mpp7",
	401	"mpp8", "mpp9", "mpp10",
	402	"mpp12", "mpp13";
	403	marvell,function = "audio";
	404	};
	405
	406	i2s_pins2: i2s-pins2 {
	407	marvell,pins = "mpp49", "mpp47", "mpp50",
	408	"mpp59", "mpp57", "mpp61",
	409	"mpp62", "mpp60", "mpp58";
	410	marvell,function = "audio";
	411	};
	412
	413	mdio_pins: mdio-pins {
	414	marvell,pins = "mpp17", "mpp18";
	415	marvell,function = "ge";
	416	};
	417
	418	ge0_rgmii_pins: ge0-rgmii-pins {
	419	marvell,pins = "mpp5", "mpp6", "mpp7", "mpp8",
	420	"mpp9", "mpp10", "mpp11", "mpp12",
	421	"mpp13", "mpp14", "mpp15", "mpp16";
	422	marvell,function = "ge0";
	423	};
	424
	425	ge1_rgmii_pins: ge1-rgmii-pins {
	426	marvell,pins = "mpp19", "mpp20", "mpp21", "mpp22",
	427	"mpp23", "mpp24", "mpp25", "mpp26",
	428	"mpp27", "mpp28", "mpp29", "mpp30";
	429	marvell,function = "ge1";
	430	};
	431	};
0160a4b6 SR	432
	433	/*
	434	* Default SPI pinctrl setting, can be overwritten on
	435	* board level if a different configuration is used.
	436	*/
	437	&spi0 {
	438	compatible = "marvell,armada-370-spi", "marvell,orion-spi";
	439	pinctrl-0 = <&spi0_pins1>;
	440	pinctrl-names = "default";
	441	};
	442
	443	&spi1 {
	444	compatible = "marvell,armada-370-spi", "marvell,orion-spi";
	445	pinctrl-0 = <&spi1_pins>;
	446	pinctrl-names = "default";
	447	};