[deliverable/linux.git] / arch / arm / boot / dts / armada-xp-db.dts

/*
 * Device Tree file for Marvell Armada XP evaluation board
 * (DB-78460-BP)
 *
 * Copyright (C) 2012-2014 Marvell
 *
 * Lior Amsalem <alior@marvell.com>
 * Gregory CLEMENT <gregory.clement@free-electrons.com>
 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 *  a) This file is free software; you can redistribute it and/or
 *     modify it under the terms of the GNU General Public License as
 *     published by the Free Software Foundation; either version 2 of the
 *     License, or (at your option) any later version.
 *
 *     This file is distributed in the hope that it will be useful
 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *     GNU General Public License for more details.
 *
 * Or, alternatively
 *
 *  b) Permission is hereby granted, free of charge, to any person
 *     obtaining a copy of this software and associated documentation
 *     files (the "Software"), to deal in the Software without
 *     restriction, including without limitation the rights to use
 *     copy, modify, merge, publish, distribute, sublicense, and/or
 *     sell copies of the Software, and to permit persons to whom the
 *     Software is furnished to do so, subject to the following
 *     conditions:
 *
 *     The above copyright notice and this permission notice shall be
 *     included in all copies or substantial portions of the Software.
 *
 *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 *     OTHER DEALINGS IN THE SOFTWARE.
  *
 * Note: this Device Tree assumes that the bootloader has remapped the
 * internal registers to 0xf1000000 (instead of the default
 * 0xd0000000). The 0xf1000000 is the default used by the recent,
 * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
 * boards were delivered with an older version of the bootloader that
 * left internal registers mapped at 0xd0000000. If you are in this
 * situation, you should either update your bootloader (preferred
 * solution) or the below Device Tree should be adjusted.
 */

/dts-v1/;
#include "armada-xp-mv78460.dtsi"

/ {
	model = "Marvell Armada XP Evaluation Board";
	compatible = "marvell,axp-db", "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp";

	chosen {
		stdout-path = "serial0:115200n8";
	};

	memory {
		device_type = "memory";
		reg = <0 0x00000000 0 0x80000000>; /* 2 GB */
	};

	soc {
		ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
			  MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
			  MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000
			  MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000
			  MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000
			  MBUS_ID(0x0c, 0x04) 0 0 0xf1200000 0x100000>;

		devbus-bootcs {
			status = "okay";

			/* Device Bus parameters are required */

			/* Read parameters */
			devbus,bus-width    = <16>;
			devbus,turn-off-ps  = <60000>;
			devbus,badr-skew-ps = <0>;
			devbus,acc-first-ps = <124000>;
			devbus,acc-next-ps  = <248000>;
			devbus,rd-setup-ps  = <0>;
			devbus,rd-hold-ps   = <0>;

			/* Write parameters */
			devbus,sync-enable = <0>;
			devbus,wr-high-ps  = <60000>;
			devbus,wr-low-ps   = <60000>;
			devbus,ale-wr-ps   = <60000>;

			/* NOR 16 MiB */
			nor@0 {
				compatible = "cfi-flash";
				reg = <0 0x1000000>;
				bank-width = <2>;
			};
		};

		pcie-controller {
			status = "okay";

			/*
			 * All 6 slots are physically present as
			 * standard PCIe slots on the board.
			 */
			pcie@1,0 {
				/* Port 0, Lane 0 */
				status = "okay";
			};
			pcie@2,0 {
				/* Port 0, Lane 1 */
				status = "okay";
			};
			pcie@3,0 {
				/* Port 0, Lane 2 */
				status = "okay";
			};
			pcie@4,0 {
				/* Port 0, Lane 3 */
				status = "okay";
			};
			pcie@9,0 {
				/* Port 2, Lane 0 */
				status = "okay";
			};
			pcie@10,0 {
				/* Port 3, Lane 0 */
				status = "okay";
			};
		};

		internal-regs {
			serial@12000 {
				status = "okay";
			};
			serial@12100 {
				status = "okay";
			};
			serial@12200 {
				status = "okay";
			};
			serial@12300 {
				status = "okay";
			};

			sata@a0000 {
				nr-ports = <2>;
				status = "okay";
			};

			mdio {
				phy0: ethernet-phy@0 {
					reg = <0>;
				};

				phy1: ethernet-phy@1 {
					reg = <1>;
				};

				phy2: ethernet-phy@2 {
					reg = <25>;
				};

				phy3: ethernet-phy@3 {
					reg = <27>;
				};
			};

			ethernet@70000 {
				status = "okay";
				phy = <&phy0>;
				phy-mode = "rgmii-id";
				buffer-manager = <&bm>;
				bm,pool-long = <0>;
			};
			ethernet@74000 {
				status = "okay";
				phy = <&phy1>;
				phy-mode = "rgmii-id";
				buffer-manager = <&bm>;
				bm,pool-long = <1>;
			};
			ethernet@30000 {
				status = "okay";
				phy = <&phy2>;
				phy-mode = "sgmii";
				buffer-manager = <&bm>;
				bm,pool-long = <2>;
			};
			ethernet@34000 {
				status = "okay";
				phy = <&phy3>;
				phy-mode = "sgmii";
				buffer-manager = <&bm>;
				bm,pool-long = <3>;
			};

			bm@c0000 {
				status = "okay";
			};

			mvsdio@d4000 {
				pinctrl-0 = <&sdio_pins>;
				pinctrl-names = "default";
				status = "okay";
				/* No CD or WP GPIOs */
				broken-cd;
			};

			usb@50000 {
				status = "okay";
			};

			usb@51000 {
				status = "okay";
			};

			usb@52000 {
				status = "okay";
			};

			nand@d0000 {
				status = "okay";
				num-cs = <1>;
				marvell,nand-keep-config;
				marvell,nand-enable-arbiter;
				nand-on-flash-bbt;

				partitions {
					compatible = "fixed-partitions";
					#address-cells = <1>;
					#size-cells = <1>;

					partition@0 {
						label = "U-Boot";
						reg = <0 0x800000>;
					};
					partition@800000 {
						label = "Linux";
						reg = <0x800000 0x800000>;
					};
					partition@1000000 {
						label = "Filesystem";
						reg = <0x1000000 0x3f000000>;

					};
				};
			};
		};

		bm-bppi {
			status = "okay";
		};
	};
};

&spi0 {
	status = "okay";

	spi-flash@0 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "m25p64", "jedec,spi-nor";
		reg = <0>; /* Chip select 0 */
		spi-max-frequency = <20000000>;
	};
};
Commit	Line	Data
9ae6f740 TP	1	/*
	2	* Device Tree file for Marvell Armada XP evaluation board
	3	* (DB-78460-BP)
	4	*
82066bdb	5	* Copyright (C) 2012-2014 Marvell
9ae6f740 TP	6	*
	7	* Lior Amsalem <alior@marvell.com>
	8	* Gregory CLEMENT <gregory.clement@free-electrons.com>
	9	* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
	10	*
d5272edd GC	11	* This file is dual-licensed: you can use it either under the terms
	12	* of the GPL or the X11 license, at your option. Note that this dual
	13	* licensing only applies to this file, and not this project as a
	14	* whole.
	15	*
	16	* a) This file is free software; you can redistribute it and/or
	17	* modify it under the terms of the GNU General Public License as
	18	* published by the Free Software Foundation; either version 2 of the
	19	* License, or (at your option) any later version.
	20	*
	21	* This file is distributed in the hope that it will be useful
	22	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	23	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	24	* GNU General Public License for more details.
	25	*
	26	* Or, alternatively
	27	*
	28	* b) Permission is hereby granted, free of charge, to any person
	29	* obtaining a copy of this software and associated documentation
	30	* files (the "Software"), to deal in the Software without
	31	* restriction, including without limitation the rights to use
	32	* copy, modify, merge, publish, distribute, sublicense, and/or
	33	* sell copies of the Software, and to permit persons to whom the
	34	* Software is furnished to do so, subject to the following
	35	* conditions:
	36	*
	37	* The above copyright notice and this permission notice shall be
	38	* included in all copies or substantial portions of the Software.
	39	*
	40	* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
	41	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
	42	* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	43	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
	44	* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
	45	* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	46	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	47	* OTHER DEALINGS IN THE SOFTWARE.
82066bdb TP	48	*
	49	* Note: this Device Tree assumes that the bootloader has remapped the
	50	* internal registers to 0xf1000000 (instead of the default
	51	* 0xd0000000). The 0xf1000000 is the default used by the recent,
	52	* DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
	53	* boards were delivered with an older version of the bootloader that
	54	* left internal registers mapped at 0xd0000000. If you are in this
	55	* situation, you should either update your bootloader (preferred
	56	* solution) or the below Device Tree should be adjusted.
9ae6f740 TP	57	*/
	58
	59	/dts-v1/;
38149887	60	#include "armada-xp-mv78460.dtsi"
9ae6f740 TP	61
	62	/ {
	63	model = "Marvell Armada XP Evaluation Board";
0bec30a7	64	compatible = "marvell,axp-db", "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp";
9ae6f740 TP	65
9ae6f740 TP	66	chosen {
9552203c	67	stdout-path = "serial0:115200n8";
9ae6f740 TP	68	};
	69
	70	memory {
	71	device_type = "memory";
74898364	72	reg = <0 0x00000000 0 0x80000000>; /* 2 GB */
9ae6f740 TP	73	};
	74
	75	soc {
82066bdb	76	ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
de1af8d4	77	MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
c466d997	78	MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000
d7d5a43c	79	MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000
1200b680	80	MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000
9dd7a57e	81	MBUS_ID(0x0c, 0x04) 0 0 0xf1200000 0x100000>;
de1af8d4 EG	82
	83	devbus-bootcs {
	84	status = "okay";
	85
	86	/* Device Bus parameters are required */
	87
	88	/* Read parameters */
f3aec8f3	89	devbus,bus-width = <16>;
de1af8d4 EG	90	devbus,turn-off-ps = <60000>;
	91	devbus,badr-skew-ps = <0>;
	92	devbus,acc-first-ps = <124000>;
	93	devbus,acc-next-ps = <248000>;
	94	devbus,rd-setup-ps = <0>;
	95	devbus,rd-hold-ps = <0>;
	96
	97	/* Write parameters */
	98	devbus,sync-enable = <0>;
	99	devbus,wr-high-ps = <60000>;
	100	devbus,wr-low-ps = <60000>;
	101	devbus,ale-wr-ps = <60000>;
	102
	103	/* NOR 16 MiB */
	104	nor@0 {
	105	compatible = "cfi-flash";
	106	reg = <0 0x1000000>;
	107	bank-width = <2>;
	108	};
	109	};
b484ff42	110
14fd8ed0 EG	111	pcie-controller {
	112	status = "okay";
	113
	114	/*
	115	* All 6 slots are physically present as
	116	* standard PCIe slots on the board.
	117	*/
	118	pcie@1,0 {
	119	/* Port 0, Lane 0 */
	120	status = "okay";
	121	};
	122	pcie@2,0 {
	123	/* Port 0, Lane 1 */
	124	status = "okay";
	125	};
	126	pcie@3,0 {
	127	/* Port 0, Lane 2 */
	128	status = "okay";
	129	};
	130	pcie@4,0 {
	131	/* Port 0, Lane 3 */
	132	status = "okay";
	133	};
	134	pcie@9,0 {
	135	/* Port 2, Lane 0 */
	136	status = "okay";
	137	};
	138	pcie@10,0 {
	139	/* Port 3, Lane 0 */
	140	status = "okay";
	141	};
	142	};
	143
467f54b2 GC	144	internal-regs {
467f54b2 GC	145	serial@12000 {
467f54b2	146	status = "okay";
f01959a9	147	};
467f54b2	148	serial@12100 {
467f54b2	149	status = "okay";
f01959a9	150	};
467f54b2	151	serial@12200 {
467f54b2	152	status = "okay";
f01959a9	153	};
467f54b2	154	serial@12300 {
467f54b2	155	status = "okay";
f01959a9	156	};
200506b1	157
467f54b2 GC	158	sata@a0000 {
	159	nr-ports = <2>;
	160	status = "okay";
	161	};
200506b1	162
467f54b2 GC	163	mdio {
	164	phy0: ethernet-phy@0 {
	165	reg = <0>;
	166	};
200506b1	167
467f54b2 GC	168	phy1: ethernet-phy@1 {
	169	reg = <1>;
	170	};
1f24a21f	171
467f54b2 GC	172	phy2: ethernet-phy@2 {
	173	reg = <25>;
	174	};
1f24a21f	175
467f54b2 GC	176	phy3: ethernet-phy@3 {
	177	reg = <27>;
	178	};
1f24a21f	179	};
bf4f9c63	180
467f54b2 GC	181	ethernet@70000 {
	182	status = "okay";
	183	phy = <&phy0>;
	184	phy-mode = "rgmii-id";
9dd7a57e MW	185	buffer-manager = <&bm>;
9dd7a57e MW	186	bm,pool-long = <0>;
467f54b2 GC	187	};
	188	ethernet@74000 {
	189	status = "okay";
	190	phy = <&phy1>;
	191	phy-mode = "rgmii-id";
9dd7a57e MW	192	buffer-manager = <&bm>;
9dd7a57e MW	193	bm,pool-long = <1>;
467f54b2 GC	194	};
	195	ethernet@30000 {
	196	status = "okay";
	197	phy = <&phy2>;
	198	phy-mode = "sgmii";
9dd7a57e MW	199	buffer-manager = <&bm>;
9dd7a57e MW	200	bm,pool-long = <2>;
467f54b2 GC	201	};
	202	ethernet@34000 {
	203	status = "okay";
	204	phy = <&phy3>;
	205	phy-mode = "sgmii";
9dd7a57e MW	206	buffer-manager = <&bm>;
	207	bm,pool-long = <3>;
	208	};
	209
	210	bm@c0000 {
	211	status = "okay";
467f54b2	212	};
bf4f9c63	213
467f54b2 GC	214	mvsdio@d4000 {
	215	pinctrl-0 = <&sdio_pins>;
	216	pinctrl-names = "default";
bf4f9c63	217	status = "okay";
467f54b2	218	/* No CD or WP GPIOs */
d87b5fbb	219	broken-cd;
bf4f9c63	220	};
467f54b2 GC	221
467f54b2 GC	222	usb@50000 {
bf4f9c63 TP	223	status = "okay";
bf4f9c63 TP	224	};
467f54b2 GC	225
467f54b2 GC	226	usb@51000 {
bf4f9c63 TP	227	status = "okay";
bf4f9c63 TP	228	};
467f54b2 GC	229
467f54b2 GC	230	usb@52000 {
bf4f9c63 TP	231	status = "okay";
bf4f9c63 TP	232	};
467f54b2	233
af5ece39 TP	234	nand@d0000 {
	235	status = "okay";
	236	num-cs = <1>;
	237	marvell,nand-keep-config;
	238	marvell,nand-enable-arbiter;
	239	nand-on-flash-bbt;
	240
	241	partitions {
	242	compatible = "fixed-partitions";
	243	#address-cells = <1>;
	244	#size-cells = <1>;
	245
	246	partition@0 {
	247	label = "U-Boot";
	248	reg = <0 0x800000>;
	249	};
	250	partition@800000 {
	251	label = "Linux";
	252	reg = <0x800000 0x800000>;
	253	};
	254	partition@1000000 {
	255	label = "Filesystem";
	256	reg = <0x1000000 0x3f000000>;
	257
	258	};
	259	};
	260	};
bf4f9c63	261	};
9dd7a57e MW	262
	263	bm-bppi {
	264	status = "okay";
	265	};
9ae6f740 TP	266	};
9ae6f740 TP	267	};
0160a4b6 SR	268
	269	&spi0 {
	270	status = "okay";
	271
	272	spi-flash@0 {
	273	#address-cells = <1>;
	274	#size-cells = <1>;
	275	compatible = "m25p64", "jedec,spi-nor";
	276	reg = <0>; /* Chip select 0 */
	277	spi-max-frequency = <20000000>;
	278	};
	279	};