[deliverable/linux.git] / arch / arm / boot / dts / dove.dtsi

/include/ "skeleton.dtsi"

#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))

/ {
	compatible = "marvell,dove";
	model = "Marvell Armada 88AP510 SoC";

	aliases {
		gpio0 = &gpio0;
		gpio1 = &gpio1;
		gpio2 = &gpio2;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			compatible = "marvell,pj4a", "marvell,sheeva-v7";
			device_type = "cpu";
			next-level-cache = <&l2>;
			reg = <0>;
		};
	};

	l2: l2-cache {
		compatible = "marvell,tauros2-cache";
		marvell,tauros2-cache-features = <0>;
	};

	soc@f1000000 {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		interrupt-parent = <&intc>;

		ranges = <0xc8000000 0xc8000000 0x0100000   /* CESA SRAM   1M */
		          0xe0000000 0xe0000000 0x8000000   /* PCIe0 Mem 128M */
		          0xe8000000 0xe8000000 0x8000000   /* PCIe1 Mem 128M */
		          0xf0000000 0xf0000000 0x0100000   /* ScratchPad  1M */
		          0x00000000 0xf1000000 0x1000000   /* SB/NB regs 16M */
		          0xf2000000 0xf2000000 0x0100000   /* PCIe0 I/O   1M */
		          0xf2100000 0xf2100000 0x0100000   /* PCIe0 I/O   1M */
		          0xf8000000 0xf8000000 0x8000000>; /* BootROM   128M */

		timer: timer@20300 {
			compatible = "marvell,orion-timer";
			reg = <0x20300 0x20>;
			interrupt-parent = <&bridge_intc>;
			interrupts = <1>, <2>;
			clocks = <&core_clk 0>;
		};

		intc: main-interrupt-ctrl@20200 {
			compatible = "marvell,orion-intc";
			interrupt-controller;
			#interrupt-cells = <1>;
			reg = <0x20200 0x10>, <0x20210 0x10>;
		};

		bridge_intc: bridge-interrupt-ctrl@20110 {
			compatible = "marvell,orion-bridge-intc";
			interrupt-controller;
			#interrupt-cells = <1>;
			reg = <0x20110 0x8>;
			interrupts = <0>;
			marvell,#interrupts = <5>;
		};

		core_clk: core-clocks@d0214 {
			compatible = "marvell,dove-core-clock";
			reg = <0xd0214 0x4>;
			#clock-cells = <1>;
		};

		gate_clk: clock-gating-ctrl@d0038 {
			compatible = "marvell,dove-gating-clock";
			reg = <0xd0038 0x4>;
			clocks = <&core_clk 0>;
			#clock-cells = <1>;
		};

		thermal: thermal-diode@d001c {
			compatible = "marvell,dove-thermal";
			reg = <0xd001c 0x0c>, <0xd005c 0x08>;
		};

		uart0: serial@12000 {
			compatible = "ns16550a";
			reg = <0x12000 0x100>;
			reg-shift = <2>;
			interrupts = <7>;
			clocks = <&core_clk 0>;
			status = "disabled";
		};

		uart1: serial@12100 {
			compatible = "ns16550a";
			reg = <0x12100 0x100>;
			reg-shift = <2>;
			interrupts = <8>;
			clocks = <&core_clk 0>;
			pinctrl-0 = <&pmx_uart1>;
			pinctrl-names = "default";
			status = "disabled";
		};

		uart2: serial@12200 {
			compatible = "ns16550a";
			reg = <0x12000 0x100>;
			reg-shift = <2>;
			interrupts = <9>;
			clocks = <&core_clk 0>;
			status = "disabled";
		};

		uart3: serial@12300 {
			compatible = "ns16550a";
			reg = <0x12100 0x100>;
			reg-shift = <2>;
			interrupts = <10>;
			clocks = <&core_clk 0>;
			status = "disabled";
		};

		gpio0: gpio-ctrl@d0400 {
			compatible = "marvell,orion-gpio";
			#gpio-cells = <2>;
			gpio-controller;
			reg = <0xd0400 0x20>;
			ngpios = <32>;
			interrupt-controller;
			#interrupt-cells = <2>;
			interrupts = <12>, <13>, <14>, <60>;
		};

		gpio1: gpio-ctrl@d0420 {
			compatible = "marvell,orion-gpio";
			#gpio-cells = <2>;
			gpio-controller;
			reg = <0xd0420 0x20>;
			ngpios = <32>;
			interrupt-controller;
			#interrupt-cells = <2>;
			interrupts = <61>;
		};

		gpio2: gpio-ctrl@e8400 {
			compatible = "marvell,orion-gpio";
			#gpio-cells = <2>;
			gpio-controller;
			reg = <0xe8400 0x0c>;
			ngpios = <8>;
		};

		pinctrl: pin-ctrl@d0200 {
			compatible = "marvell,dove-pinctrl";
			reg = <0xd0200 0x10>;
			clocks = <&gate_clk 22>;

			pmx_gpio_0: pmx-gpio-0 {
				marvell,pins = "mpp0";
				marvell,function = "gpio";
			};

			pmx_gpio_1: pmx-gpio-1 {
				marvell,pins = "mpp1";
				marvell,function = "gpio";
			};

			pmx_gpio_2: pmx-gpio-2 {
				marvell,pins = "mpp2";
				marvell,function = "gpio";
			};

			pmx_gpio_3: pmx-gpio-3 {
				marvell,pins = "mpp3";
				marvell,function = "gpio";
			};

			pmx_gpio_4: pmx-gpio-4 {
				marvell,pins = "mpp4";
				marvell,function = "gpio";
			};

			pmx_gpio_5: pmx-gpio-5 {
				marvell,pins = "mpp5";
				marvell,function = "gpio";
			};

			pmx_gpio_6: pmx-gpio-6 {
				marvell,pins = "mpp6";
				marvell,function = "gpio";
			};

			pmx_gpio_7: pmx-gpio-7 {
				marvell,pins = "mpp7";
				marvell,function = "gpio";
			};

			pmx_gpio_8: pmx-gpio-8 {
				marvell,pins = "mpp8";
				marvell,function = "gpio";
			};

			pmx_gpio_9: pmx-gpio-9 {
				marvell,pins = "mpp9";
				marvell,function = "gpio";
			};

			pmx_gpio_10: pmx-gpio-10 {
				marvell,pins = "mpp10";
				marvell,function = "gpio";
			};

			pmx_gpio_11: pmx-gpio-11 {
				marvell,pins = "mpp11";
				marvell,function = "gpio";
			};

			pmx_gpio_12: pmx-gpio-12 {
				marvell,pins = "mpp12";
				marvell,function = "gpio";
			};

			pmx_gpio_13: pmx-gpio-13 {
				marvell,pins = "mpp13";
				marvell,function = "gpio";
			};

			pmx_gpio_14: pmx-gpio-14 {
				marvell,pins = "mpp14";
				marvell,function = "gpio";
			};

			pmx_gpio_15: pmx-gpio-15 {
				marvell,pins = "mpp15";
				marvell,function = "gpio";
			};

			pmx_gpio_16: pmx-gpio-16 {
				marvell,pins = "mpp16";
				marvell,function = "gpio";
			};

			pmx_gpio_17: pmx-gpio-17 {
				marvell,pins = "mpp17";
				marvell,function = "gpio";
			};

			pmx_gpio_18: pmx-gpio-18 {
				marvell,pins = "mpp18";
				marvell,function = "gpio";
			};

			pmx_gpio_19: pmx-gpio-19 {
				marvell,pins = "mpp19";
				marvell,function = "gpio";
			};

			pmx_gpio_20: pmx-gpio-20 {
				marvell,pins = "mpp20";
				marvell,function = "gpio";
			};

			pmx_gpio_21: pmx-gpio-21 {
				marvell,pins = "mpp21";
				marvell,function = "gpio";
			};

			pmx_camera: pmx-camera {
				marvell,pins = "mpp_camera";
				marvell,function = "camera";
			};

			pmx_camera_gpio: pmx-camera-gpio {
				marvell,pins = "mpp_camera";
				marvell,function = "gpio";
			};

			pmx_sdio0: pmx-sdio0 {
				marvell,pins = "mpp_sdio0";
				marvell,function = "sdio0";
			};

			pmx_sdio0_gpio: pmx-sdio0-gpio {
				marvell,pins = "mpp_sdio0";
				marvell,function = "gpio";
			};

			pmx_sdio1: pmx-sdio1 {
				marvell,pins = "mpp_sdio1";
				marvell,function = "sdio1";
			};

			pmx_sdio1_gpio: pmx-sdio1-gpio {
				marvell,pins = "mpp_sdio1";
				marvell,function = "gpio";
			};

			pmx_audio1_gpio: pmx-audio1-gpio {
				marvell,pins = "mpp_audio1";
				marvell,function = "gpio";
			};

			pmx_spi0: pmx-spi0 {
				marvell,pins = "mpp_spi0";
				marvell,function = "spi0";
			};

			pmx_spi0_gpio: pmx-spi0-gpio {
				marvell,pins = "mpp_spi0";
				marvell,function = "gpio";
			};

			pmx_uart1: pmx-uart1 {
				marvell,pins = "mpp_uart1";
				marvell,function = "uart1";
			};

			pmx_uart1_gpio: pmx-uart1-gpio {
				marvell,pins = "mpp_uart1";
				marvell,function = "gpio";
			};

			pmx_nand: pmx-nand {
				marvell,pins = "mpp_nand";
				marvell,function = "nand";
			};

			pmx_nand_gpo: pmx-nand-gpo {
				marvell,pins = "mpp_nand";
				marvell,function = "gpo";
			};
		};

		spi0: spi-ctrl@10600 {
			compatible = "marvell,orion-spi";
			#address-cells = <1>;
			#size-cells = <0>;
			cell-index = <0>;
			interrupts = <6>;
			reg = <0x10600 0x28>;
			clocks = <&core_clk 0>;
			pinctrl-0 = <&pmx_spi0>;
			pinctrl-names = "default";
			status = "disabled";
		};

		spi1: spi-ctrl@14600 {
			compatible = "marvell,orion-spi";
			#address-cells = <1>;
			#size-cells = <0>;
			cell-index = <1>;
			interrupts = <5>;
			reg = <0x14600 0x28>;
			clocks = <&core_clk 0>;
			status = "disabled";
		};

		i2c0: i2c-ctrl@11000 {
			compatible = "marvell,mv64xxx-i2c";
			reg = <0x11000 0x20>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <11>;
			clock-frequency = <400000>;
			timeout-ms = <1000>;
			clocks = <&core_clk 0>;
			status = "disabled";
		};

		ehci0: usb-host@50000 {
			compatible = "marvell,orion-ehci";
			reg = <0x50000 0x1000>;
			interrupts = <24>;
			clocks = <&gate_clk 0>;
			status = "okay";
		};

		ehci1: usb-host@51000 {
			compatible = "marvell,orion-ehci";
			reg = <0x51000 0x1000>;
			interrupts = <25>;
			clocks = <&gate_clk 1>;
			status = "okay";
		};

		sdio0: sdio-host@92000 {
			compatible = "marvell,dove-sdhci";
			reg = <0x92000 0x100>;
			interrupts = <35>, <37>;
			clocks = <&gate_clk 8>;
			pinctrl-0 = <&pmx_sdio0>;
			pinctrl-names = "default";
			status = "disabled";
		};

		sdio1: sdio-host@90000 {
			compatible = "marvell,dove-sdhci";
			reg = <0x90000 0x100>;
			interrupts = <36>, <38>;
			clocks = <&gate_clk 9>;
			pinctrl-0 = <&pmx_sdio1>;
			pinctrl-names = "default";
			status = "disabled";
		};

		sata0: sata-host@a0000 {
			compatible = "marvell,orion-sata";
			reg = <0xa0000 0x2400>;
			interrupts = <62>;
			clocks = <&gate_clk 3>;
			nr-ports = <1>;
			status = "disabled";
		};

		rtc: real-time-clock@d8500 {
			compatible = "marvell,orion-rtc";
			reg = <0xd8500 0x20>;
		};

		crypto: crypto-engine@30000 {
			compatible = "marvell,orion-crypto";
			reg = <0x30000 0x10000>,
			      <0xc8000000 0x800>;
			reg-names = "regs", "sram";
			interrupts = <31>;
			clocks = <&gate_clk 15>;
			status = "okay";
		};

		xor0: dma-engine@60800 {
			compatible = "marvell,orion-xor";
			reg = <0x60800 0x100
			       0x60a00 0x100>;
			clocks = <&gate_clk 23>;
			status = "okay";

			channel0 {
				interrupts = <39>;
				dmacap,memcpy;
				dmacap,xor;
			};

			channel1 {
				interrupts = <40>;
				dmacap,memset;
				dmacap,memcpy;
				dmacap,xor;
			};
		};

		xor1: dma-engine@60900 {
			compatible = "marvell,orion-xor";
			reg = <0x60900 0x100
			       0x60b00 0x100>;
			clocks = <&gate_clk 24>;
			status = "okay";

			channel0 {
				interrupts = <42>;
				dmacap,memcpy;
				dmacap,xor;
			};

			channel1 {
				interrupts = <43>;
				dmacap,memset;
				dmacap,memcpy;
				dmacap,xor;
			};
		};

		mdio: mdio-bus@72004 {
			compatible = "marvell,orion-mdio";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x72004 0x84>;
			interrupts = <30>;
			clocks = <&gate_clk 2>;
			status = "disabled";

			ethphy: ethernet-phy {
				device-type = "ethernet-phy";
				/* set phy address in board file */
			};
		};

		eth: ethernet-controller@72000 {
			compatible = "marvell,orion-eth";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x72000 0x4000>;
			clocks = <&gate_clk 2>;
			marvell,tx-checksum-limit = <1600>;
			status = "disabled";

			ethernet-port@0 {
				device_type = "network";
				compatible = "marvell,orion-eth-port";
				reg = <0>;
				interrupts = <29>;
				/* overwrite MAC address in bootloader */
				local-mac-address = [00 00 00 00 00 00];
				phy-handle = <&ethphy>;
			};
		};
	};
};
Commit	Line	Data
80a8b54b SH	1	/include/ "skeleton.dtsi"
80a8b54b SH	2
6953af77 SH	3	#define MBUS_ID(target,attributes) (((target) << 24) \| ((attributes) << 16))
6953af77 SH	4
80a8b54b SH	5	/ {
	6	compatible = "marvell,dove";
	7	model = "Marvell Armada 88AP510 SoC";
	8
9139acd1 SH	9	aliases {
	10	gpio0 = &gpio0;
	11	gpio1 = &gpio1;
	12	gpio2 = &gpio2;
	13	};
	14
2d299834 SH	15	cpus {
	16	#address-cells = <1>;
	17	#size-cells = <0>;
	18
	19	cpu0: cpu@0 {
	20	compatible = "marvell,pj4a", "marvell,sheeva-v7";
	21	device_type = "cpu";
	22	next-level-cache = <&l2>;
	23	reg = <0>;
	24	};
	25	};
	26
	27	l2: l2-cache {
	28	compatible = "marvell,tauros2-cache";
	29	marvell,tauros2-cache-features = <0>;
	30	};
	31
138ee960	32	soc@f1000000 {
80a8b54b	33	compatible = "simple-bus";
80a8b54b SH	34	#address-cells = <1>;
80a8b54b SH	35	#size-cells = <1>;
138ee960 SH	36	interrupt-parent = <&intc>;
	37
	38	ranges = <0xc8000000 0xc8000000 0x0100000 /* CESA SRAM 1M */
	39	0xe0000000 0xe0000000 0x8000000 /* PCIe0 Mem 128M */
	40	0xe8000000 0xe8000000 0x8000000 /* PCIe1 Mem 128M */
	41	0xf0000000 0xf0000000 0x0100000 /* ScratchPad 1M */
	42	0x00000000 0xf1000000 0x1000000 /* SB/NB regs 16M */
	43	0xf2000000 0xf2000000 0x0100000 /* PCIe0 I/O 1M */
	44	0xf2100000 0xf2100000 0x0100000 /* PCIe0 I/O 1M */
	45	0xf8000000 0xf8000000 0x8000000>; /* BootROM 128M */
80a8b54b	46
953b710c SH	47	timer: timer@20300 {
	48	compatible = "marvell,orion-timer";
	49	reg = <0x20300 0x20>;
	50	interrupt-parent = <&bridge_intc>;
	51	interrupts = <1>, <2>;
	52	clocks = <&core_clk 0>;
	53	};
	54
	55	intc: main-interrupt-ctrl@20200 {
138ee960 SH	56	compatible = "marvell,orion-intc";
	57	interrupt-controller;
	58	#interrupt-cells = <1>;
953b710c SH	59	reg = <0x20200 0x10>, <0x20210 0x10>;
	60	};
	61
	62	bridge_intc: bridge-interrupt-ctrl@20110 {
	63	compatible = "marvell,orion-bridge-intc";
	64	interrupt-controller;
	65	#interrupt-cells = <1>;
	66	reg = <0x20110 0x8>;
	67	interrupts = <0>;
	68	marvell,#interrupts = <5>;
138ee960 SH	69	};
138ee960 SH	70
5b03df9a SH	71	core_clk: core-clocks@d0214 {
	72	compatible = "marvell,dove-core-clock";
	73	reg = <0xd0214 0x4>;
	74	#clock-cells = <1>;
	75	};
	76
2d299834	77	gate_clk: clock-gating-ctrl@d0038 {
5b03df9a SH	78	compatible = "marvell,dove-gating-clock";
	79	reg = <0xd0038 0x4>;
	80	clocks = <&core_clk 0>;
	81	#clock-cells = <1>;
	82	};
	83
2d299834	84	thermal: thermal-diode@d001c {
c3117ede AL	85	compatible = "marvell,dove-thermal";
	86	reg = <0xd001c 0x0c>, <0xd005c 0x08>;
	87	};
	88
80a8b54b SH	89	uart0: serial@12000 {
	90	compatible = "ns16550a";
	91	reg = <0x12000 0x100>;
	92	reg-shift = <2>;
	93	interrupts = <7>;
8be7a962	94	clocks = <&core_clk 0>;
80a8b54b SH	95	status = "disabled";
	96	};
	97
	98	uart1: serial@12100 {
	99	compatible = "ns16550a";
	100	reg = <0x12100 0x100>;
	101	reg-shift = <2>;
	102	interrupts = <8>;
8be7a962	103	clocks = <&core_clk 0>;
2d299834 SH	104	pinctrl-0 = <&pmx_uart1>;
2d299834 SH	105	pinctrl-names = "default";
80a8b54b SH	106	status = "disabled";
	107	};
	108
	109	uart2: serial@12200 {
	110	compatible = "ns16550a";
	111	reg = <0x12000 0x100>;
	112	reg-shift = <2>;
	113	interrupts = <9>;
8be7a962	114	clocks = <&core_clk 0>;
80a8b54b SH	115	status = "disabled";
	116	};
	117
	118	uart3: serial@12300 {
	119	compatible = "ns16550a";
	120	reg = <0x12100 0x100>;
	121	reg-shift = <2>;
	122	interrupts = <10>;
8be7a962	123	clocks = <&core_clk 0>;
80a8b54b SH	124	status = "disabled";
	125	};
	126
2d299834	127	gpio0: gpio-ctrl@d0400 {
80a8b54b SH	128	compatible = "marvell,orion-gpio";
	129	#gpio-cells = <2>;
	130	gpio-controller;
	131	reg = <0xd0400 0x20>;
9139acd1 SH	132	ngpios = <32>;
9139acd1 SH	133	interrupt-controller;
fd2704e8	134	#interrupt-cells = <2>;
80a8b54b SH	135	interrupts = <12>, <13>, <14>, <60>;
	136	};
	137
2d299834	138	gpio1: gpio-ctrl@d0420 {
80a8b54b SH	139	compatible = "marvell,orion-gpio";
	140	#gpio-cells = <2>;
	141	gpio-controller;
	142	reg = <0xd0420 0x20>;
9139acd1 SH	143	ngpios = <32>;
9139acd1 SH	144	interrupt-controller;
fd2704e8	145	#interrupt-cells = <2>;
80a8b54b SH	146	interrupts = <61>;
	147	};
	148
2d299834	149	gpio2: gpio-ctrl@e8400 {
80a8b54b SH	150	compatible = "marvell,orion-gpio";
	151	#gpio-cells = <2>;
	152	gpio-controller;
	153	reg = <0xe8400 0x0c>;
9139acd1 SH	154	ngpios = <8>;
	155	};
	156
2d299834	157	pinctrl: pin-ctrl@d0200 {
9139acd1 SH	158	compatible = "marvell,dove-pinctrl";
9139acd1 SH	159	reg = <0xd0200 0x10>;
db7d77e6	160	clocks = <&gate_clk 22>;
2d299834 SH	161
	162	pmx_gpio_0: pmx-gpio-0 {
	163	marvell,pins = "mpp0";
	164	marvell,function = "gpio";
	165	};
	166
	167	pmx_gpio_1: pmx-gpio-1 {
	168	marvell,pins = "mpp1";
	169	marvell,function = "gpio";
	170	};
	171
	172	pmx_gpio_2: pmx-gpio-2 {
	173	marvell,pins = "mpp2";
	174	marvell,function = "gpio";
	175	};
	176
	177	pmx_gpio_3: pmx-gpio-3 {
	178	marvell,pins = "mpp3";
	179	marvell,function = "gpio";
	180	};
	181
	182	pmx_gpio_4: pmx-gpio-4 {
	183	marvell,pins = "mpp4";
	184	marvell,function = "gpio";
	185	};
	186
	187	pmx_gpio_5: pmx-gpio-5 {
	188	marvell,pins = "mpp5";
	189	marvell,function = "gpio";
	190	};
	191
	192	pmx_gpio_6: pmx-gpio-6 {
	193	marvell,pins = "mpp6";
	194	marvell,function = "gpio";
	195	};
	196
	197	pmx_gpio_7: pmx-gpio-7 {
	198	marvell,pins = "mpp7";
	199	marvell,function = "gpio";
	200	};
	201
	202	pmx_gpio_8: pmx-gpio-8 {
	203	marvell,pins = "mpp8";
	204	marvell,function = "gpio";
	205	};
	206
	207	pmx_gpio_9: pmx-gpio-9 {
	208	marvell,pins = "mpp9";
	209	marvell,function = "gpio";
	210	};
	211
	212	pmx_gpio_10: pmx-gpio-10 {
	213	marvell,pins = "mpp10";
	214	marvell,function = "gpio";
	215	};
	216
	217	pmx_gpio_11: pmx-gpio-11 {
	218	marvell,pins = "mpp11";
	219	marvell,function = "gpio";
	220	};
	221
	222	pmx_gpio_12: pmx-gpio-12 {
	223	marvell,pins = "mpp12";
	224	marvell,function = "gpio";
225	};
226
227	pmx_gpio_13: pmx-gpio-13 {
228	marvell,pins = "mpp13";
229	marvell,function = "gpio";
230	};
231
232	pmx_gpio_14: pmx-gpio-14 {
233	marvell,pins = "mpp14";
234	marvell,function = "gpio";
235	};
236
237	pmx_gpio_15: pmx-gpio-15 {
238	marvell,pins = "mpp15";
239	marvell,function = "gpio";
240	};
241
242	pmx_gpio_16: pmx-gpio-16 {
243	marvell,pins = "mpp16";
244	marvell,function = "gpio";
245	};
246
247	pmx_gpio_17: pmx-gpio-17 {
248	marvell,pins = "mpp17";
249	marvell,function = "gpio";
250	};
251
252	pmx_gpio_18: pmx-gpio-18 {
253	marvell,pins = "mpp18";
254	marvell,function = "gpio";
255	};
256
257	pmx_gpio_19: pmx-gpio-19 {
258	marvell,pins = "mpp19";
259	marvell,function = "gpio";
260	};
261
262	pmx_gpio_20: pmx-gpio-20 {
263	marvell,pins = "mpp20";
264	marvell,function = "gpio";
265	};
266
267	pmx_gpio_21: pmx-gpio-21 {
268	marvell,pins = "mpp21";
269	marvell,function = "gpio";
270	};
271
272	pmx_camera: pmx-camera {
273	marvell,pins = "mpp_camera";
274	marvell,function = "camera";
275	};
276
277	pmx_camera_gpio: pmx-camera-gpio {
278	marvell,pins = "mpp_camera";
279	marvell,function = "gpio";
280	};
281
282	pmx_sdio0: pmx-sdio0 {
283	marvell,pins = "mpp_sdio0";
284	marvell,function = "sdio0";
285	};
286
287	pmx_sdio0_gpio: pmx-sdio0-gpio {
288	marvell,pins = "mpp_sdio0";
289	marvell,function = "gpio";
290	};
291
292	pmx_sdio1: pmx-sdio1 {
293	marvell,pins = "mpp_sdio1";
294	marvell,function = "sdio1";
295	};
296
297	pmx_sdio1_gpio: pmx-sdio1-gpio {
298	marvell,pins = "mpp_sdio1";
299	marvell,function = "gpio";
300	};
301
302	pmx_audio1_gpio: pmx-audio1-gpio {
303	marvell,pins = "mpp_audio1";
304	marvell,function = "gpio";
305	};
306
307	pmx_spi0: pmx-spi0 {
308	marvell,pins = "mpp_spi0";
309	marvell,function = "spi0";
310	};
311
312	pmx_spi0_gpio: pmx-spi0-gpio {
313	marvell,pins = "mpp_spi0";
314	marvell,function = "gpio";
315	};
316
317	pmx_uart1: pmx-uart1 {
318	marvell,pins = "mpp_uart1";
319	marvell,function = "uart1";
320	};
321
322	pmx_uart1_gpio: pmx-uart1-gpio {
323	marvell,pins = "mpp_uart1";
324	marvell,function = "gpio";
325	};
326
327	pmx_nand: pmx-nand {
328	marvell,pins = "mpp_nand";
329	marvell,function = "nand";
330	};
331
332	pmx_nand_gpo: pmx-nand-gpo {
333	marvell,pins = "mpp_nand";
334	marvell,function = "gpo";
335	};
80a8b54b SH	336	};
80a8b54b SH	337
2d299834	338	spi0: spi-ctrl@10600 {
80a8b54b SH	339	compatible = "marvell,orion-spi";
	340	#address-cells = <1>;
	341	#size-cells = <0>;
	342	cell-index = <0>;
	343	interrupts = <6>;
	344	reg = <0x10600 0x28>;
5b03df9a	345	clocks = <&core_clk 0>;
2d299834 SH	346	pinctrl-0 = <&pmx_spi0>;
2d299834 SH	347	pinctrl-names = "default";
80a8b54b SH	348	status = "disabled";
	349	};
	350
2d299834	351	spi1: spi-ctrl@14600 {
80a8b54b SH	352	compatible = "marvell,orion-spi";
	353	#address-cells = <1>;
	354	#size-cells = <0>;
	355	cell-index = <1>;
	356	interrupts = <5>;
	357	reg = <0x14600 0x28>;
5b03df9a	358	clocks = <&core_clk 0>;
80a8b54b SH	359	status = "disabled";
	360	};
	361
2d299834	362	i2c0: i2c-ctrl@11000 {
80a8b54b SH	363	compatible = "marvell,mv64xxx-i2c";
	364	reg = <0x11000 0x20>;
	365	#address-cells = <1>;
	366	#size-cells = <0>;
	367	interrupts = <11>;
	368	clock-frequency = <400000>;
	369	timeout-ms = <1000>;
5b03df9a	370	clocks = <&core_clk 0>;
80a8b54b SH	371	status = "disabled";
	372	};
	373
a1abcd7c SH	374	ehci0: usb-host@50000 {
	375	compatible = "marvell,orion-ehci";
	376	reg = <0x50000 0x1000>;
	377	interrupts = <24>;
	378	clocks = <&gate_clk 0>;
	379	status = "okay";
	380	};
	381
	382	ehci1: usb-host@51000 {
	383	compatible = "marvell,orion-ehci";
	384	reg = <0x51000 0x1000>;
	385	interrupts = <25>;
	386	clocks = <&gate_clk 1>;
	387	status = "okay";
	388	};
	389
2d299834	390	sdio0: sdio-host@92000 {
80a8b54b SH	391	compatible = "marvell,dove-sdhci";
	392	reg = <0x92000 0x100>;
	393	interrupts = <35>, <37>;
5b03df9a	394	clocks = <&gate_clk 8>;
2d299834 SH	395	pinctrl-0 = <&pmx_sdio0>;
2d299834 SH	396	pinctrl-names = "default";
80a8b54b SH	397	status = "disabled";
	398	};
	399
2d299834	400	sdio1: sdio-host@90000 {
80a8b54b SH	401	compatible = "marvell,dove-sdhci";
	402	reg = <0x90000 0x100>;
	403	interrupts = <36>, <38>;
5b03df9a	404	clocks = <&gate_clk 9>;
2d299834 SH	405	pinctrl-0 = <&pmx_sdio1>;
2d299834 SH	406	pinctrl-names = "default";
80a8b54b SH	407	status = "disabled";
	408	};
	409
2d299834	410	sata0: sata-host@a0000 {
80a8b54b SH	411	compatible = "marvell,orion-sata";
	412	reg = <0xa0000 0x2400>;
	413	interrupts = <62>;
5b03df9a	414	clocks = <&gate_clk 3>;
80a8b54b SH	415	nr-ports = <1>;
	416	status = "disabled";
	417	};
a458926e	418
2d299834	419	rtc: real-time-clock@d8500 {
85c0c13d JFM	420	compatible = "marvell,orion-rtc";
	421	reg = <0xd8500 0x20>;
	422	};
	423
2d299834	424	crypto: crypto-engine@30000 {
a458926e SH	425	compatible = "marvell,orion-crypto";
	426	reg = <0x30000 0x10000>,
	427	<0xc8000000 0x800>;
	428	reg-names = "regs", "sram";
	429	interrupts = <31>;
5b03df9a	430	clocks = <&gate_clk 15>;
a458926e SH	431	status = "okay";
a458926e SH	432	};
49f175b9 SH	433
	434	xor0: dma-engine@60800 {
	435	compatible = "marvell,orion-xor";
	436	reg = <0x60800 0x100
	437	0x60a00 0x100>;
	438	clocks = <&gate_clk 23>;
a458926e	439	status = "okay";
49f175b9 SH	440
	441	channel0 {
	442	interrupts = <39>;
	443	dmacap,memcpy;
	444	dmacap,xor;
	445	};
	446
	447	channel1 {
	448	interrupts = <40>;
	449	dmacap,memset;
	450	dmacap,memcpy;
	451	dmacap,xor;
	452	};
	453	};
	454
	455	xor1: dma-engine@60900 {
	456	compatible = "marvell,orion-xor";
	457	reg = <0x60900 0x100
	458	0x60b00 0x100>;
	459	clocks = <&gate_clk 24>;
	460	status = "okay";
	461
	462	channel0 {
	463	interrupts = <42>;
	464	dmacap,memcpy;
	465	dmacap,xor;
	466	};
	467
	468	channel1 {
	469	interrupts = <43>;
	470	dmacap,memset;
	471	dmacap,memcpy;
	472	dmacap,xor;
	473	};
a458926e	474	};
4c3f6b86 SH	475
	476	mdio: mdio-bus@72004 {
	477	compatible = "marvell,orion-mdio";
	478	#address-cells = <1>;
	479	#size-cells = <0>;
	480	reg = <0x72004 0x84>;
	481	interrupts = <30>;
	482	clocks = <&gate_clk 2>;
	483	status = "disabled";
	484
	485	ethphy: ethernet-phy {
	486	device-type = "ethernet-phy";
	487	/* set phy address in board file */
	488	};
	489	};
	490
	491	eth: ethernet-controller@72000 {
	492	compatible = "marvell,orion-eth";
	493	#address-cells = <1>;
	494	#size-cells = <0>;
	495	reg = <0x72000 0x4000>;
	496	clocks = <&gate_clk 2>;
	497	marvell,tx-checksum-limit = <1600>;
	498	status = "disabled";
	499
	500	ethernet-port@0 {
	501	device_type = "network";
	502	compatible = "marvell,orion-eth-port";
	503	reg = <0>;
	504	interrupts = <29>;
	505	/* overwrite MAC address in bootloader */
	506	local-mac-address = [00 00 00 00 00 00];
	507	phy-handle = <&ethphy>;
	508	};
	509	};
80a8b54b SH	510	};
80a8b54b SH	511	};