[deliverable/linux.git] / arch / arm / boot / dts / exynos3250.dtsi

/*
 * Samsung's Exynos3250 SoC device tree source
 *
 * Copyright (c) 2014 Samsung Electronics Co., Ltd.
 *		http://www.samsung.com
 *
 * Samsung's Exynos3250 SoC device nodes are listed in this file. Exynos3250
 * based board files can include this file and provide values for board specfic
 * bindings.
 *
 * Note: This file does not include device nodes for all the controllers in
 * Exynos3250 SoC. As device tree coverage for Exynos3250 increases, additional
 * nodes can be added to this file.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include "skeleton.dtsi"
#include "exynos4-cpu-thermal.dtsi"
#include <dt-bindings/clock/exynos3250.h>

/ {
	compatible = "samsung,exynos3250";
	interrupt-parent = <&gic>;

	aliases {
		pinctrl0 = &pinctrl_0;
		pinctrl1 = &pinctrl_1;
		mshc0 = &mshc_0;
		mshc1 = &mshc_1;
		spi0 = &spi_0;
		spi1 = &spi_1;
		i2c0 = &i2c_0;
		i2c1 = &i2c_1;
		i2c2 = &i2c_2;
		i2c3 = &i2c_3;
		i2c4 = &i2c_4;
		i2c5 = &i2c_5;
		i2c6 = &i2c_6;
		i2c7 = &i2c_7;
		serial0 = &serial_0;
		serial1 = &serial_1;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0>;
			clock-frequency = <1000000000>;
			clocks = <&cmu CLK_ARM_CLK>;
			clock-names = "cpu";

			operating-points = <
				1000000 1150000
				900000  1112500
				800000  1075000
				700000  1037500
				600000  1000000
				500000  962500
				400000  925000
				300000  887500
				200000  850000
				100000  850000
			>;
		};

		cpu1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <1>;
			clock-frequency = <1000000000>;
		};
	};

	soc: soc {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		fixed-rate-clocks {
			#address-cells = <1>;
			#size-cells = <0>;

			xusbxti: clock@0 {
				compatible = "fixed-clock";
				#address-cells = <1>;
				#size-cells = <0>;
				reg = <0>;
				clock-frequency = <0>;
				#clock-cells = <0>;
				clock-output-names = "xusbxti";
			};

			xxti: clock@1 {
				compatible = "fixed-clock";
				reg = <1>;
				clock-frequency = <0>;
				#clock-cells = <0>;
				clock-output-names = "xxti";
			};

			xtcxo: clock@2 {
				compatible = "fixed-clock";
				reg = <2>;
				clock-frequency = <0>;
				#clock-cells = <0>;
				clock-output-names = "xtcxo";
			};
		};

		sysram@02020000 {
			compatible = "mmio-sram";
			reg = <0x02020000 0x40000>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 0x02020000 0x40000>;

			smp-sysram@0 {
				compatible = "samsung,exynos4210-sysram";
				reg = <0x0 0x1000>;
			};

			smp-sysram@3f000 {
				compatible = "samsung,exynos4210-sysram-ns";
				reg = <0x3f000 0x1000>;
			};
		};

		chipid@10000000 {
			compatible = "samsung,exynos4210-chipid";
			reg = <0x10000000 0x100>;
		};

		sys_reg: syscon@10010000 {
			compatible = "samsung,exynos3-sysreg", "syscon";
			reg = <0x10010000 0x400>;
		};

		pmu_system_controller: system-controller@10020000 {
			compatible = "samsung,exynos3250-pmu", "syscon";
			reg = <0x10020000 0x4000>;
			interrupt-controller;
			#interrupt-cells = <3>;
			interrupt-parent = <&gic>;
		};

		mipi_phy: video-phy@10020710 {
			compatible = "samsung,s5pv210-mipi-video-phy";
			#phy-cells = <1>;
			syscon = <&pmu_system_controller>;
		};

		pd_cam: cam-power-domain@10023C00 {
			compatible = "samsung,exynos4210-pd";
			reg = <0x10023C00 0x20>;
			#power-domain-cells = <0>;
		};

		pd_mfc: mfc-power-domain@10023C40 {
			compatible = "samsung,exynos4210-pd";
			reg = <0x10023C40 0x20>;
			#power-domain-cells = <0>;
		};

		pd_g3d: g3d-power-domain@10023C60 {
			compatible = "samsung,exynos4210-pd";
			reg = <0x10023C60 0x20>;
			#power-domain-cells = <0>;
		};

		pd_lcd0: lcd0-power-domain@10023C80 {
			compatible = "samsung,exynos4210-pd";
			reg = <0x10023C80 0x20>;
			#power-domain-cells = <0>;
		};

		pd_isp: isp-power-domain@10023CA0 {
			compatible = "samsung,exynos4210-pd";
			reg = <0x10023CA0 0x20>;
			#power-domain-cells = <0>;
		};

		cmu: clock-controller@10030000 {
			compatible = "samsung,exynos3250-cmu";
			reg = <0x10030000 0x20000>;
			#clock-cells = <1>;
			assigned-clocks = <&cmu CLK_MOUT_ACLK_400_MCUISP_SUB>,
					  <&cmu CLK_MOUT_ACLK_266_SUB>;
			assigned-clock-parents = <&cmu CLK_FIN_PLL>,
						 <&cmu CLK_FIN_PLL>;
		};

		cmu_dmc: clock-controller@105C0000 {
			compatible = "samsung,exynos3250-cmu-dmc";
			reg = <0x105C0000 0x2000>;
			#clock-cells = <1>;
		};

		rtc: rtc@10070000 {
			compatible = "samsung,s3c6410-rtc";
			reg = <0x10070000 0x100>;
			interrupts = <0 73 0>, <0 74 0>;
			interrupt-parent = <&pmu_system_controller>;
			status = "disabled";
		};

		tmu: tmu@100C0000 {
			compatible = "samsung,exynos3250-tmu";
			reg = <0x100C0000 0x100>;
			interrupts = <0 216 0>;
			clocks = <&cmu CLK_TMU_APBIF>;
			clock-names = "tmu_apbif";
			#include "exynos4412-tmu-sensor-conf.dtsi"
			status = "disabled";
		};

		gic: interrupt-controller@10481000 {
			compatible = "arm,cortex-a15-gic";
			#interrupt-cells = <3>;
			interrupt-controller;
			reg = <0x10481000 0x1000>,
			      <0x10482000 0x1000>,
			      <0x10484000 0x2000>,
			      <0x10486000 0x2000>;
			interrupts = <1 9 0xf04>;
		};

		mct@10050000 {
			compatible = "samsung,exynos4210-mct";
			reg = <0x10050000 0x800>;
			interrupts = <0 218 0>, <0 219 0>, <0 220 0>, <0 221 0>,
				     <0 223 0>, <0 226 0>, <0 227 0>, <0 228 0>;
			clocks = <&cmu CLK_FIN_PLL>, <&cmu CLK_MCT>;
			clock-names = "fin_pll", "mct";
		};

		pinctrl_1: pinctrl@11000000 {
			compatible = "samsung,exynos3250-pinctrl";
			reg = <0x11000000 0x1000>;
			interrupts = <0 225 0>;

			wakeup-interrupt-controller {
				compatible = "samsung,exynos4210-wakeup-eint";
				interrupts = <0 48 0>;
			};
		};

		pinctrl_0: pinctrl@11400000 {
			compatible = "samsung,exynos3250-pinctrl";
			reg = <0x11400000 0x1000>;
			interrupts = <0 240 0>;
		};

		jpeg: codec@11830000 {
			compatible = "samsung,exynos3250-jpeg";
			reg = <0x11830000 0x1000>;
			interrupts = <0 171 0>;
			clocks = <&cmu CLK_JPEG>, <&cmu CLK_SCLK_JPEG>;
			clock-names = "jpeg", "sclk";
			power-domains = <&pd_cam>;
			assigned-clocks = <&cmu CLK_MOUT_CAM_BLK>, <&cmu CLK_SCLK_JPEG>;
			assigned-clock-rates = <0>, <150000000>;
			assigned-clock-parents = <&cmu CLK_DIV_MPLL_PRE>;
			iommus = <&sysmmu_jpeg>;
			status = "disabled";
		};

		sysmmu_jpeg: sysmmu@11A60000 {
			compatible = "samsung,exynos-sysmmu";
			reg = <0x11a60000 0x1000>;
			interrupts = <0 156 0>, <0 161 0>;
			clock-names = "sysmmu", "master";
			clocks = <&cmu CLK_SMMUJPEG>, <&cmu CLK_JPEG>;
			power-domains = <&pd_cam>;
			#iommu-cells = <0>;
		};

		fimd: fimd@11c00000 {
			compatible = "samsung,exynos3250-fimd";
			reg = <0x11c00000 0x30000>;
			interrupt-names = "fifo", "vsync", "lcd_sys";
			interrupts = <0 84 0>, <0 85 0>, <0 86 0>;
			clocks = <&cmu CLK_SCLK_FIMD0>, <&cmu CLK_FIMD0>;
			clock-names = "sclk_fimd", "fimd";
			power-domains = <&pd_lcd0>;
			iommus = <&sysmmu_fimd0>;
			samsung,sysreg = <&sys_reg>;
			status = "disabled";
		};

		dsi_0: dsi@11C80000 {
			compatible = "samsung,exynos3250-mipi-dsi";
			reg = <0x11C80000 0x10000>;
			interrupts = <0 83 0>;
			samsung,phy-type = <0>;
			power-domains = <&pd_lcd0>;
			phys = <&mipi_phy 1>;
			phy-names = "dsim";
			clocks = <&cmu CLK_DSIM0>, <&cmu CLK_SCLK_MIPI0>;
			clock-names = "bus_clk", "pll_clk";
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		sysmmu_fimd0: sysmmu@11E20000 {
			compatible = "samsung,exynos-sysmmu";
			reg = <0x11e20000 0x1000>;
			interrupts = <0 80 0>, <0 81 0>;
			clock-names = "sysmmu", "master";
			clocks = <&cmu CLK_SMMUFIMD0>, <&cmu CLK_FIMD0>;
			power-domains = <&pd_lcd0>;
			#iommu-cells = <0>;
		};

		hsotg: hsotg@12480000 {
			compatible = "snps,dwc2";
			reg = <0x12480000 0x20000>;
			interrupts = <0 141 0>;
			clocks = <&cmu CLK_USBOTG>;
			clock-names = "otg";
			phys = <&exynos_usbphy 0>;
			phy-names = "usb2-phy";
			status = "disabled";
		};

		mshc_0: mshc@12510000 {
			compatible = "samsung,exynos5250-dw-mshc";
			reg = <0x12510000 0x1000>;
			interrupts = <0 142 0>;
			clocks = <&cmu CLK_SDMMC0>, <&cmu CLK_SCLK_MMC0>;
			clock-names = "biu", "ciu";
			fifo-depth = <0x80>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		mshc_1: mshc@12520000 {
			compatible = "samsung,exynos5250-dw-mshc";
			reg = <0x12520000 0x1000>;
			interrupts = <0 143 0>;
			clocks = <&cmu CLK_SDMMC1>, <&cmu CLK_SCLK_MMC1>;
			clock-names = "biu", "ciu";
			fifo-depth = <0x80>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		exynos_usbphy: exynos-usbphy@125B0000 {
			compatible = "samsung,exynos3250-usb2-phy";
			reg = <0x125B0000 0x100>;
			samsung,pmureg-phandle = <&pmu_system_controller>;
			clocks = <&cmu CLK_USBOTG>, <&cmu CLK_SCLK_UPLL>;
			clock-names = "phy", "ref";
			#phy-cells = <1>;
			status = "disabled";
		};

		amba {
			compatible = "arm,amba-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

			pdma0: pdma@12680000 {
				compatible = "arm,pl330", "arm,primecell";
				reg = <0x12680000 0x1000>;
				interrupts = <0 138 0>;
				clocks = <&cmu CLK_PDMA0>;
				clock-names = "apb_pclk";
				#dma-cells = <1>;
				#dma-channels = <8>;
				#dma-requests = <32>;
			};

			pdma1: pdma@12690000 {
				compatible = "arm,pl330", "arm,primecell";
				reg = <0x12690000 0x1000>;
				interrupts = <0 139 0>;
				clocks = <&cmu CLK_PDMA1>;
				clock-names = "apb_pclk";
				#dma-cells = <1>;
				#dma-channels = <8>;
				#dma-requests = <32>;
			};
		};

		adc: adc@126C0000 {
			compatible = "samsung,exynos3250-adc",
				     "samsung,exynos-adc-v2";
			reg = <0x126C0000 0x100>;
			interrupts = <0 137 0>;
			clock-names = "adc", "sclk";
			clocks = <&cmu CLK_TSADC>, <&cmu CLK_SCLK_TSADC>;
			#io-channel-cells = <1>;
			io-channel-ranges;
			samsung,syscon-phandle = <&pmu_system_controller>;
			status = "disabled";
		};

		mfc: codec@13400000 {
			compatible = "samsung,mfc-v7";
			reg = <0x13400000 0x10000>;
			interrupts = <0 102 0>;
			clock-names = "mfc", "sclk_mfc";
			clocks = <&cmu CLK_MFC>, <&cmu CLK_SCLK_MFC>;
			power-domains = <&pd_mfc>;
			iommus = <&sysmmu_mfc>;
			status = "disabled";
		};

		sysmmu_mfc: sysmmu@13620000 {
			compatible = "samsung,exynos-sysmmu";
			reg = <0x13620000 0x1000>;
			interrupts = <0 96 0>, <0 98 0>;
			clock-names = "sysmmu", "master";
			clocks = <&cmu CLK_SMMUMFC_L>, <&cmu CLK_MFC>;
			power-domains = <&pd_mfc>;
			#iommu-cells = <0>;
		};

		serial_0: serial@13800000 {
			compatible = "samsung,exynos4210-uart";
			reg = <0x13800000 0x100>;
			interrupts = <0 109 0>;
			clocks = <&cmu CLK_UART0>, <&cmu CLK_SCLK_UART0>;
			clock-names = "uart", "clk_uart_baud0";
			pinctrl-names = "default";
			pinctrl-0 = <&uart0_data &uart0_fctl>;
			status = "disabled";
		};

		serial_1: serial@13810000 {
			compatible = "samsung,exynos4210-uart";
			reg = <0x13810000 0x100>;
			interrupts = <0 110 0>;
			clocks = <&cmu CLK_UART1>, <&cmu CLK_SCLK_UART1>;
			clock-names = "uart", "clk_uart_baud0";
			pinctrl-names = "default";
			pinctrl-0 = <&uart1_data>;
			status = "disabled";
		};

		i2c_0: i2c@13860000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "samsung,s3c2440-i2c";
			reg = <0x13860000 0x100>;
			interrupts = <0 113 0>;
			clocks = <&cmu CLK_I2C0>;
			clock-names = "i2c";
			pinctrl-names = "default";
			pinctrl-0 = <&i2c0_bus>;
			status = "disabled";
		};

		i2c_1: i2c@13870000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "samsung,s3c2440-i2c";
			reg = <0x13870000 0x100>;
			interrupts = <0 114 0>;
			clocks = <&cmu CLK_I2C1>;
			clock-names = "i2c";
			pinctrl-names = "default";
			pinctrl-0 = <&i2c1_bus>;
			status = "disabled";
		};

		i2c_2: i2c@13880000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "samsung,s3c2440-i2c";
			reg = <0x13880000 0x100>;
			interrupts = <0 115 0>;
			clocks = <&cmu CLK_I2C2>;
			clock-names = "i2c";
			pinctrl-names = "default";
			pinctrl-0 = <&i2c2_bus>;
			status = "disabled";
		};

		i2c_3: i2c@13890000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "samsung,s3c2440-i2c";
			reg = <0x13890000 0x100>;
			interrupts = <0 116 0>;
			clocks = <&cmu CLK_I2C3>;
			clock-names = "i2c";
			pinctrl-names = "default";
			pinctrl-0 = <&i2c3_bus>;
			status = "disabled";
		};

		i2c_4: i2c@138A0000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "samsung,s3c2440-i2c";
			reg = <0x138A0000 0x100>;
			interrupts = <0 117 0>;
			clocks = <&cmu CLK_I2C4>;
			clock-names = "i2c";
			pinctrl-names = "default";
			pinctrl-0 = <&i2c4_bus>;
			status = "disabled";
		};

		i2c_5: i2c@138B0000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "samsung,s3c2440-i2c";
			reg = <0x138B0000 0x100>;
			interrupts = <0 118 0>;
			clocks = <&cmu CLK_I2C5>;
			clock-names = "i2c";
			pinctrl-names = "default";
			pinctrl-0 = <&i2c5_bus>;
			status = "disabled";
		};

		i2c_6: i2c@138C0000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "samsung,s3c2440-i2c";
			reg = <0x138C0000 0x100>;
			interrupts = <0 119 0>;
			clocks = <&cmu CLK_I2C6>;
			clock-names = "i2c";
			pinctrl-names = "default";
			pinctrl-0 = <&i2c6_bus>;
			status = "disabled";
		};

		i2c_7: i2c@138D0000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "samsung,s3c2440-i2c";
			reg = <0x138D0000 0x100>;
			interrupts = <0 120 0>;
			clocks = <&cmu CLK_I2C7>;
			clock-names = "i2c";
			pinctrl-names = "default";
			pinctrl-0 = <&i2c7_bus>;
			status = "disabled";
		};

		spi_0: spi@13920000 {
			compatible = "samsung,exynos4210-spi";
			reg = <0x13920000 0x100>;
			interrupts = <0 121 0>;
			dmas = <&pdma0 7>, <&pdma0 6>;
			dma-names = "tx", "rx";
			#address-cells = <1>;
			#size-cells = <0>;
			clocks = <&cmu CLK_SPI0>, <&cmu CLK_SCLK_SPI0>;
			clock-names = "spi", "spi_busclk0";
			samsung,spi-src-clk = <0>;
			pinctrl-names = "default";
			pinctrl-0 = <&spi0_bus>;
			status = "disabled";
		};

		spi_1: spi@13930000 {
			compatible = "samsung,exynos4210-spi";
			reg = <0x13930000 0x100>;
			interrupts = <0 122 0>;
			dmas = <&pdma1 7>, <&pdma1 6>;
			dma-names = "tx", "rx";
			#address-cells = <1>;
			#size-cells = <0>;
			clocks = <&cmu CLK_SPI1>, <&cmu CLK_SCLK_SPI1>;
			clock-names = "spi", "spi_busclk0";
			samsung,spi-src-clk = <0>;
			pinctrl-names = "default";
			pinctrl-0 = <&spi1_bus>;
			status = "disabled";
		};

		i2s2: i2s@13970000 {
			compatible = "samsung,s3c6410-i2s";
			reg = <0x13970000 0x100>;
			interrupts = <0 126 0>;
			clocks = <&cmu CLK_I2S>, <&cmu CLK_SCLK_I2S>;
			clock-names = "iis", "i2s_opclk0";
			dmas = <&pdma0 14>, <&pdma0 13>;
			dma-names = "tx", "rx";
			pinctrl-0 = <&i2s2_bus>;
			pinctrl-names = "default";
			status = "disabled";
		};

		pwm: pwm@139D0000 {
			compatible = "samsung,exynos4210-pwm";
			reg = <0x139D0000 0x1000>;
			interrupts = <0 104 0>, <0 105 0>, <0 106 0>,
				     <0 107 0>, <0 108 0>;
			#pwm-cells = <3>;
			status = "disabled";
		};

		pmu {
			compatible = "arm,cortex-a7-pmu";
			interrupts = <0 18 0>, <0 19 0>;
		};

		ppmu_dmc0: ppmu_dmc0@106a0000 {
			compatible = "samsung,exynos-ppmu";
			reg = <0x106a0000 0x2000>;
			status = "disabled";
		};

		ppmu_dmc1: ppmu_dmc1@106b0000 {
			compatible = "samsung,exynos-ppmu";
			reg = <0x106b0000 0x2000>;
			status = "disabled";
		};

		ppmu_cpu: ppmu_cpu@106c0000 {
			compatible = "samsung,exynos-ppmu";
			reg = <0x106c0000 0x2000>;
			status = "disabled";
		};

		ppmu_rightbus: ppmu_rightbus@112a0000 {
			compatible = "samsung,exynos-ppmu";
			reg = <0x112a0000 0x2000>;
			clocks = <&cmu CLK_PPMURIGHT>;
			clock-names = "ppmu";
			status = "disabled";
		};

		ppmu_leftbus: ppmu_leftbus0@116a0000 {
			compatible = "samsung,exynos-ppmu";
			reg = <0x116a0000 0x2000>;
			clocks = <&cmu CLK_PPMULEFT>;
			clock-names = "ppmu";
			status = "disabled";
		};

		ppmu_camif: ppmu_camif@11ac0000 {
			compatible = "samsung,exynos-ppmu";
			reg = <0x11ac0000 0x2000>;
			clocks = <&cmu CLK_PPMUCAMIF>;
			clock-names = "ppmu";
			status = "disabled";
		};

		ppmu_lcd0: ppmu_lcd0@11e40000 {
			compatible = "samsung,exynos-ppmu";
			reg = <0x11e40000 0x2000>;
			clocks = <&cmu CLK_PPMULCD0>;
			clock-names = "ppmu";
			status = "disabled";
		};

		ppmu_fsys: ppmu_fsys@12630000 {
			compatible = "samsung,exynos-ppmu";
			reg = <0x12630000 0x2000>;
			clocks = <&cmu CLK_PPMUFILE>;
			clock-names = "ppmu";
			status = "disabled";
		};

		ppmu_g3d: ppmu_g3d@13220000 {
			compatible = "samsung,exynos-ppmu";
			reg = <0x13220000 0x2000>;
			clocks = <&cmu CLK_PPMUG3D>;
			clock-names = "ppmu";
			status = "disabled";
		};

		ppmu_mfc: ppmu_mfc@13660000 {
			compatible = "samsung,exynos-ppmu";
			reg = <0x13660000 0x2000>;
			clocks = <&cmu CLK_PPMUMFC_L>;
			clock-names = "ppmu";
			status = "disabled";
		};
	};
};

#include "exynos3250-pinctrl.dtsi"
Commit	Line	Data
5a992a9c TF	1	/*
	2	* Samsung's Exynos3250 SoC device tree source
	3	*
	4	* Copyright (c) 2014 Samsung Electronics Co., Ltd.
	5	* http://www.samsung.com
	6	*
	7	* Samsung's Exynos3250 SoC device nodes are listed in this file. Exynos3250
	8	* based board files can include this file and provide values for board specfic
	9	* bindings.
	10	*
	11	* Note: This file does not include device nodes for all the controllers in
	12	* Exynos3250 SoC. As device tree coverage for Exynos3250 increases, additional
	13	* nodes can be added to this file.
	14	*
	15	* This program is free software; you can redistribute it and/or modify
	16	* it under the terms of the GNU General Public License version 2 as
	17	* published by the Free Software Foundation.
	18	*/
	19
	20	#include "skeleton.dtsi"
9843a223	21	#include "exynos4-cpu-thermal.dtsi"
5a992a9c TF	22	#include <dt-bindings/clock/exynos3250.h>
	23
	24	/ {
	25	compatible = "samsung,exynos3250";
	26	interrupt-parent = <&gic>;
	27
	28	aliases {
	29	pinctrl0 = &pinctrl_0;
	30	pinctrl1 = &pinctrl_1;
	31	mshc0 = &mshc_0;
	32	mshc1 = &mshc_1;
	33	spi0 = &spi_0;
	34	spi1 = &spi_1;
	35	i2c0 = &i2c_0;
	36	i2c1 = &i2c_1;
	37	i2c2 = &i2c_2;
	38	i2c3 = &i2c_3;
	39	i2c4 = &i2c_4;
	40	i2c5 = &i2c_5;
	41	i2c6 = &i2c_6;
	42	i2c7 = &i2c_7;
1e64f48e TF	43	serial0 = &serial_0;
1e64f48e TF	44	serial1 = &serial_1;
5a992a9c TF	45	};
	46
	47	cpus {
	48	#address-cells = <1>;
	49	#size-cells = <0>;
	50
	51	cpu0: cpu@0 {
	52	device_type = "cpu";
	53	compatible = "arm,cortex-a7";
	54	reg = <0>;
	55	clock-frequency = <1000000000>;
48816aff CC	56	clocks = <&cmu CLK_ARM_CLK>;
	57	clock-names = "cpu";
	58
	59	operating-points = <
	60	1000000 1150000
	61	900000 1112500
	62	800000 1075000
	63	700000 1037500
	64	600000 1000000
	65	500000 962500
	66	400000 925000
	67	300000 887500
	68	200000 850000
	69	100000 850000
	70	>;
5a992a9c TF	71	};
	72
	73	cpu1: cpu@1 {
	74	device_type = "cpu";
	75	compatible = "arm,cortex-a7";
	76	reg = <1>;
	77	clock-frequency = <1000000000>;
	78	};
	79	};
	80
	81	soc: soc {
	82	compatible = "simple-bus";
	83	#address-cells = <1>;
	84	#size-cells = <1>;
	85	ranges;
	86
	87	fixed-rate-clocks {
	88	#address-cells = <1>;
	89	#size-cells = <0>;
	90
	91	xusbxti: clock@0 {
	92	compatible = "fixed-clock";
	93	#address-cells = <1>;
	94	#size-cells = <0>;
	95	reg = <0>;
	96	clock-frequency = <0>;
	97	#clock-cells = <0>;
	98	clock-output-names = "xusbxti";
	99	};
	100
	101	xxti: clock@1 {
	102	compatible = "fixed-clock";
	103	reg = <1>;
	104	clock-frequency = <0>;
	105	#clock-cells = <0>;
	106	clock-output-names = "xxti";
	107	};
	108
	109	xtcxo: clock@2 {
	110	compatible = "fixed-clock";
	111	reg = <2>;
	112	clock-frequency = <0>;
	113	#clock-cells = <0>;
	114	clock-output-names = "xtcxo";
	115	};
	116	};
	117
	118	sysram@02020000 {
	119	compatible = "mmio-sram";
	120	reg = <0x02020000 0x40000>;
	121	#address-cells = <1>;
	122	#size-cells = <1>;
	123	ranges = <0 0x02020000 0x40000>;
	124
	125	smp-sysram@0 {
	126	compatible = "samsung,exynos4210-sysram";
	127	reg = <0x0 0x1000>;
	128	};
	129
	130	smp-sysram@3f000 {
	131	compatible = "samsung,exynos4210-sysram-ns";
	132	reg = <0x3f000 0x1000>;
	133	};
	134	};
135
136	chipid@10000000 {
137	compatible = "samsung,exynos4210-chipid";
138	reg = <0x10000000 0x100>;
139	};
140
141	sys_reg: syscon@10010000 {
142	compatible = "samsung,exynos3-sysreg", "syscon";
143	reg = <0x10010000 0x400>;
144	};
145
25023926 CC	146	pmu_system_controller: system-controller@10020000 {
	147	compatible = "samsung,exynos3250-pmu", "syscon";
	148	reg = <0x10020000 0x4000>;
8b283c02 MZ	149	interrupt-controller;
	150	#interrupt-cells = <3>;
	151	interrupt-parent = <&gic>;
25023926 CC	152	};
25023926 CC	153
9fab9d6a ID	154	mipi_phy: video-phy@10020710 {
9fab9d6a ID	155	compatible = "samsung,s5pv210-mipi-video-phy";
9fab9d6a	156	#phy-cells = <1>;
1342ff45	157	syscon = <&pmu_system_controller>;
9fab9d6a ID	158	};
9fab9d6a ID	159
5a992a9c TF	160	pd_cam: cam-power-domain@10023C00 {
	161	compatible = "samsung,exynos4210-pd";
	162	reg = <0x10023C00 0x20>;
0da65870	163	#power-domain-cells = <0>;
5a992a9c TF	164	};
	165
	166	pd_mfc: mfc-power-domain@10023C40 {
	167	compatible = "samsung,exynos4210-pd";
	168	reg = <0x10023C40 0x20>;
0da65870	169	#power-domain-cells = <0>;
5a992a9c TF	170	};
	171
	172	pd_g3d: g3d-power-domain@10023C60 {
	173	compatible = "samsung,exynos4210-pd";
	174	reg = <0x10023C60 0x20>;
0da65870	175	#power-domain-cells = <0>;
5a992a9c TF	176	};
	177
	178	pd_lcd0: lcd0-power-domain@10023C80 {
	179	compatible = "samsung,exynos4210-pd";
	180	reg = <0x10023C80 0x20>;
0da65870	181	#power-domain-cells = <0>;
5a992a9c TF	182	};
	183
	184	pd_isp: isp-power-domain@10023CA0 {
	185	compatible = "samsung,exynos4210-pd";
	186	reg = <0x10023CA0 0x20>;
0da65870	187	#power-domain-cells = <0>;
5a992a9c TF	188	};
	189
	190	cmu: clock-controller@10030000 {
	191	compatible = "samsung,exynos3250-cmu";
	192	reg = <0x10030000 0x20000>;
	193	#clock-cells = <1>;
52005dec BM	194	assigned-clocks = <&cmu CLK_MOUT_ACLK_400_MCUISP_SUB>,
	195	<&cmu CLK_MOUT_ACLK_266_SUB>;
	196	assigned-clock-parents = <&cmu CLK_FIN_PLL>,
	197	<&cmu CLK_FIN_PLL>;
5a992a9c TF	198	};
5a992a9c TF	199
d0e73eaf KK	200	cmu_dmc: clock-controller@105C0000 {
	201	compatible = "samsung,exynos3250-cmu-dmc";
	202	reg = <0x105C0000 0x2000>;
	203	#clock-cells = <1>;
	204	};
	205
5a992a9c	206	rtc: rtc@10070000 {
062f49c4	207	compatible = "samsung,s3c6410-rtc";
5a992a9c TF	208	reg = <0x10070000 0x100>;
5a992a9c TF	209	interrupts = <0 73 0>, <0 74 0>;
8b283c02	210	interrupt-parent = <&pmu_system_controller>;
5a992a9c TF	211	status = "disabled";
	212	};
	213
9dfb3347 CC	214	tmu: tmu@100C0000 {
	215	compatible = "samsung,exynos3250-tmu";
	216	reg = <0x100C0000 0x100>;
	217	interrupts = <0 216 0>;
	218	clocks = <&cmu CLK_TMU_APBIF>;
	219	clock-names = "tmu_apbif";
9843a223	220	#include "exynos4412-tmu-sensor-conf.dtsi"
9dfb3347 CC	221	status = "disabled";
	222	};
	223
5a992a9c TF	224	gic: interrupt-controller@10481000 {
	225	compatible = "arm,cortex-a15-gic";
	226	#interrupt-cells = <3>;
	227	interrupt-controller;
	228	reg = <0x10481000 0x1000>,
	229	<0x10482000 0x1000>,
	230	<0x10484000 0x2000>,
	231	<0x10486000 0x2000>;
	232	interrupts = <1 9 0xf04>;
	233	};
	234
	235	mct@10050000 {
	236	compatible = "samsung,exynos4210-mct";
	237	reg = <0x10050000 0x800>;
	238	interrupts = <0 218 0>, <0 219 0>, <0 220 0>, <0 221 0>,
	239	<0 223 0>, <0 226 0>, <0 227 0>, <0 228 0>;
	240	clocks = <&cmu CLK_FIN_PLL>, <&cmu CLK_MCT>;
	241	clock-names = "fin_pll", "mct";
	242	};
	243
	244	pinctrl_1: pinctrl@11000000 {
	245	compatible = "samsung,exynos3250-pinctrl";
	246	reg = <0x11000000 0x1000>;
	247	interrupts = <0 225 0>;
	248
	249	wakeup-interrupt-controller {
	250	compatible = "samsung,exynos4210-wakeup-eint";
5a992a9c TF	251	interrupts = <0 48 0>;
	252	};
	253	};
	254
	255	pinctrl_0: pinctrl@11400000 {
	256	compatible = "samsung,exynos3250-pinctrl";
	257	reg = <0x11400000 0x1000>;
	258	interrupts = <0 240 0>;
	259	};
	260
c9c1adfe JA	261	jpeg: codec@11830000 {
	262	compatible = "samsung,exynos3250-jpeg";
	263	reg = <0x11830000 0x1000>;
	264	interrupts = <0 171 0>;
	265	clocks = <&cmu CLK_JPEG>, <&cmu CLK_SCLK_JPEG>;
	266	clock-names = "jpeg", "sclk";
	267	power-domains = <&pd_cam>;
	268	assigned-clocks = <&cmu CLK_MOUT_CAM_BLK>, <&cmu CLK_SCLK_JPEG>;
	269	assigned-clock-rates = <0>, <150000000>;
	270	assigned-clock-parents = <&cmu CLK_DIV_MPLL_PRE>;
f5976ce5	271	iommus = <&sysmmu_jpeg>;
c9c1adfe JA	272	status = "disabled";
	273	};
	274
f5976ce5 MS	275	sysmmu_jpeg: sysmmu@11A60000 {
	276	compatible = "samsung,exynos-sysmmu";
	277	reg = <0x11a60000 0x1000>;
	278	interrupts = <0 156 0>, <0 161 0>;
	279	clock-names = "sysmmu", "master";
	280	clocks = <&cmu CLK_SMMUJPEG>, <&cmu CLK_JPEG>;
	281	power-domains = <&pd_cam>;
	282	#iommu-cells = <0>;
	283	};
	284
03b86c79 ID	285	fimd: fimd@11c00000 {
	286	compatible = "samsung,exynos3250-fimd";
	287	reg = <0x11c00000 0x30000>;
	288	interrupt-names = "fifo", "vsync", "lcd_sys";
	289	interrupts = <0 84 0>, <0 85 0>, <0 86 0>;
	290	clocks = <&cmu CLK_SCLK_FIMD0>, <&cmu CLK_FIMD0>;
	291	clock-names = "sclk_fimd", "fimd";
0da65870	292	power-domains = <&pd_lcd0>;
f5976ce5	293	iommus = <&sysmmu_fimd0>;
03b86c79 ID	294	samsung,sysreg = <&sys_reg>;
	295	status = "disabled";
	296	};
	297
025d8e13 ID	298	dsi_0: dsi@11C80000 {
	299	compatible = "samsung,exynos3250-mipi-dsi";
	300	reg = <0x11C80000 0x10000>;
	301	interrupts = <0 83 0>;
	302	samsung,phy-type = <0>;
0da65870	303	power-domains = <&pd_lcd0>;
025d8e13 ID	304	phys = <&mipi_phy 1>;
	305	phy-names = "dsim";
	306	clocks = <&cmu CLK_DSIM0>, <&cmu CLK_SCLK_MIPI0>;
	307	clock-names = "bus_clk", "pll_clk";
	308	#address-cells = <1>;
	309	#size-cells = <0>;
	310	status = "disabled";
	311	};
	312
f5976ce5 MS	313	sysmmu_fimd0: sysmmu@11E20000 {
	314	compatible = "samsung,exynos-sysmmu";
	315	reg = <0x11e20000 0x1000>;
	316	interrupts = <0 80 0>, <0 81 0>;
	317	clock-names = "sysmmu", "master";
	318	clocks = <&cmu CLK_SMMUFIMD0>, <&cmu CLK_FIMD0>;
	319	power-domains = <&pd_lcd0>;
	320	#iommu-cells = <0>;
	321	};
	322
e0c6e929 JK	323	hsotg: hsotg@12480000 {
	324	compatible = "snps,dwc2";
	325	reg = <0x12480000 0x20000>;
	326	interrupts = <0 141 0>;
	327	clocks = <&cmu CLK_USBOTG>;
	328	clock-names = "otg";
	329	phys = <&exynos_usbphy 0>;
	330	phy-names = "usb2-phy";
	331	status = "disabled";
	332	};
	333
5a992a9c TF	334	mshc_0: mshc@12510000 {
	335	compatible = "samsung,exynos5250-dw-mshc";
	336	reg = <0x12510000 0x1000>;
	337	interrupts = <0 142 0>;
	338	clocks = <&cmu CLK_SDMMC0>, <&cmu CLK_SCLK_MMC0>;
	339	clock-names = "biu", "ciu";
	340	fifo-depth = <0x80>;
	341	#address-cells = <1>;
	342	#size-cells = <0>;
	343	status = "disabled";
	344	};
	345
	346	mshc_1: mshc@12520000 {
	347	compatible = "samsung,exynos5250-dw-mshc";
	348	reg = <0x12520000 0x1000>;
	349	interrupts = <0 143 0>;
	350	clocks = <&cmu CLK_SDMMC1>, <&cmu CLK_SCLK_MMC1>;
	351	clock-names = "biu", "ciu";
	352	fifo-depth = <0x80>;
	353	#address-cells = <1>;
	354	#size-cells = <0>;
	355	status = "disabled";
	356	};
	357
11ab02b8 JK	358	exynos_usbphy: exynos-usbphy@125B0000 {
	359	compatible = "samsung,exynos3250-usb2-phy";
	360	reg = <0x125B0000 0x100>;
	361	samsung,pmureg-phandle = <&pmu_system_controller>;
	362	clocks = <&cmu CLK_USBOTG>, <&cmu CLK_SCLK_UPLL>;
	363	clock-names = "phy", "ref";
	364	#phy-cells = <1>;
	365	status = "disabled";
	366	};
	367
5a992a9c TF	368	amba {
	369	compatible = "arm,amba-bus";
	370	#address-cells = <1>;
	371	#size-cells = <1>;
5a992a9c TF	372	ranges;
	373
	374	pdma0: pdma@12680000 {
	375	compatible = "arm,pl330", "arm,primecell";
	376	reg = <0x12680000 0x1000>;
	377	interrupts = <0 138 0>;
	378	clocks = <&cmu CLK_PDMA0>;
	379	clock-names = "apb_pclk";
	380	#dma-cells = <1>;
	381	#dma-channels = <8>;
	382	#dma-requests = <32>;
	383	};
	384
	385	pdma1: pdma@12690000 {
	386	compatible = "arm,pl330", "arm,primecell";
	387	reg = <0x12690000 0x1000>;
	388	interrupts = <0 139 0>;
	389	clocks = <&cmu CLK_PDMA1>;
	390	clock-names = "apb_pclk";
	391	#dma-cells = <1>;
	392	#dma-channels = <8>;
	393	#dma-requests = <32>;
	394	};
	395	};
	396
	397	adc: adc@126C0000 {
e6ca2d84 CC	398	compatible = "samsung,exynos3250-adc",
e6ca2d84 CC	399	"samsung,exynos-adc-v2";
db9bf4d6	400	reg = <0x126C0000 0x100>;
5a992a9c	401	interrupts = <0 137 0>;
e6ca2d84	402	clock-names = "adc", "sclk";
5a992a9c TF	403	clocks = <&cmu CLK_TSADC>, <&cmu CLK_SCLK_TSADC>;
	404	#io-channel-cells = <1>;
	405	io-channel-ranges;
db9bf4d6	406	samsung,syscon-phandle = <&pmu_system_controller>;
5a992a9c TF	407	status = "disabled";
	408	};
	409
752d3a23 JA	410	mfc: codec@13400000 {
	411	compatible = "samsung,mfc-v7";
	412	reg = <0x13400000 0x10000>;
	413	interrupts = <0 102 0>;
	414	clock-names = "mfc", "sclk_mfc";
	415	clocks = <&cmu CLK_MFC>, <&cmu CLK_SCLK_MFC>;
0da65870	416	power-domains = <&pd_mfc>;
f5976ce5	417	iommus = <&sysmmu_mfc>;
752d3a23 JA	418	status = "disabled";
	419	};
	420
f5976ce5 MS	421	sysmmu_mfc: sysmmu@13620000 {
	422	compatible = "samsung,exynos-sysmmu";
	423	reg = <0x13620000 0x1000>;
	424	interrupts = <0 96 0>, <0 98 0>;
	425	clock-names = "sysmmu", "master";
	426	clocks = <&cmu CLK_SMMUMFC_L>, <&cmu CLK_MFC>;
	427	power-domains = <&pd_mfc>;
	428	#iommu-cells = <0>;
	429	};
	430
5a992a9c TF	431	serial_0: serial@13800000 {
	432	compatible = "samsung,exynos4210-uart";
	433	reg = <0x13800000 0x100>;
	434	interrupts = <0 109 0>;
	435	clocks = <&cmu CLK_UART0>, <&cmu CLK_SCLK_UART0>;
	436	clock-names = "uart", "clk_uart_baud0";
a9408a6b CC	437	pinctrl-names = "default";
a9408a6b CC	438	pinctrl-0 = <&uart0_data &uart0_fctl>;
5a992a9c TF	439	status = "disabled";
	440	};
	441
	442	serial_1: serial@13810000 {
	443	compatible = "samsung,exynos4210-uart";
	444	reg = <0x13810000 0x100>;
	445	interrupts = <0 110 0>;
	446	clocks = <&cmu CLK_UART1>, <&cmu CLK_SCLK_UART1>;
	447	clock-names = "uart", "clk_uart_baud0";
a9408a6b CC	448	pinctrl-names = "default";
a9408a6b CC	449	pinctrl-0 = <&uart1_data>;
5a992a9c TF	450	status = "disabled";
	451	};
	452
	453	i2c_0: i2c@13860000 {
	454	#address-cells = <1>;
	455	#size-cells = <0>;
	456	compatible = "samsung,s3c2440-i2c";
	457	reg = <0x13860000 0x100>;
	458	interrupts = <0 113 0>;
	459	clocks = <&cmu CLK_I2C0>;
	460	clock-names = "i2c";
	461	pinctrl-names = "default";
	462	pinctrl-0 = <&i2c0_bus>;
	463	status = "disabled";
	464	};
	465
	466	i2c_1: i2c@13870000 {
	467	#address-cells = <1>;
	468	#size-cells = <0>;
	469	compatible = "samsung,s3c2440-i2c";
	470	reg = <0x13870000 0x100>;
	471	interrupts = <0 114 0>;
	472	clocks = <&cmu CLK_I2C1>;
	473	clock-names = "i2c";
	474	pinctrl-names = "default";
	475	pinctrl-0 = <&i2c1_bus>;
	476	status = "disabled";
	477	};
	478
	479	i2c_2: i2c@13880000 {
	480	#address-cells = <1>;
	481	#size-cells = <0>;
	482	compatible = "samsung,s3c2440-i2c";
	483	reg = <0x13880000 0x100>;
	484	interrupts = <0 115 0>;
	485	clocks = <&cmu CLK_I2C2>;
	486	clock-names = "i2c";
	487	pinctrl-names = "default";
	488	pinctrl-0 = <&i2c2_bus>;
	489	status = "disabled";
	490	};
	491
	492	i2c_3: i2c@13890000 {
	493	#address-cells = <1>;
	494	#size-cells = <0>;
	495	compatible = "samsung,s3c2440-i2c";
	496	reg = <0x13890000 0x100>;
	497	interrupts = <0 116 0>;
	498	clocks = <&cmu CLK_I2C3>;
	499	clock-names = "i2c";
	500	pinctrl-names = "default";
	501	pinctrl-0 = <&i2c3_bus>;
	502	status = "disabled";
	503	};
	504
	505	i2c_4: i2c@138A0000 {
	506	#address-cells = <1>;
	507	#size-cells = <0>;
	508	compatible = "samsung,s3c2440-i2c";
	509	reg = <0x138A0000 0x100>;
	510	interrupts = <0 117 0>;
	511	clocks = <&cmu CLK_I2C4>;
	512	clock-names = "i2c";
	513	pinctrl-names = "default";
514	pinctrl-0 = <&i2c4_bus>;
515	status = "disabled";
516	};
517
518	i2c_5: i2c@138B0000 {
519	#address-cells = <1>;
520	#size-cells = <0>;
521	compatible = "samsung,s3c2440-i2c";
522	reg = <0x138B0000 0x100>;
523	interrupts = <0 118 0>;
524	clocks = <&cmu CLK_I2C5>;
525	clock-names = "i2c";
526	pinctrl-names = "default";
527	pinctrl-0 = <&i2c5_bus>;
528	status = "disabled";
529	};
530
531	i2c_6: i2c@138C0000 {
532	#address-cells = <1>;
533	#size-cells = <0>;
534	compatible = "samsung,s3c2440-i2c";
535	reg = <0x138C0000 0x100>;
536	interrupts = <0 119 0>;
537	clocks = <&cmu CLK_I2C6>;
538	clock-names = "i2c";
539	pinctrl-names = "default";
540	pinctrl-0 = <&i2c6_bus>;
541	status = "disabled";
542	};
543
544	i2c_7: i2c@138D0000 {
545	#address-cells = <1>;
546	#size-cells = <0>;
547	compatible = "samsung,s3c2440-i2c";
548	reg = <0x138D0000 0x100>;
549	interrupts = <0 120 0>;
550	clocks = <&cmu CLK_I2C7>;
551	clock-names = "i2c";
552	pinctrl-names = "default";
553	pinctrl-0 = <&i2c7_bus>;
554	status = "disabled";
555	};
556
557	spi_0: spi@13920000 {
558	compatible = "samsung,exynos4210-spi";
559	reg = <0x13920000 0x100>;
560	interrupts = <0 121 0>;
561	dmas = <&pdma0 7>, <&pdma0 6>;
562	dma-names = "tx", "rx";
563	#address-cells = <1>;
564	#size-cells = <0>;
565	clocks = <&cmu CLK_SPI0>, <&cmu CLK_SCLK_SPI0>;
566	clock-names = "spi", "spi_busclk0";
567	samsung,spi-src-clk = <0>;
568	pinctrl-names = "default";
569	pinctrl-0 = <&spi0_bus>;
570	status = "disabled";
571	};
572
573	spi_1: spi@13930000 {
574	compatible = "samsung,exynos4210-spi";
575	reg = <0x13930000 0x100>;
576	interrupts = <0 122 0>;
577	dmas = <&pdma1 7>, <&pdma1 6>;
578	dma-names = "tx", "rx";
579	#address-cells = <1>;
580	#size-cells = <0>;
581	clocks = <&cmu CLK_SPI1>, <&cmu CLK_SCLK_SPI1>;
582	clock-names = "spi", "spi_busclk0";
583	samsung,spi-src-clk = <0>;
584	pinctrl-names = "default";
585	pinctrl-0 = <&spi1_bus>;
586	status = "disabled";
587	};
588
ccaba452 TF	589	i2s2: i2s@13970000 {
	590	compatible = "samsung,s3c6410-i2s";
	591	reg = <0x13970000 0x100>;
	592	interrupts = <0 126 0>;
	593	clocks = <&cmu CLK_I2S>, <&cmu CLK_SCLK_I2S>;
	594	clock-names = "iis", "i2s_opclk0";
	595	dmas = <&pdma0 14>, <&pdma0 13>;
	596	dma-names = "tx", "rx";
	597	pinctrl-0 = <&i2s2_bus>;
	598	pinctrl-names = "default";
	599	status = "disabled";
	600	};
	601
5a992a9c TF	602	pwm: pwm@139D0000 {
	603	compatible = "samsung,exynos4210-pwm";
	604	reg = <0x139D0000 0x1000>;
	605	interrupts = <0 104 0>, <0 105 0>, <0 106 0>,
	606	<0 107 0>, <0 108 0>;
	607	#pwm-cells = <3>;
	608	status = "disabled";
	609	};
	610
	611	pmu {
	612	compatible = "arm,cortex-a7-pmu";
	613	interrupts = <0 18 0>, <0 19 0>;
	614	};
e4502367 CC	615
	616	ppmu_dmc0: ppmu_dmc0@106a0000 {
	617	compatible = "samsung,exynos-ppmu";
	618	reg = <0x106a0000 0x2000>;
	619	status = "disabled";
	620	};
	621
	622	ppmu_dmc1: ppmu_dmc1@106b0000 {
	623	compatible = "samsung,exynos-ppmu";
	624	reg = <0x106b0000 0x2000>;
	625	status = "disabled";
	626	};
	627
	628	ppmu_cpu: ppmu_cpu@106c0000 {
	629	compatible = "samsung,exynos-ppmu";
	630	reg = <0x106c0000 0x2000>;
	631	status = "disabled";
	632	};
	633
	634	ppmu_rightbus: ppmu_rightbus@112a0000 {
	635	compatible = "samsung,exynos-ppmu";
	636	reg = <0x112a0000 0x2000>;
	637	clocks = <&cmu CLK_PPMURIGHT>;
	638	clock-names = "ppmu";
	639	status = "disabled";
	640	};
	641
	642	ppmu_leftbus: ppmu_leftbus0@116a0000 {
	643	compatible = "samsung,exynos-ppmu";
	644	reg = <0x116a0000 0x2000>;
	645	clocks = <&cmu CLK_PPMULEFT>;
	646	clock-names = "ppmu";
	647	status = "disabled";
	648	};
	649
	650	ppmu_camif: ppmu_camif@11ac0000 {
	651	compatible = "samsung,exynos-ppmu";
	652	reg = <0x11ac0000 0x2000>;
	653	clocks = <&cmu CLK_PPMUCAMIF>;
	654	clock-names = "ppmu";
	655	status = "disabled";
	656	};
	657
	658	ppmu_lcd0: ppmu_lcd0@11e40000 {
	659	compatible = "samsung,exynos-ppmu";
	660	reg = <0x11e40000 0x2000>;
	661	clocks = <&cmu CLK_PPMULCD0>;
	662	clock-names = "ppmu";
	663	status = "disabled";
	664	};
	665
	666	ppmu_fsys: ppmu_fsys@12630000 {
	667	compatible = "samsung,exynos-ppmu";
	668	reg = <0x12630000 0x2000>;
	669	clocks = <&cmu CLK_PPMUFILE>;
	670	clock-names = "ppmu";
	671	status = "disabled";
	672	};
	673
	674	ppmu_g3d: ppmu_g3d@13220000 {
	675	compatible = "samsung,exynos-ppmu";
	676	reg = <0x13220000 0x2000>;
	677	clocks = <&cmu CLK_PPMUG3D>;
	678	clock-names = "ppmu";
679	status = "disabled";
680	};
681
682	ppmu_mfc: ppmu_mfc@13660000 {
683	compatible = "samsung,exynos-ppmu";
684	reg = <0x13660000 0x2000>;
685	clocks = <&cmu CLK_PPMUMFC_L>;
686	clock-names = "ppmu";
687	status = "disabled";
688	};
5a992a9c TF	689	};
	690	};
	691
	692	#include "exynos3250-pinctrl.dtsi"