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Merge remote-tracking branch 'mfd/for-mfd-next'
[deliverable/linux.git] / arch / arm / boot / dts / exynos3250.dtsi
CommitLineData
5a992a9c
TF		 1/*
2 * Samsung's Exynos3250 SoC device tree source
3 *
4 * Copyright (c) 2014 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 *
7 * Samsung's Exynos3250 SoC device nodes are listed in this file. Exynos3250
8 * based board files can include this file and provide values for board specfic
9 * bindings.
10 *
11 * Note: This file does not include device nodes for all the controllers in
12 * Exynos3250 SoC. As device tree coverage for Exynos3250 increases, additional
13 * nodes can be added to this file.
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
18 */
19
9843a223 20#include "exynos4-cpu-thermal.dtsi"
1462b137 21#include "exynos-syscon-restart.dtsi"
5a992a9c
TF		 22#include <dt-bindings/clock/exynos3250.h>
23
24/ {
25 compatible = "samsung,exynos3250";
26 interrupt-parent = <&gic>;
33c3de7e
JMC		 27 #address-cells = <1>;
28 #size-cells = <1>;
5a992a9c
TF		 29
30 aliases {
31 pinctrl0 = &pinctrl_0;
32 pinctrl1 = &pinctrl_1;
33 mshc0 = &mshc_0;
34 mshc1 = &mshc_1;
92173e6a 35 mshc2 = &mshc_2;
5a992a9c
TF		 36 spi0 = &spi_0;
37 spi1 = &spi_1;
38 i2c0 = &i2c_0;
39 i2c1 = &i2c_1;
40 i2c2 = &i2c_2;
41 i2c3 = &i2c_3;
42 i2c4 = &i2c_4;
43 i2c5 = &i2c_5;
44 i2c6 = &i2c_6;
45 i2c7 = &i2c_7;
1e64f48e
TF		 46 serial0 = &serial_0;
47 serial1 = &serial_1;
ecaba514 48 serial2 = &serial_2;
5a992a9c
TF		 49 };
50
51 cpus {
52 #address-cells = <1>;
53 #size-cells = <0>;
54
55 cpu0: cpu@0 {
56 device_type = "cpu";
57 compatible = "arm,cortex-a7";
58 reg = <0>;
59 clock-frequency = <1000000000>;
48816aff
CC		 60 clocks = <&cmu CLK_ARM_CLK>;
61 clock-names = "cpu";
5600f8cc 62 #cooling-cells = <2>;
48816aff
CC		 63
64 operating-points = <
65 1000000 1150000
66 900000 1112500
67 800000 1075000
68 700000 1037500
69 600000 1000000
70 500000 962500
71 400000 925000
72 300000 887500
73 200000 850000
74 100000 850000
75 >;
5a992a9c
TF		 76 };
77
78 cpu1: cpu@1 {
79 device_type = "cpu";
80 compatible = "arm,cortex-a7";
81 reg = <1>;
82 clock-frequency = <1000000000>;
83 };
84 };
85
86 soc: soc {
87 compatible = "simple-bus";
88 #address-cells = <1>;
89 #size-cells = <1>;
90 ranges;
91
92 fixed-rate-clocks {
93 #address-cells = <1>;
94 #size-cells = <0>;
95
96 xusbxti: clock@0 {
97 compatible = "fixed-clock";
98 #address-cells = <1>;
99 #size-cells = <0>;
100 reg = <0>;
101 clock-frequency = <0>;
102 #clock-cells = <0>;
103 clock-output-names = "xusbxti";
104 };
105
106 xxti: clock@1 {
107 compatible = "fixed-clock";
108 reg = <1>;
109 clock-frequency = <0>;
110 #clock-cells = <0>;
111 clock-output-names = "xxti";
112 };
113
114 xtcxo: clock@2 {
115 compatible = "fixed-clock";
116 reg = <2>;
117 clock-frequency = <0>;
118 #clock-cells = <0>;
119 clock-output-names = "xtcxo";
120 };
121 };
122
123 sysram@02020000 {
124 compatible = "mmio-sram";
125 reg = <0x02020000 0x40000>;
126 #address-cells = <1>;
127 #size-cells = <1>;
128 ranges = <0 0x02020000 0x40000>;
129
130 smp-sysram@0 {
131 compatible = "samsung,exynos4210-sysram";
132 reg = <0x0 0x1000>;
133 };
134
135 smp-sysram@3f000 {
136 compatible = "samsung,exynos4210-sysram-ns";
137 reg = <0x3f000 0x1000>;
138 };
139 };
140
141 chipid@10000000 {
142 compatible = "samsung,exynos4210-chipid";
143 reg = <0x10000000 0x100>;
144 };
145
146 sys_reg: syscon@10010000 {
147 compatible = "samsung,exynos3-sysreg", "syscon";
148 reg = <0x10010000 0x400>;
149 };
150
25023926
CC		 151 pmu_system_controller: system-controller@10020000 {
152 compatible = "samsung,exynos3250-pmu", "syscon";
153 reg = <0x10020000 0x4000>;
8b283c02
MZ		 154 interrupt-controller;
155 #interrupt-cells = <3>;
156 interrupt-parent = <&gic>;
25023926
CC		 157 };
158
bb72cade 159 mipi_phy: video-phy {
9fab9d6a 160 compatible = "samsung,s5pv210-mipi-video-phy";
9fab9d6a 161 #phy-cells = <1>;
1342ff45 162 syscon = <&pmu_system_controller>;
9fab9d6a
ID		 163 };
164
5a992a9c
TF		 165 pd_cam: cam-power-domain@10023C00 {
166 compatible = "samsung,exynos4210-pd";
167 reg = <0x10023C00 0x20>;
0da65870 168 #power-domain-cells = <0>;
5a992a9c
TF		 169 };
170
171 pd_mfc: mfc-power-domain@10023C40 {
172 compatible = "samsung,exynos4210-pd";
173 reg = <0x10023C40 0x20>;
0da65870 174 #power-domain-cells = <0>;
5a992a9c
TF		 175 };
176
177 pd_g3d: g3d-power-domain@10023C60 {
178 compatible = "samsung,exynos4210-pd";
179 reg = <0x10023C60 0x20>;
0da65870 180 #power-domain-cells = <0>;
5a992a9c
TF		 181 };
182
183 pd_lcd0: lcd0-power-domain@10023C80 {
184 compatible = "samsung,exynos4210-pd";
185 reg = <0x10023C80 0x20>;
0da65870 186 #power-domain-cells = <0>;
5a992a9c
TF		 187 };
188
189 pd_isp: isp-power-domain@10023CA0 {
190 compatible = "samsung,exynos4210-pd";
191 reg = <0x10023CA0 0x20>;
0da65870 192 #power-domain-cells = <0>;
5a992a9c
TF		 193 };
194
195 cmu: clock-controller@10030000 {
196 compatible = "samsung,exynos3250-cmu";
197 reg = <0x10030000 0x20000>;
198 #clock-cells = <1>;
52005dec
BM		 199 assigned-clocks = <&cmu CLK_MOUT_ACLK_400_MCUISP_SUB>,
200 <&cmu CLK_MOUT_ACLK_266_SUB>;
201 assigned-clock-parents = <&cmu CLK_FIN_PLL>,
202 <&cmu CLK_FIN_PLL>;
5a992a9c
TF		 203 };
204
d0e73eaf
KK		 205 cmu_dmc: clock-controller@105C0000 {
206 compatible = "samsung,exynos3250-cmu-dmc";
207 reg = <0x105C0000 0x2000>;
208 #clock-cells = <1>;
209 };
210
5a992a9c 211 rtc: rtc@10070000 {
062f49c4 212 compatible = "samsung,s3c6410-rtc";
5a992a9c
TF		 213 reg = <0x10070000 0x100>;
214 interrupts = <0 73 0>, <0 74 0>;
8b283c02 215 interrupt-parent = <&pmu_system_controller>;
5a992a9c
TF		 216 status = "disabled";
217 };
218
9dfb3347
CC		 219 tmu: tmu@100C0000 {
220 compatible = "samsung,exynos3250-tmu";
221 reg = <0x100C0000 0x100>;
222 interrupts = <0 216 0>;
223 clocks = <&cmu CLK_TMU_APBIF>;
224 clock-names = "tmu_apbif";
9843a223 225 #include "exynos4412-tmu-sensor-conf.dtsi"
9dfb3347
CC		 226 status = "disabled";
227 };
228
5a992a9c
TF		 229 gic: interrupt-controller@10481000 {
230 compatible = "arm,cortex-a15-gic";
231 #interrupt-cells = <3>;
232 interrupt-controller;
233 reg = <0x10481000 0x1000>,
234 <0x10482000 0x1000>,
235 <0x10484000 0x2000>,
236 <0x10486000 0x2000>;
237 interrupts = <1 9 0xf04>;
238 };
239
240 mct@10050000 {
241 compatible = "samsung,exynos4210-mct";
242 reg = <0x10050000 0x800>;
243 interrupts = <0 218 0>, <0 219 0>, <0 220 0>, <0 221 0>,
244 <0 223 0>, <0 226 0>, <0 227 0>, <0 228 0>;
245 clocks = <&cmu CLK_FIN_PLL>, <&cmu CLK_MCT>;
246 clock-names = "fin_pll", "mct";
247 };
248
249 pinctrl_1: pinctrl@11000000 {
250 compatible = "samsung,exynos3250-pinctrl";
251 reg = <0x11000000 0x1000>;
252 interrupts = <0 225 0>;
253
254 wakeup-interrupt-controller {
255 compatible = "samsung,exynos4210-wakeup-eint";
5a992a9c
TF		 256 interrupts = <0 48 0>;
257 };
258 };
259
260 pinctrl_0: pinctrl@11400000 {
261 compatible = "samsung,exynos3250-pinctrl";
262 reg = <0x11400000 0x1000>;
263 interrupts = <0 240 0>;
264 };
265
c9c1adfe
JA		 266 jpeg: codec@11830000 {
267 compatible = "samsung,exynos3250-jpeg";
268 reg = <0x11830000 0x1000>;
269 interrupts = <0 171 0>;
270 clocks = <&cmu CLK_JPEG>, <&cmu CLK_SCLK_JPEG>;
271 clock-names = "jpeg", "sclk";
272 power-domains = <&pd_cam>;
273 assigned-clocks = <&cmu CLK_MOUT_CAM_BLK>, <&cmu CLK_SCLK_JPEG>;
274 assigned-clock-rates = <0>, <150000000>;
275 assigned-clock-parents = <&cmu CLK_DIV_MPLL_PRE>;
f5976ce5 276 iommus = <&sysmmu_jpeg>;
c9c1adfe
JA		 277 status = "disabled";
278 };
279
f5976ce5
MS		 280 sysmmu_jpeg: sysmmu@11A60000 {
281 compatible = "samsung,exynos-sysmmu";
282 reg = <0x11a60000 0x1000>;
283 interrupts = <0 156 0>, <0 161 0>;
284 clock-names = "sysmmu", "master";
285 clocks = <&cmu CLK_SMMUJPEG>, <&cmu CLK_JPEG>;
286 power-domains = <&pd_cam>;
287 #iommu-cells = <0>;
288 };
289
03b86c79
ID		 290 fimd: fimd@11c00000 {
291 compatible = "samsung,exynos3250-fimd";
292 reg = <0x11c00000 0x30000>;
293 interrupt-names = "fifo", "vsync", "lcd_sys";
294 interrupts = <0 84 0>, <0 85 0>, <0 86 0>;
295 clocks = <&cmu CLK_SCLK_FIMD0>, <&cmu CLK_FIMD0>;
296 clock-names = "sclk_fimd", "fimd";
0da65870 297 power-domains = <&pd_lcd0>;
f5976ce5 298 iommus = <&sysmmu_fimd0>;
03b86c79
ID		 299 samsung,sysreg = <&sys_reg>;
300 status = "disabled";
301 };
302
025d8e13
ID		 303 dsi_0: dsi@11C80000 {
304 compatible = "samsung,exynos3250-mipi-dsi";
305 reg = <0x11C80000 0x10000>;
306 interrupts = <0 83 0>;
307 samsung,phy-type = <0>;
0da65870 308 power-domains = <&pd_lcd0>;
025d8e13
ID		 309 phys = <&mipi_phy 1>;
310 phy-names = "dsim";
311 clocks = <&cmu CLK_DSIM0>, <&cmu CLK_SCLK_MIPI0>;
312 clock-names = "bus_clk", "pll_clk";
313 #address-cells = <1>;
314 #size-cells = <0>;
315 status = "disabled";
316 };
317
f5976ce5
MS		 318 sysmmu_fimd0: sysmmu@11E20000 {
319 compatible = "samsung,exynos-sysmmu";
320 reg = <0x11e20000 0x1000>;
321 interrupts = <0 80 0>, <0 81 0>;
322 clock-names = "sysmmu", "master";
323 clocks = <&cmu CLK_SMMUFIMD0>, <&cmu CLK_FIMD0>;
324 power-domains = <&pd_lcd0>;
325 #iommu-cells = <0>;
326 };
327
e0c6e929
JK		 328 hsotg: hsotg@12480000 {
329 compatible = "snps,dwc2";
330 reg = <0x12480000 0x20000>;
331 interrupts = <0 141 0>;
332 clocks = <&cmu CLK_USBOTG>;
333 clock-names = "otg";
334 phys = <&exynos_usbphy 0>;
335 phy-names = "usb2-phy";
336 status = "disabled";
337 };
338
5a992a9c 339 mshc_0: mshc@12510000 {
b29dd5fa 340 compatible = "samsung,exynos5420-dw-mshc";
5a992a9c
TF		 341 reg = <0x12510000 0x1000>;
342 interrupts = <0 142 0>;
343 clocks = <&cmu CLK_SDMMC0>, <&cmu CLK_SCLK_MMC0>;
344 clock-names = "biu", "ciu";
345 fifo-depth = <0x80>;
346 #address-cells = <1>;
347 #size-cells = <0>;
348 status = "disabled";
349 };
350
351 mshc_1: mshc@12520000 {
b29dd5fa 352 compatible = "samsung,exynos5420-dw-mshc";
5a992a9c
TF		 353 reg = <0x12520000 0x1000>;
354 interrupts = <0 143 0>;
355 clocks = <&cmu CLK_SDMMC1>, <&cmu CLK_SCLK_MMC1>;
356 clock-names = "biu", "ciu";
357 fifo-depth = <0x80>;
358 #address-cells = <1>;
359 #size-cells = <0>;
360 status = "disabled";
361 };
362
92173e6a
CC		 363 mshc_2: mshc@12530000 {
364 compatible = "samsung,exynos5250-dw-mshc";
365 reg = <0x12530000 0x1000>;
366 interrupts = <0 144 0>;
367 clocks = <&cmu CLK_SDMMC2>, <&cmu CLK_SCLK_MMC2>;
368 clock-names = "biu", "ciu";
369 fifo-depth = <0x80>;
370 #address-cells = <1>;
371 #size-cells = <0>;
372 status = "disabled";
373 };
374
11ab02b8
JK		 375 exynos_usbphy: exynos-usbphy@125B0000 {
376 compatible = "samsung,exynos3250-usb2-phy";
377 reg = <0x125B0000 0x100>;
378 samsung,pmureg-phandle = <&pmu_system_controller>;
379 clocks = <&cmu CLK_USBOTG>, <&cmu CLK_SCLK_UPLL>;
380 clock-names = "phy", "ref";
381 #phy-cells = <1>;
382 status = "disabled";
383 };
384
5a992a9c 385 amba {
2ef7d5f3 386 compatible = "simple-bus";
5a992a9c
TF		 387 #address-cells = <1>;
388 #size-cells = <1>;
5a992a9c
TF		 389 ranges;
390
391 pdma0: pdma@12680000 {
392 compatible = "arm,pl330", "arm,primecell";
393 reg = <0x12680000 0x1000>;
394 interrupts = <0 138 0>;
395 clocks = <&cmu CLK_PDMA0>;
396 clock-names = "apb_pclk";
397 #dma-cells = <1>;
398 #dma-channels = <8>;
399 #dma-requests = <32>;
400 };
401
402 pdma1: pdma@12690000 {
403 compatible = "arm,pl330", "arm,primecell";
404 reg = <0x12690000 0x1000>;
405 interrupts = <0 139 0>;
406 clocks = <&cmu CLK_PDMA1>;
407 clock-names = "apb_pclk";
408 #dma-cells = <1>;
409 #dma-channels = <8>;
410 #dma-requests = <32>;
411 };
412 };
413
414 adc: adc@126C0000 {
e6ca2d84
CC		 415 compatible = "samsung,exynos3250-adc",
416 "samsung,exynos-adc-v2";
db9bf4d6 417 reg = <0x126C0000 0x100>;
5a992a9c 418 interrupts = <0 137 0>;
e6ca2d84 419 clock-names = "adc", "sclk";
5a992a9c
TF		 420 clocks = <&cmu CLK_TSADC>, <&cmu CLK_SCLK_TSADC>;
421 #io-channel-cells = <1>;
422 io-channel-ranges;
db9bf4d6 423 samsung,syscon-phandle = <&pmu_system_controller>;
5a992a9c
TF		 424 status = "disabled";
425 };
426
752d3a23
JA		 427 mfc: codec@13400000 {
428 compatible = "samsung,mfc-v7";
429 reg = <0x13400000 0x10000>;
430 interrupts = <0 102 0>;
431 clock-names = "mfc", "sclk_mfc";
432 clocks = <&cmu CLK_MFC>, <&cmu CLK_SCLK_MFC>;
0da65870 433 power-domains = <&pd_mfc>;
f5976ce5 434 iommus = <&sysmmu_mfc>;
752d3a23
JA		 435 };
436
f5976ce5
MS		 437 sysmmu_mfc: sysmmu@13620000 {
438 compatible = "samsung,exynos-sysmmu";
439 reg = <0x13620000 0x1000>;
440 interrupts = <0 96 0>, <0 98 0>;
441 clock-names = "sysmmu", "master";
442 clocks = <&cmu CLK_SMMUMFC_L>, <&cmu CLK_MFC>;
443 power-domains = <&pd_mfc>;
444 #iommu-cells = <0>;
445 };
446
5a992a9c
TF		 447 serial_0: serial@13800000 {
448 compatible = "samsung,exynos4210-uart";
449 reg = <0x13800000 0x100>;
450 interrupts = <0 109 0>;
451 clocks = <&cmu CLK_UART0>, <&cmu CLK_SCLK_UART0>;
452 clock-names = "uart", "clk_uart_baud0";
a9408a6b
CC		 453 pinctrl-names = "default";
454 pinctrl-0 = <&uart0_data &uart0_fctl>;
5a992a9c
TF		 455 status = "disabled";
456 };
457
458 serial_1: serial@13810000 {
459 compatible = "samsung,exynos4210-uart";
460 reg = <0x13810000 0x100>;
461 interrupts = <0 110 0>;
462 clocks = <&cmu CLK_UART1>, <&cmu CLK_SCLK_UART1>;
463 clock-names = "uart", "clk_uart_baud0";
a9408a6b
CC		 464 pinctrl-names = "default";
465 pinctrl-0 = <&uart1_data>;
5a992a9c
TF		 466 status = "disabled";
467 };
468
ecaba514
PD		 469 serial_2: serial@13820000 {
470 compatible = "samsung,exynos4210-uart";
471 reg = <0x13820000 0x100>;
472 interrupts = <0 111 0>;
473 clocks = <&cmu CLK_UART2>, <&cmu CLK_SCLK_UART2>;
474 clock-names = "uart", "clk_uart_baud0";
475 pinctrl-names = "default";
476 pinctrl-0 = <&uart2_data>;
477 status = "disabled";
478 };
479
5a992a9c
TF		 480 i2c_0: i2c@13860000 {
481 #address-cells = <1>;
482 #size-cells = <0>;
483 compatible = "samsung,s3c2440-i2c";
484 reg = <0x13860000 0x100>;
485 interrupts = <0 113 0>;
486 clocks = <&cmu CLK_I2C0>;
487 clock-names = "i2c";
488 pinctrl-names = "default";
489 pinctrl-0 = <&i2c0_bus>;
490 status = "disabled";
491 };
492
493 i2c_1: i2c@13870000 {
494 #address-cells = <1>;
495 #size-cells = <0>;
496 compatible = "samsung,s3c2440-i2c";
497 reg = <0x13870000 0x100>;
498 interrupts = <0 114 0>;
499 clocks = <&cmu CLK_I2C1>;
500 clock-names = "i2c";
501 pinctrl-names = "default";
502 pinctrl-0 = <&i2c1_bus>;
503 status = "disabled";
504 };
505
506 i2c_2: i2c@13880000 {
507 #address-cells = <1>;
508 #size-cells = <0>;
509 compatible = "samsung,s3c2440-i2c";
510 reg = <0x13880000 0x100>;
511 interrupts = <0 115 0>;
512 clocks = <&cmu CLK_I2C2>;
513 clock-names = "i2c";
514 pinctrl-names = "default";
515 pinctrl-0 = <&i2c2_bus>;
516 status = "disabled";
517 };
518
519 i2c_3: i2c@13890000 {
520 #address-cells = <1>;
521 #size-cells = <0>;
522 compatible = "samsung,s3c2440-i2c";
523 reg = <0x13890000 0x100>;
524 interrupts = <0 116 0>;
525 clocks = <&cmu CLK_I2C3>;
526 clock-names = "i2c";
527 pinctrl-names = "default";
528 pinctrl-0 = <&i2c3_bus>;
529 status = "disabled";
530 };
531
532 i2c_4: i2c@138A0000 {
533 #address-cells = <1>;
534 #size-cells = <0>;
535 compatible = "samsung,s3c2440-i2c";
536 reg = <0x138A0000 0x100>;
537 interrupts = <0 117 0>;
538 clocks = <&cmu CLK_I2C4>;
539 clock-names = "i2c";
540 pinctrl-names = "default";
541 pinctrl-0 = <&i2c4_bus>;
542 status = "disabled";
543 };
544
545 i2c_5: i2c@138B0000 {
546 #address-cells = <1>;
547 #size-cells = <0>;
548 compatible = "samsung,s3c2440-i2c";
549 reg = <0x138B0000 0x100>;
550 interrupts = <0 118 0>;
551 clocks = <&cmu CLK_I2C5>;
552 clock-names = "i2c";
553 pinctrl-names = "default";
554 pinctrl-0 = <&i2c5_bus>;
555 status = "disabled";
556 };
557
558 i2c_6: i2c@138C0000 {
559 #address-cells = <1>;
560 #size-cells = <0>;
561 compatible = "samsung,s3c2440-i2c";
562 reg = <0x138C0000 0x100>;
563 interrupts = <0 119 0>;
564 clocks = <&cmu CLK_I2C6>;
565 clock-names = "i2c";
566 pinctrl-names = "default";
567 pinctrl-0 = <&i2c6_bus>;
568 status = "disabled";
569 };
570
571 i2c_7: i2c@138D0000 {
572 #address-cells = <1>;
573 #size-cells = <0>;
574 compatible = "samsung,s3c2440-i2c";
575 reg = <0x138D0000 0x100>;
576 interrupts = <0 120 0>;
577 clocks = <&cmu CLK_I2C7>;
578 clock-names = "i2c";
579 pinctrl-names = "default";
580 pinctrl-0 = <&i2c7_bus>;
581 status = "disabled";
582 };
583
584 spi_0: spi@13920000 {
585 compatible = "samsung,exynos4210-spi";
586 reg = <0x13920000 0x100>;
587 interrupts = <0 121 0>;
588 dmas = <&pdma0 7>, <&pdma0 6>;
589 dma-names = "tx", "rx";
590 #address-cells = <1>;
591 #size-cells = <0>;
592 clocks = <&cmu CLK_SPI0>, <&cmu CLK_SCLK_SPI0>;
593 clock-names = "spi", "spi_busclk0";
594 samsung,spi-src-clk = <0>;
595 pinctrl-names = "default";
596 pinctrl-0 = <&spi0_bus>;
597 status = "disabled";
598 };
599
600 spi_1: spi@13930000 {
601 compatible = "samsung,exynos4210-spi";
602 reg = <0x13930000 0x100>;
603 interrupts = <0 122 0>;
604 dmas = <&pdma1 7>, <&pdma1 6>;
605 dma-names = "tx", "rx";
606 #address-cells = <1>;
607 #size-cells = <0>;
608 clocks = <&cmu CLK_SPI1>, <&cmu CLK_SCLK_SPI1>;
609 clock-names = "spi", "spi_busclk0";
610 samsung,spi-src-clk = <0>;
611 pinctrl-names = "default";
612 pinctrl-0 = <&spi1_bus>;
613 status = "disabled";
614 };
615
ccaba452
TF		 616 i2s2: i2s@13970000 {
617 compatible = "samsung,s3c6410-i2s";
618 reg = <0x13970000 0x100>;
619 interrupts = <0 126 0>;
620 clocks = <&cmu CLK_I2S>, <&cmu CLK_SCLK_I2S>;
621 clock-names = "iis", "i2s_opclk0";
622 dmas = <&pdma0 14>, <&pdma0 13>;
623 dma-names = "tx", "rx";
624 pinctrl-0 = <&i2s2_bus>;
625 pinctrl-names = "default";
626 status = "disabled";
627 };
628
5a992a9c
TF		 629 pwm: pwm@139D0000 {
630 compatible = "samsung,exynos4210-pwm";
631 reg = <0x139D0000 0x1000>;
632 interrupts = <0 104 0>, <0 105 0>, <0 106 0>,
633 <0 107 0>, <0 108 0>;
634 #pwm-cells = <3>;
635 status = "disabled";
636 };
637
638 pmu {
639 compatible = "arm,cortex-a7-pmu";
640 interrupts = <0 18 0>, <0 19 0>;
641 };
e4502367
CC		 642
643 ppmu_dmc0: ppmu_dmc0@106a0000 {
644 compatible = "samsung,exynos-ppmu";
645 reg = <0x106a0000 0x2000>;
646 status = "disabled";
647 };
648
649 ppmu_dmc1: ppmu_dmc1@106b0000 {
650 compatible = "samsung,exynos-ppmu";
651 reg = <0x106b0000 0x2000>;
652 status = "disabled";
653 };
654
655 ppmu_cpu: ppmu_cpu@106c0000 {
656 compatible = "samsung,exynos-ppmu";
657 reg = <0x106c0000 0x2000>;
658 status = "disabled";
659 };
660
661 ppmu_rightbus: ppmu_rightbus@112a0000 {
662 compatible = "samsung,exynos-ppmu";
663 reg = <0x112a0000 0x2000>;
664 clocks = <&cmu CLK_PPMURIGHT>;
665 clock-names = "ppmu";
666 status = "disabled";
667 };
668
669 ppmu_leftbus: ppmu_leftbus0@116a0000 {
670 compatible = "samsung,exynos-ppmu";
671 reg = <0x116a0000 0x2000>;
672 clocks = <&cmu CLK_PPMULEFT>;
673 clock-names = "ppmu";
674 status = "disabled";
675 };
676
677 ppmu_camif: ppmu_camif@11ac0000 {
678 compatible = "samsung,exynos-ppmu";
679 reg = <0x11ac0000 0x2000>;
680 clocks = <&cmu CLK_PPMUCAMIF>;
681 clock-names = "ppmu";
682 status = "disabled";
683 };
684
685 ppmu_lcd0: ppmu_lcd0@11e40000 {
686 compatible = "samsung,exynos-ppmu";
687 reg = <0x11e40000 0x2000>;
688 clocks = <&cmu CLK_PPMULCD0>;
689 clock-names = "ppmu";
690 status = "disabled";
691 };
692
693 ppmu_fsys: ppmu_fsys@12630000 {
694 compatible = "samsung,exynos-ppmu";
695 reg = <0x12630000 0x2000>;
696 clocks = <&cmu CLK_PPMUFILE>;
697 clock-names = "ppmu";
698 status = "disabled";
699 };
700
701 ppmu_g3d: ppmu_g3d@13220000 {
702 compatible = "samsung,exynos-ppmu";
703 reg = <0x13220000 0x2000>;
704 clocks = <&cmu CLK_PPMUG3D>;
705 clock-names = "ppmu";
706 status = "disabled";
707 };
708
709 ppmu_mfc: ppmu_mfc@13660000 {
710 compatible = "samsung,exynos-ppmu";
711 reg = <0x13660000 0x2000>;
712 clocks = <&cmu CLK_PPMUMFC_L>;
713 clock-names = "ppmu";
714 status = "disabled";
715 };
6b088a62
CC		 716
717 bus_dmc: bus_dmc {
718 compatible = "samsung,exynos-bus";
719 clocks = <&cmu_dmc CLK_DIV_DMC>;
720 clock-names = "bus";
721 operating-points-v2 = <&bus_dmc_opp_table>;
722 status = "disabled";
723 };
724
725 bus_dmc_opp_table: opp_table1 {
726 compatible = "operating-points-v2";
727 opp-shared;
728
729 opp@50000000 {
730 opp-hz = /bits/ 64 <50000000>;
731 opp-microvolt = <800000>;
732 };
733 opp@100000000 {
734 opp-hz = /bits/ 64 <100000000>;
735 opp-microvolt = <800000>;
736 };
737 opp@134000000 {
738 opp-hz = /bits/ 64 <134000000>;
739 opp-microvolt = <800000>;
740 };
741 opp@200000000 {
742 opp-hz = /bits/ 64 <200000000>;
743 opp-microvolt = <825000>;
744 };
745 opp@400000000 {
746 opp-hz = /bits/ 64 <400000000>;
747 opp-microvolt = <875000>;
748 };
749 };
304d10ab
CC		 750
751 bus_leftbus: bus_leftbus {
752 compatible = "samsung,exynos-bus";
753 clocks = <&cmu CLK_DIV_GDL>;
754 clock-names = "bus";
755 operating-points-v2 = <&bus_leftbus_opp_table>;
756 status = "disabled";
757 };
758
759 bus_rightbus: bus_rightbus {
760 compatible = "samsung,exynos-bus";
761 clocks = <&cmu CLK_DIV_GDR>;
762 clock-names = "bus";
763 operating-points-v2 = <&bus_leftbus_opp_table>;
764 status = "disabled";
765 };
766
767 bus_lcd0: bus_lcd0 {
768 compatible = "samsung,exynos-bus";
769 clocks = <&cmu CLK_DIV_ACLK_160>;
770 clock-names = "bus";
771 operating-points-v2 = <&bus_leftbus_opp_table>;
772 status = "disabled";
773 };
774
775 bus_fsys: bus_fsys {
776 compatible = "samsung,exynos-bus";
777 clocks = <&cmu CLK_DIV_ACLK_200>;
778 clock-names = "bus";
779 operating-points-v2 = <&bus_leftbus_opp_table>;
780 status = "disabled";
781 };
782
783 bus_mcuisp: bus_mcuisp {
784 compatible = "samsung,exynos-bus";
785 clocks = <&cmu CLK_DIV_ACLK_400_MCUISP>;
786 clock-names = "bus";
787 operating-points-v2 = <&bus_mcuisp_opp_table>;
788 status = "disabled";
789 };
790
791 bus_isp: bus_isp {
792 compatible = "samsung,exynos-bus";
793 clocks = <&cmu CLK_DIV_ACLK_266>;
794 clock-names = "bus";
795 operating-points-v2 = <&bus_isp_opp_table>;
796 status = "disabled";
797 };
798
799 bus_peril: bus_peril {
800 compatible = "samsung,exynos-bus";
801 clocks = <&cmu CLK_DIV_ACLK_100>;
802 clock-names = "bus";
803 operating-points-v2 = <&bus_peril_opp_table>;
804 status = "disabled";
805 };
806
807 bus_mfc: bus_mfc {
808 compatible = "samsung,exynos-bus";
809 clocks = <&cmu CLK_SCLK_MFC>;
810 clock-names = "bus";
811 operating-points-v2 = <&bus_leftbus_opp_table>;
812 status = "disabled";
813 };
814
815 bus_leftbus_opp_table: opp_table2 {
816 compatible = "operating-points-v2";
817 opp-shared;
818
819 opp@50000000 {
820 opp-hz = /bits/ 64 <50000000>;
821 opp-microvolt = <900000>;
822 };
823 opp@80000000 {
824 opp-hz = /bits/ 64 <80000000>;
825 opp-microvolt = <900000>;
826 };
827 opp@100000000 {
828 opp-hz = /bits/ 64 <100000000>;
829 opp-microvolt = <1000000>;
830 };
831 opp@134000000 {
832 opp-hz = /bits/ 64 <134000000>;
833 opp-microvolt = <1000000>;
834 };
835 opp@200000000 {
836 opp-hz = /bits/ 64 <200000000>;
837 opp-microvolt = <1000000>;
838 };
839 };
840
841 bus_mcuisp_opp_table: opp_table3 {
842 compatible = "operating-points-v2";
843 opp-shared;
844
845 opp@50000000 {
846 opp-hz = /bits/ 64 <50000000>;
847 };
848 opp@80000000 {
849 opp-hz = /bits/ 64 <80000000>;
850 };
851 opp@100000000 {
852 opp-hz = /bits/ 64 <100000000>;
853 };
854 opp@200000000 {
855 opp-hz = /bits/ 64 <200000000>;
856 };
857 opp@400000000 {
858 opp-hz = /bits/ 64 <400000000>;
859 };
860 };
861
862 bus_isp_opp_table: opp_table4 {
863 compatible = "operating-points-v2";
864 opp-shared;
865
866 opp@50000000 {
867 opp-hz = /bits/ 64 <50000000>;
868 };
869 opp@80000000 {
870 opp-hz = /bits/ 64 <80000000>;
871 };
872 opp@100000000 {
873 opp-hz = /bits/ 64 <100000000>;
874 };
875 opp@200000000 {
876 opp-hz = /bits/ 64 <200000000>;
877 };
878 opp@300000000 {
879 opp-hz = /bits/ 64 <300000000>;
880 };
881 };
882
883 bus_peril_opp_table: opp_table5 {
884 compatible = "operating-points-v2";
885 opp-shared;
886
887 opp@50000000 {
888 opp-hz = /bits/ 64 <50000000>;
889 };
890 opp@80000000 {
891 opp-hz = /bits/ 64 <80000000>;
892 };
893 opp@100000000 {
894 opp-hz = /bits/ 64 <100000000>;
895 };
896 };
5a992a9c
TF		 897 };
898};
899
900#include "exynos3250-pinctrl.dtsi"
Linux kernel - Deliverables
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