[deliverable/linux.git] / arch / arm / boot / dts / imx6q.dtsi


/*
 * Copyright 2013 Freescale Semiconductor, Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 */

#include <dt-bindings/interrupt-controller/irq.h>
#include "imx6q-pinfunc.h"
#include "imx6qdl.dtsi"

/ {
	aliases {
		ipu1 = &ipu2;
		spi4 = &ecspi5;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			compatible = "arm,cortex-a9";
			device_type = "cpu";
			reg = <0>;
			next-level-cache = <&L2>;
			operating-points = <
				/* kHz    uV */
				1200000 1275000
				996000  1250000
				852000  1250000
				792000  1175000
				396000  975000
			>;
			fsl,soc-operating-points = <
				/* ARM kHz  SOC-PU uV */
				1200000 1275000
				996000	1250000
				852000	1250000
				792000	1175000
				396000	1175000
			>;
			clock-latency = <61036>; /* two CLK32 periods */
			clocks = <&clks IMX6QDL_CLK_ARM>,
				 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
				 <&clks IMX6QDL_CLK_STEP>,
				 <&clks IMX6QDL_CLK_PLL1_SW>,
				 <&clks IMX6QDL_CLK_PLL1_SYS>;
			clock-names = "arm", "pll2_pfd2_396m", "step",
				      "pll1_sw", "pll1_sys";
			arm-supply = <&reg_arm>;
			pu-supply = <&reg_pu>;
			soc-supply = <&reg_soc>;
		};

		cpu@1 {
			compatible = "arm,cortex-a9";
			device_type = "cpu";
			reg = <1>;
			next-level-cache = <&L2>;
		};

		cpu@2 {
			compatible = "arm,cortex-a9";
			device_type = "cpu";
			reg = <2>;
			next-level-cache = <&L2>;
		};

		cpu@3 {
			compatible = "arm,cortex-a9";
			device_type = "cpu";
			reg = <3>;
			next-level-cache = <&L2>;
		};
	};

	soc {
		ocram: sram@00900000 {
			compatible = "mmio-sram";
			reg = <0x00900000 0x40000>;
			clocks = <&clks IMX6QDL_CLK_OCRAM>;
		};

		aips-bus@02000000 { /* AIPS1 */
			spba-bus@02000000 {
				ecspi5: ecspi@02018000 {
					#address-cells = <1>;
					#size-cells = <0>;
					compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
					reg = <0x02018000 0x4000>;
					interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
					clocks = <&clks IMX6Q_CLK_ECSPI5>,
						 <&clks IMX6Q_CLK_ECSPI5>;
					clock-names = "ipg", "per";
					dmas = <&sdma 11 7 1>, <&sdma 12 7 2>;
					dma-names = "rx", "tx";
					status = "disabled";
				};
			};

			iomuxc: iomuxc@020e0000 {
				compatible = "fsl,imx6q-iomuxc";
			};
		};

		sata: sata@02200000 {
			compatible = "fsl,imx6q-ahci";
			reg = <0x02200000 0x4000>;
			interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clks IMX6QDL_CLK_SATA>,
				 <&clks IMX6QDL_CLK_SATA_REF_100M>,
				 <&clks IMX6QDL_CLK_AHB>;
			clock-names = "sata", "sata_ref", "ahb";
			status = "disabled";
		};

		gpu_vg: gpu@02204000 {
			compatible = "vivante,gc";
			reg = <0x02204000 0x4000>;
			interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clks IMX6QDL_CLK_OPENVG_AXI>,
				 <&clks IMX6QDL_CLK_GPU2D_CORE>;
			clock-names = "bus", "core";
			power-domains = <&gpc 1>;
		};

		ipu2: ipu@02800000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "fsl,imx6q-ipu";
			reg = <0x02800000 0x400000>;
			interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>,
				     <0 7 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clks IMX6QDL_CLK_IPU2>,
				 <&clks IMX6QDL_CLK_IPU2_DI0>,
				 <&clks IMX6QDL_CLK_IPU2_DI1>;
			clock-names = "bus", "di0", "di1";
			resets = <&src 4>;

			ipu2_csi0: port@0 {
				reg = <0>;
			};

			ipu2_csi1: port@1 {
				reg = <1>;
			};

			ipu2_di0: port@2 {
				#address-cells = <1>;
				#size-cells = <0>;
				reg = <2>;

				ipu2_di0_disp0: disp0-endpoint {
				};

				ipu2_di0_hdmi: hdmi-endpoint {
					remote-endpoint = <&hdmi_mux_2>;
				};

				ipu2_di0_mipi: mipi-endpoint {
					remote-endpoint = <&mipi_mux_2>;
				};

				ipu2_di0_lvds0: lvds0-endpoint {
					remote-endpoint = <&lvds0_mux_2>;
				};

				ipu2_di0_lvds1: lvds1-endpoint {
					remote-endpoint = <&lvds1_mux_2>;
				};
			};

			ipu2_di1: port@3 {
				#address-cells = <1>;
				#size-cells = <0>;
				reg = <3>;

				ipu2_di1_hdmi: hdmi-endpoint {
					remote-endpoint = <&hdmi_mux_3>;
				};

				ipu2_di1_mipi: mipi-endpoint {
					remote-endpoint = <&mipi_mux_3>;
				};

				ipu2_di1_lvds0: lvds0-endpoint {
					remote-endpoint = <&lvds0_mux_3>;
				};

				ipu2_di1_lvds1: lvds1-endpoint {
					remote-endpoint = <&lvds1_mux_3>;
				};
			};
		};
	};

	display-subsystem {
		compatible = "fsl,imx-display-subsystem";
		ports = <&ipu1_di0>, <&ipu1_di1>, <&ipu2_di0>, <&ipu2_di1>;
	};

	gpu-subsystem {
		compatible = "fsl,imx-gpu-subsystem";
		cores = <&gpu_2d>, <&gpu_3d>, <&gpu_vg>;
	};
};

&gpio1 {
	gpio-ranges = <&iomuxc  0 136  2>, <&iomuxc  2 141 1>, <&iomuxc  3 139 1>,
		      <&iomuxc  4 142  2>, <&iomuxc  6 140 1>, <&iomuxc  7 144 2>,
		      <&iomuxc  9 138  1>, <&iomuxc 10 213 3>, <&iomuxc 13  20 1>,
		      <&iomuxc 14  19  1>, <&iomuxc 15  21 1>, <&iomuxc 16 208 1>,
		      <&iomuxc 17 207  1>, <&iomuxc 18 210 3>, <&iomuxc 21 209 1>,
		      <&iomuxc 22 116 10>;
};

&gpio2 {
	gpio-ranges = <&iomuxc  0 191 16>, <&iomuxc 16 55 14>, <&iomuxc 30 35 1>,
		      <&iomuxc 31  44  1>;
};

&gpio3 {
	gpio-ranges = <&iomuxc 0 69 16>, <&iomuxc 16 36 8>, <&iomuxc 24 45 8>;
};

&gpio4 {
	gpio-ranges = <&iomuxc 5 149 1>, <&iomuxc 6 126 10>, <&iomuxc 16 87 16>;
};

&gpio5 {
	gpio-ranges = <&iomuxc 0  85  1>, <&iomuxc  2  34  1>, <&iomuxc 4 53 1>,
		      <&iomuxc 5 103 13>, <&iomuxc 18 150 14>;
};

&gpio6 {
	gpio-ranges = <&iomuxc  0 164 6>, <&iomuxc  6  54 1>, <&iomuxc  7 181  5>,
		      <&iomuxc 14 186 3>, <&iomuxc 17 170 2>, <&iomuxc 19  22 12>,
		      <&iomuxc 31  86 1>;
};

&gpio7 {
	gpio-ranges = <&iomuxc 0 172 9>, <&iomuxc 9 189 2>, <&iomuxc 11 146 3>;
};

&hdmi {
	compatible = "fsl,imx6q-hdmi";

	port@2 {
		reg = <2>;

		hdmi_mux_2: endpoint {
			remote-endpoint = <&ipu2_di0_hdmi>;
		};
	};

	port@3 {
		reg = <3>;

		hdmi_mux_3: endpoint {
			remote-endpoint = <&ipu2_di1_hdmi>;
		};
	};
};

&ldb {
	clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
		 <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>,
		 <&clks IMX6QDL_CLK_IPU2_DI0_SEL>, <&clks IMX6QDL_CLK_IPU2_DI1_SEL>,
		 <&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>;
	clock-names = "di0_pll", "di1_pll",
		      "di0_sel", "di1_sel", "di2_sel", "di3_sel",
		      "di0", "di1";

	lvds-channel@0 {
		port@2 {
			reg = <2>;

			lvds0_mux_2: endpoint {
				remote-endpoint = <&ipu2_di0_lvds0>;
			};
		};

		port@3 {
			reg = <3>;

			lvds0_mux_3: endpoint {
				remote-endpoint = <&ipu2_di1_lvds0>;
			};
		};
	};

	lvds-channel@1 {
		port@2 {
			reg = <2>;

			lvds1_mux_2: endpoint {
				remote-endpoint = <&ipu2_di0_lvds1>;
			};
		};

		port@3 {
			reg = <3>;

			lvds1_mux_3: endpoint {
				remote-endpoint = <&ipu2_di1_lvds1>;
			};
		};
	};
};

&mipi_dsi {
	ports {
		port@2 {
			reg = <2>;

			mipi_mux_2: endpoint {
				remote-endpoint = <&ipu2_di0_mipi>;
			};
		};

		port@3 {
			reg = <3>;

			mipi_mux_3: endpoint {
				remote-endpoint = <&ipu2_di1_mipi>;
			};
		};
	};
};

&vpu {
	compatible = "fsl,imx6q-vpu", "cnm,coda960";
};
Commit	Line	Data
7c1da585 SG	1
	2	/*
	3	* Copyright 2013 Freescale Semiconductor, Inc.
	4	*
	5	* This program is free software; you can redistribute it and/or modify
	6	* it under the terms of the GNU General Public License version 2 as
	7	* published by the Free Software Foundation.
	8	*
	9	*/
	10
e6117ff3	11	#include <dt-bindings/interrupt-controller/irq.h>
e1641531	12	#include "imx6q-pinfunc.h"
c56009b2	13	#include "imx6qdl.dtsi"
7c1da585 SG	14
7c1da585 SG	15	/ {
a26be0f0	16	aliases {
41beef39	17	ipu1 = &ipu2;
a26be0f0 SH	18	spi4 = &ecspi5;
	19	};
	20
7c1da585 SG	21	cpus {
	22	#address-cells = <1>;
	23	#size-cells = <0>;
	24
5d625375	25	cpu0: cpu@0 {
7c1da585	26	compatible = "arm,cortex-a9";
7925e89f	27	device_type = "cpu";
7c1da585 SG	28	reg = <0>;
	29	next-level-cache = <&L2>;
	30	operating-points = <
	31	/* kHz uV */
	32	1200000 1275000
	33	996000 1250000
89ef8ef4	34	852000 1250000
eabb3227	35	792000 1175000
26ea5801	36	396000 975000
7c1da585	37	>;
69171eda AH	38	fsl,soc-operating-points = <
	39	/* ARM kHz SOC-PU uV */
	40	1200000 1275000
	41	996000 1250000
89ef8ef4	42	852000 1250000
69171eda AH	43	792000 1175000
69171eda AH	44	396000 1175000
7c1da585 SG	45	>;
7c1da585 SG	46	clock-latency = <61036>; /* two CLK32 periods */
8888f651 SG	47	clocks = <&clks IMX6QDL_CLK_ARM>,
	48	<&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
	49	<&clks IMX6QDL_CLK_STEP>,
	50	<&clks IMX6QDL_CLK_PLL1_SW>,
	51	<&clks IMX6QDL_CLK_PLL1_SYS>;
7c1da585 SG	52	clock-names = "arm", "pll2_pfd2_396m", "step",
	53	"pll1_sw", "pll1_sys";
	54	arm-supply = <&reg_arm>;
	55	pu-supply = <&reg_pu>;
	56	soc-supply = <&reg_soc>;
	57	};
	58
	59	cpu@1 {
	60	compatible = "arm,cortex-a9";
7925e89f	61	device_type = "cpu";
7c1da585 SG	62	reg = <1>;
	63	next-level-cache = <&L2>;
	64	};
	65
	66	cpu@2 {
	67	compatible = "arm,cortex-a9";
7925e89f	68	device_type = "cpu";
7c1da585 SG	69	reg = <2>;
	70	next-level-cache = <&L2>;
	71	};
	72
	73	cpu@3 {
	74	compatible = "arm,cortex-a9";
7925e89f	75	device_type = "cpu";
7c1da585 SG	76	reg = <3>;
	77	next-level-cache = <&L2>;
	78	};
	79	};
	80
	81	soc {
951ebf58 SG	82	ocram: sram@00900000 {
	83	compatible = "mmio-sram";
	84	reg = <0x00900000 0x40000>;
8888f651	85	clocks = <&clks IMX6QDL_CLK_OCRAM>;
951ebf58 SG	86	};
951ebf58 SG	87
7c1da585 SG	88	aips-bus@02000000 { /* AIPS1 */
	89	spba-bus@02000000 {
	90	ecspi5: ecspi@02018000 {
	91	#address-cells = <1>;
	92	#size-cells = <0>;
	93	compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
	94	reg = <0x02018000 0x4000>;
e6117ff3	95	interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
8888f651 SG	96	clocks = <&clks IMX6Q_CLK_ECSPI5>,
8888f651 SG	97	<&clks IMX6Q_CLK_ECSPI5>;
7c1da585	98	clock-names = "ipg", "per";
67794025 AB	99	dmas = <&sdma 11 7 1>, <&sdma 12 7 2>;
67794025 AB	100	dma-names = "rx", "tx";
7c1da585 SG	101	status = "disabled";
	102	};
	103	};
	104
	105	iomuxc: iomuxc@020e0000 {
	106	compatible = "fsl,imx6q-iomuxc";
7c1da585 SG	107	};
	108	};
	109
0fb1f804 RZ	110	sata: sata@02200000 {
	111	compatible = "fsl,imx6q-ahci";
	112	reg = <0x02200000 0x4000>;
e6117ff3	113	interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
8888f651 SG	114	clocks = <&clks IMX6QDL_CLK_SATA>,
	115	<&clks IMX6QDL_CLK_SATA_REF_100M>,
	116	<&clks IMX6QDL_CLK_AHB>;
0fb1f804 RZ	117	clock-names = "sata", "sata_ref", "ahb";
	118	status = "disabled";
	119	};
	120
419e202b LS	121	gpu_vg: gpu@02204000 {
	122	compatible = "vivante,gc";
	123	reg = <0x02204000 0x4000>;
	124	interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
	125	clocks = <&clks IMX6QDL_CLK_OPENVG_AXI>,
	126	<&clks IMX6QDL_CLK_GPU2D_CORE>;
	127	clock-names = "bus", "core";
	128	power-domains = <&gpc 1>;
	129	};
	130
7c1da585	131	ipu2: ipu@02800000 {
4520e692 PZ	132	#address-cells = <1>;
4520e692 PZ	133	#size-cells = <0>;
7c1da585 SG	134	compatible = "fsl,imx6q-ipu";
7c1da585 SG	135	reg = <0x02800000 0x400000>;
e6117ff3 TK	136	interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>,
e6117ff3 TK	137	<0 7 IRQ_TYPE_LEVEL_HIGH>;
8888f651 SG	138	clocks = <&clks IMX6QDL_CLK_IPU2>,
	139	<&clks IMX6QDL_CLK_IPU2_DI0>,
	140	<&clks IMX6QDL_CLK_IPU2_DI1>;
7c1da585	141	clock-names = "bus", "di0", "di1";
09ebf366	142	resets = <&src 4>;
4520e692	143
c0470c38 PZ	144	ipu2_csi0: port@0 {
	145	reg = <0>;
	146	};
	147
	148	ipu2_csi1: port@1 {
	149	reg = <1>;
	150	};
	151
4520e692 PZ	152	ipu2_di0: port@2 {
	153	#address-cells = <1>;
	154	#size-cells = <0>;
	155	reg = <2>;
	156
416196cd	157	ipu2_di0_disp0: disp0-endpoint {
4520e692 PZ	158	};
4520e692 PZ	159
416196cd	160	ipu2_di0_hdmi: hdmi-endpoint {
4520e692 PZ	161	remote-endpoint = <&hdmi_mux_2>;
	162	};
	163
416196cd	164	ipu2_di0_mipi: mipi-endpoint {
28f2c118	165	remote-endpoint = <&mipi_mux_2>;
4520e692 PZ	166	};
4520e692 PZ	167
416196cd	168	ipu2_di0_lvds0: lvds0-endpoint {
4520e692 PZ	169	remote-endpoint = <&lvds0_mux_2>;
	170	};
	171
416196cd	172	ipu2_di0_lvds1: lvds1-endpoint {
4520e692 PZ	173	remote-endpoint = <&lvds1_mux_2>;
	174	};
	175	};
	176
	177	ipu2_di1: port@3 {
	178	#address-cells = <1>;
	179	#size-cells = <0>;
	180	reg = <3>;
	181
416196cd	182	ipu2_di1_hdmi: hdmi-endpoint {
4520e692 PZ	183	remote-endpoint = <&hdmi_mux_3>;
	184	};
	185
416196cd	186	ipu2_di1_mipi: mipi-endpoint {
28f2c118	187	remote-endpoint = <&mipi_mux_3>;
4520e692 PZ	188	};
4520e692 PZ	189
416196cd	190	ipu2_di1_lvds0: lvds0-endpoint {
4520e692 PZ	191	remote-endpoint = <&lvds0_mux_3>;
	192	};
	193
416196cd	194	ipu2_di1_lvds1: lvds1-endpoint {
4520e692 PZ	195	remote-endpoint = <&lvds1_mux_3>;
	196	};
	197	};
	198	};
	199	};
	200
	201	display-subsystem {
	202	compatible = "fsl,imx-display-subsystem";
	203	ports = <&ipu1_di0>, <&ipu1_di1>, <&ipu2_di0>, <&ipu2_di1>;
	204	};
419e202b LS	205
	206	gpu-subsystem {
	207	compatible = "fsl,imx-gpu-subsystem";
	208	cores = <&gpu_2d>, <&gpu_3d>, <&gpu_vg>;
	209	};
4520e692 PZ	210	};
4520e692 PZ	211
bb728d66 VZ	212	&gpio1 {
	213	gpio-ranges = <&iomuxc 0 136 2>, <&iomuxc 2 141 1>, <&iomuxc 3 139 1>,
	214	<&iomuxc 4 142 2>, <&iomuxc 6 140 1>, <&iomuxc 7 144 2>,
	215	<&iomuxc 9 138 1>, <&iomuxc 10 213 3>, <&iomuxc 13 20 1>,
	216	<&iomuxc 14 19 1>, <&iomuxc 15 21 1>, <&iomuxc 16 208 1>,
	217	<&iomuxc 17 207 1>, <&iomuxc 18 210 3>, <&iomuxc 21 209 1>,
	218	<&iomuxc 22 116 10>;
	219	};
	220
	221	&gpio2 {
	222	gpio-ranges = <&iomuxc 0 191 16>, <&iomuxc 16 55 14>, <&iomuxc 30 35 1>,
	223	<&iomuxc 31 44 1>;
	224	};
	225
	226	&gpio3 {
	227	gpio-ranges = <&iomuxc 0 69 16>, <&iomuxc 16 36 8>, <&iomuxc 24 45 8>;
	228	};
	229
	230	&gpio4 {
	231	gpio-ranges = <&iomuxc 5 149 1>, <&iomuxc 6 126 10>, <&iomuxc 16 87 16>;
	232	};
	233
	234	&gpio5 {
	235	gpio-ranges = <&iomuxc 0 85 1>, <&iomuxc 2 34 1>, <&iomuxc 4 53 1>,
	236	<&iomuxc 5 103 13>, <&iomuxc 18 150 14>;
	237	};
	238
	239	&gpio6 {
	240	gpio-ranges = <&iomuxc 0 164 6>, <&iomuxc 6 54 1>, <&iomuxc 7 181 5>,
	241	<&iomuxc 14 186 3>, <&iomuxc 17 170 2>, <&iomuxc 19 22 12>,
	242	<&iomuxc 31 86 1>;
	243	};
	244
	245	&gpio7 {
	246	gpio-ranges = <&iomuxc 0 172 9>, <&iomuxc 9 189 2>, <&iomuxc 11 146 3>;
	247	};
	248
4520e692 PZ	249	&hdmi {
	250	compatible = "fsl,imx6q-hdmi";
	251
	252	port@2 {
	253	reg = <2>;
	254
	255	hdmi_mux_2: endpoint {
	256	remote-endpoint = <&ipu2_di0_hdmi>;
	257	};
	258	};
	259
	260	port@3 {
	261	reg = <3>;
	262
	263	hdmi_mux_3: endpoint {
	264	remote-endpoint = <&ipu2_di1_hdmi>;
7c1da585 SG	265	};
	266	};
	267	};
41c04342 ST	268
41c04342 ST	269	&ldb {
8888f651 SG	270	clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
	271	<&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>,
	272	<&clks IMX6QDL_CLK_IPU2_DI0_SEL>, <&clks IMX6QDL_CLK_IPU2_DI1_SEL>,
	273	<&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>;
41c04342 ST	274	clock-names = "di0_pll", "di1_pll",
	275	"di0_sel", "di1_sel", "di2_sel", "di3_sel",
	276	"di0", "di1";
	277
	278	lvds-channel@0 {
4520e692 PZ	279	port@2 {
	280	reg = <2>;
	281
	282	lvds0_mux_2: endpoint {
	283	remote-endpoint = <&ipu2_di0_lvds0>;
	284	};
	285	};
	286
	287	port@3 {
	288	reg = <3>;
	289
	290	lvds0_mux_3: endpoint {
	291	remote-endpoint = <&ipu2_di1_lvds0>;
	292	};
	293	};
41c04342 ST	294	};
	295
	296	lvds-channel@1 {
4520e692 PZ	297	port@2 {
	298	reg = <2>;
	299
	300	lvds1_mux_2: endpoint {
	301	remote-endpoint = <&ipu2_di0_lvds1>;
	302	};
	303	};
	304
	305	port@3 {
	306	reg = <3>;
	307
	308	lvds1_mux_3: endpoint {
	309	remote-endpoint = <&ipu2_di1_lvds1>;
	310	};
	311	};
41c04342 ST	312	};
41c04342 ST	313	};
04cec1a2	314
4520e692	315	&mipi_dsi {
70c2652c LY	316	ports {
	317	port@2 {
	318	reg = <2>;
4520e692	319
70c2652c LY	320	mipi_mux_2: endpoint {
	321	remote-endpoint = <&ipu2_di0_mipi>;
	322	};
4520e692	323	};
4520e692	324
70c2652c LY	325	port@3 {
70c2652c LY	326	reg = <3>;
4520e692	327
70c2652c LY	328	mipi_mux_3: endpoint {
	329	remote-endpoint = <&ipu2_di1_mipi>;
	330	};
4520e692 PZ	331	};
4520e692 PZ	332	};
04cec1a2	333	};
a04a0b6f PZ	334
	335	&vpu {
	336	compatible = "fsl,imx6q-vpu", "cnm,coda960";
	337	};