[deliverable/linux.git] / arch / arm / boot / dts / keystone.dtsi

/*
 * Copyright 2013 Texas Instruments, Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/gpio/gpio.h>

#include "skeleton.dtsi"

/ {
	compatible = "ti,keystone";
	model = "Texas Instruments Keystone 2 SoC";
	#address-cells = <2>;
	#size-cells = <2>;
	interrupt-parent = <&gic>;

	aliases {
		serial0	= &uart0;
		spi0 = &spi0;
		spi1 = &spi1;
		spi2 = &spi2;
	};

	memory {
		reg = <0x00000000 0x80000000 0x00000000 0x40000000>;
	};

	gic: interrupt-controller {
		compatible = "arm,cortex-a15-gic";
		#interrupt-cells = <3>;
		interrupt-controller;
		reg = <0x0 0x02561000 0x0 0x1000>,
		      <0x0 0x02562000 0x0 0x2000>,
		      <0x0 0x02564000 0x0 0x1000>,
		      <0x0 0x02566000 0x0 0x2000>;
		interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
				IRQ_TYPE_LEVEL_HIGH)>;
	};

	timer {
		compatible = "arm,armv7-timer";
		interrupts =
			<GIC_PPI 13
				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			<GIC_PPI 14
				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			<GIC_PPI 11
				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			<GIC_PPI 10
				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
	};

	pmu {
		compatible = "arm,cortex-a15-pmu";
		interrupts = <GIC_SPI 20 IRQ_TYPE_EDGE_RISING>,
			     <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
			     <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>,
			     <GIC_SPI 23 IRQ_TYPE_EDGE_RISING>;
	};

	psci {
		compatible	= "arm,psci";
		method		= "smc";
		cpu_suspend	= <0x84000001>;
		cpu_off		= <0x84000002>;
		cpu_on		= <0x84000003>;
	};

	soc {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "ti,keystone","simple-bus";
		interrupt-parent = <&gic>;
		ranges = <0x0 0x0 0x0 0xc0000000>;
		dma-ranges = <0x80000000 0x8 0x00000000 0x80000000>;

		pllctrl: pll-controller@02310000 {
			compatible = "ti,keystone-pllctrl", "syscon";
			reg = <0x02310000 0x200>;
		};

		devctrl: device-state-control@02620000 {
			compatible = "ti,keystone-devctrl", "syscon";
			reg = <0x02620000 0x1000>;
		};

		rstctrl: reset-controller {
			compatible = "ti,keystone-reset";
			ti,syscon-pll = <&pllctrl 0xe4>;
			ti,syscon-dev = <&devctrl 0x328>;
			ti,wdt-list = <0>;
		};

		/include/ "keystone-clocks.dtsi"

		uart0: serial@02530c00 {
			compatible = "ns16550a";
			current-speed = <115200>;
			reg-shift = <2>;
			reg-io-width = <4>;
			reg = <0x02530c00 0x100>;
			clocks	= <&clkuart0>;
			interrupts = <GIC_SPI 277 IRQ_TYPE_EDGE_RISING>;
		};

		uart1:	serial@02531000 {
			compatible = "ns16550a";
			current-speed = <115200>;
			reg-shift = <2>;
			reg-io-width = <4>;
			reg = <0x02531000 0x100>;
			clocks	= <&clkuart1>;
			interrupts = <GIC_SPI 280 IRQ_TYPE_EDGE_RISING>;
		};

		i2c0: i2c@2530000 {
			compatible = "ti,davinci-i2c";
			reg = <0x02530000 0x400>;
			clock-frequency = <100000>;
			clocks = <&clki2c>;
			interrupts = <GIC_SPI 283 IRQ_TYPE_EDGE_RISING>;
			#address-cells = <1>;
			#size-cells = <0>;
		};

		i2c1: i2c@2530400 {
			compatible = "ti,davinci-i2c";
			reg = <0x02530400 0x400>;
			clock-frequency = <100000>;
			clocks = <&clki2c>;
			interrupts = <GIC_SPI 286 IRQ_TYPE_EDGE_RISING>;
			#address-cells = <1>;
			#size-cells = <0>;
		};

		i2c2: i2c@2530800 {
			compatible = "ti,davinci-i2c";
			reg = <0x02530800 0x400>;
			clock-frequency = <100000>;
			clocks = <&clki2c>;
			interrupts = <GIC_SPI 289 IRQ_TYPE_EDGE_RISING>;
			#address-cells = <1>;
			#size-cells = <0>;
		};

		spi0: spi@21000400 {
			compatible = "ti,keystone-spi", "ti,dm6441-spi";
			reg = <0x21000400 0x200>;
			num-cs = <4>;
			ti,davinci-spi-intr-line = <0>;
			interrupts = <GIC_SPI 292 IRQ_TYPE_EDGE_RISING>;
			clocks = <&clkspi>;
			#address-cells = <1>;
			#size-cells = <0>;
		};

		spi1: spi@21000600 {
			compatible = "ti,keystone-spi", "ti,dm6441-spi";
			reg = <0x21000600 0x200>;
			num-cs = <4>;
			ti,davinci-spi-intr-line = <0>;
			interrupts = <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>;
			clocks = <&clkspi>;
			#address-cells = <1>;
			#size-cells = <0>;
		};

		spi2: spi@21000800 {
			compatible = "ti,keystone-spi", "ti,dm6441-spi";
			reg = <0x21000800 0x200>;
			num-cs = <4>;
			ti,davinci-spi-intr-line = <0>;
			interrupts = <GIC_SPI 300 IRQ_TYPE_EDGE_RISING>;
			clocks = <&clkspi>;
			#address-cells = <1>;
			#size-cells = <0>;
		};

		usb_phy: usb_phy@2620738 {
			compatible = "ti,keystone-usbphy";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0x2620738 24>;
			status = "disabled";
		};

		usb: usb@2680000 {
			compatible = "ti,keystone-dwc3";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0x2680000 0x10000>;
			clocks = <&clkusb>;
			clock-names = "usb";
			interrupts = <GIC_SPI 393 IRQ_TYPE_EDGE_RISING>;
			ranges;
			dma-coherent;
			dma-ranges;
			status = "disabled";

			dwc3@2690000 {
				compatible = "synopsys,dwc3";
				reg = <0x2690000 0x70000>;
				interrupts = <GIC_SPI 393 IRQ_TYPE_EDGE_RISING>;
				usb-phy = <&usb_phy>, <&usb_phy>;
			};
		};

		wdt: wdt@022f0080 {
			compatible = "ti,keystone-wdt","ti,davinci-wdt";
			reg = <0x022f0080 0x80>;
			clocks = <&clkwdtimer0>;
		};

		clock_event: timer@22f0000 {
			compatible = "ti,keystone-timer";
			reg = <0x022f0000 0x80>;
			interrupts = <GIC_SPI 110 IRQ_TYPE_EDGE_RISING>;
			clocks = <&clktimer15>;
		};

		gpio0: gpio@260bf00 {
			compatible = "ti,keystone-gpio";
			reg = <0x0260bf00 0x100>;
			gpio-controller;
			#gpio-cells = <2>;
			/* HW Interrupts mapped to GPIO pins */
			interrupts = <GIC_SPI 120 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 121 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 122 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 123 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 124 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 125 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 126 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 127 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 128 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 129 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 130 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 131 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 132 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 133 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 134 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 135 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 136 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 137 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 138 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 139 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 140 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 141 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 142 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 143 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 144 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 145 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 146 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 147 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 148 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 149 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 150 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 151 IRQ_TYPE_EDGE_RISING>;
			clocks = <&clkgpio>;
			clock-names = "gpio";
			ti,ngpio = <32>;
			ti,davinci-gpio-unbanked = <32>;
		};

		aemif: aemif@21000A00 {
			compatible = "ti,keystone-aemif", "ti,davinci-aemif";
			#address-cells = <2>;
			#size-cells = <1>;
			clocks = <&clkaemif>;
			clock-names = "aemif";
			clock-ranges;

			reg = <0x21000A00 0x00000100>;
			ranges = <0 0 0x30000000 0x10000000
				  1 0 0x21000A00 0x00000100>;
		};

		kirq0: keystone_irq@26202a0 {
			compatible = "ti,keystone-irq";
			interrupts = <GIC_SPI 4 IRQ_TYPE_EDGE_RISING>;
			interrupt-controller;
			#interrupt-cells = <1>;
			ti,syscon-dev = <&devctrl 0x2a0>;
		};

		pcie0: pcie@21800000 {
			compatible = "ti,keystone-pcie", "snps,dw-pcie";
			clocks = <&clkpcie>;
			clock-names = "pcie";
			#address-cells = <3>;
			#size-cells = <2>;
			reg =  <0x21801000 0x2000>, <0x21800000 0x1000>, <0x02620128 4>;
			ranges = <0x82000000 0 0x50000000 0x50000000
				  0 0x10000000>;

			status = "disabled";
			device_type = "pci";
			num-lanes = <2>;
			bus-range = <0x00 0xff>;

			/* error interrupt */
			interrupts = <GIC_SPI 38 IRQ_TYPE_EDGE_RISING>;
			#interrupt-cells = <1>;
			interrupt-map-mask = <0 0 0 7>;
			interrupt-map = <0 0 0 1 &pcie_intc0 0>, /* INT A */
					<0 0 0 2 &pcie_intc0 1>, /* INT B */
					<0 0 0 3 &pcie_intc0 2>, /* INT C */
					<0 0 0 4 &pcie_intc0 3>; /* INT D */

			pcie_msi_intc0: msi-interrupt-controller {
				interrupt-controller;
				#interrupt-cells = <1>;
				interrupt-parent = <&gic>;
				interrupts = <GIC_SPI 30 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 31 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 32 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 33 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 34 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 35 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 36 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 37 IRQ_TYPE_EDGE_RISING>;
			};

			pcie_intc0: legacy-interrupt-controller {
				interrupt-controller;
				#interrupt-cells = <1>;
				interrupt-parent = <&gic>;
				interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 27 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 28 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 29 IRQ_TYPE_EDGE_RISING>;
			};
		};
	};
};
Commit	Line	Data
d5e9fe84 SS	1	/*
	2	* Copyright 2013 Texas Instruments, Inc.
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License version 2 as
	6	* published by the Free Software Foundation.
	7	*/
	8
eb788f43	9	#include <dt-bindings/interrupt-controller/arm-gic.h>
970c2256	10	#include <dt-bindings/gpio/gpio.h>
eb788f43	11
226d1c5b	12	#include "skeleton.dtsi"
d5e9fe84 SS	13
d5e9fe84 SS	14	/ {
91dca0f0	15	compatible = "ti,keystone";
d5e9fe84	16	model = "Texas Instruments Keystone 2 SoC";
d5e9fe84 SS	17	#address-cells = <2>;
	18	#size-cells = <2>;
	19	interrupt-parent = <&gic>;
	20
	21	aliases {
	22	serial0 = &uart0;
72f7e959 V	23	spi0 = &spi0;
	24	spi1 = &spi1;
	25	spi2 = &spi2;
d5e9fe84 SS	26	};
	27
	28	memory {
	29	reg = <0x00000000 0x80000000 0x00000000 0x40000000>;
	30	};
	31
d5e9fe84 SS	32	gic: interrupt-controller {
	33	compatible = "arm,cortex-a15-gic";
	34	#interrupt-cells = <3>;
d5e9fe84 SS	35	interrupt-controller;
d5e9fe84 SS	36	reg = <0x0 0x02561000 0x0 0x1000>,
a18b4aa2 SS	37	<0x0 0x02562000 0x0 0x2000>,
	38	<0x0 0x02564000 0x0 0x1000>,
	39	<0x0 0x02566000 0x0 0x2000>;
0ee15444 SS	40	interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) \|
0ee15444 SS	41	IRQ_TYPE_LEVEL_HIGH)>;
d5e9fe84 SS	42	};
	43
	44	timer {
	45	compatible = "arm,armv7-timer";
eb788f43 SS	46	interrupts =
	47	<GIC_PPI 13
	48	(GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
	49	<GIC_PPI 14
	50	(GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
	51	<GIC_PPI 11
	52	(GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
	53	<GIC_PPI 10
	54	(GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>;
d5e9fe84 SS	55	};
	56
	57	pmu {
	58	compatible = "arm,cortex-a15-pmu";
eb788f43 SS	59	interrupts = <GIC_SPI 20 IRQ_TYPE_EDGE_RISING>,
	60	<GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
	61	<GIC_SPI 22 IRQ_TYPE_EDGE_RISING>,
	62	<GIC_SPI 23 IRQ_TYPE_EDGE_RISING>;
d5e9fe84 SS	63	};
d5e9fe84 SS	64
14de48a4 VA	65	psci {
	66	compatible = "arm,psci";
	67	method = "smc";
	68	cpu_suspend = <0x84000001>;
	69	cpu_off = <0x84000002>;
	70	cpu_on = <0x84000003>;
	71	};
	72
d5e9fe84 SS	73	soc {
	74	#address-cells = <1>;
	75	#size-cells = <1>;
	76	compatible = "ti,keystone","simple-bus";
	77	interrupt-parent = <&gic>;
	78	ranges = <0x0 0x0 0x0 0xc0000000>;
4d46596d	79	dma-ranges = <0x80000000 0x8 0x00000000 0x80000000>;
d5e9fe84	80
ded79beb IK	81	pllctrl: pll-controller@02310000 {
	82	compatible = "ti,keystone-pllctrl", "syscon";
	83	reg = <0x02310000 0x200>;
	84	};
	85
	86	devctrl: device-state-control@02620000 {
	87	compatible = "ti,keystone-devctrl", "syscon";
	88	reg = <0x02620000 0x1000>;
	89	};
	90
d5e9fe84 SS	91	rstctrl: reset-controller {
d5e9fe84 SS	92	compatible = "ti,keystone-reset";
ded79beb IK	93	ti,syscon-pll = <&pllctrl 0xe4>;
	94	ti,syscon-dev = <&devctrl 0x328>;
	95	ti,wdt-list = <0>;
d5e9fe84 SS	96	};
d5e9fe84 SS	97
feeea8f3 SS	98	/include/ "keystone-clocks.dtsi"
feeea8f3 SS	99
d5e9fe84 SS	100	uart0: serial@02530c00 {
	101	compatible = "ns16550a";
	102	current-speed = <115200>;
	103	reg-shift = <2>;
	104	reg-io-width = <4>;
	105	reg = <0x02530c00 0x100>;
f023bd10	106	clocks = <&clkuart0>;
eb788f43	107	interrupts = <GIC_SPI 277 IRQ_TYPE_EDGE_RISING>;
d5e9fe84 SS	108	};
	109
	110	uart1: serial@02531000 {
	111	compatible = "ns16550a";
	112	current-speed = <115200>;
	113	reg-shift = <2>;
	114	reg-io-width = <4>;
	115	reg = <0x02531000 0x100>;
f023bd10	116	clocks = <&clkuart1>;
eb788f43	117	interrupts = <GIC_SPI 280 IRQ_TYPE_EDGE_RISING>;
d5e9fe84 SS	118	};
d5e9fe84 SS	119
6120ac23 SS	120	i2c0: i2c@2530000 {
	121	compatible = "ti,davinci-i2c";
	122	reg = <0x02530000 0x400>;
	123	clock-frequency = <100000>;
	124	clocks = <&clki2c>;
	125	interrupts = <GIC_SPI 283 IRQ_TYPE_EDGE_RISING>;
	126	#address-cells = <1>;
	127	#size-cells = <0>;
6120ac23 SS	128	};
	129
	130	i2c1: i2c@2530400 {
	131	compatible = "ti,davinci-i2c";
	132	reg = <0x02530400 0x400>;
	133	clock-frequency = <100000>;
	134	clocks = <&clki2c>;
	135	interrupts = <GIC_SPI 286 IRQ_TYPE_EDGE_RISING>;
3953505a GS	136	#address-cells = <1>;
3953505a GS	137	#size-cells = <0>;
6120ac23 SS	138	};
	139
	140	i2c2: i2c@2530800 {
	141	compatible = "ti,davinci-i2c";
	142	reg = <0x02530800 0x400>;
	143	clock-frequency = <100000>;
	144	clocks = <&clki2c>;
	145	interrupts = <GIC_SPI 289 IRQ_TYPE_EDGE_RISING>;
3953505a GS	146	#address-cells = <1>;
3953505a GS	147	#size-cells = <0>;
6120ac23	148	};
b3bd6c59 SS	149
b3bd6c59 SS	150	spi0: spi@21000400 {
1a344e9b	151	compatible = "ti,keystone-spi", "ti,dm6441-spi";
b3bd6c59 SS	152	reg = <0x21000400 0x200>;
	153	num-cs = <4>;
	154	ti,davinci-spi-intr-line = <0>;
	155	interrupts = <GIC_SPI 292 IRQ_TYPE_EDGE_RISING>;
	156	clocks = <&clkspi>;
509046a7 GS	157	#address-cells = <1>;
509046a7 GS	158	#size-cells = <0>;
b3bd6c59 SS	159	};
	160
	161	spi1: spi@21000600 {
1a344e9b	162	compatible = "ti,keystone-spi", "ti,dm6441-spi";
b3bd6c59 SS	163	reg = <0x21000600 0x200>;
	164	num-cs = <4>;
	165	ti,davinci-spi-intr-line = <0>;
	166	interrupts = <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>;
	167	clocks = <&clkspi>;
509046a7 GS	168	#address-cells = <1>;
509046a7 GS	169	#size-cells = <0>;
b3bd6c59 SS	170	};
	171
	172	spi2: spi@21000800 {
1a344e9b	173	compatible = "ti,keystone-spi", "ti,dm6441-spi";
b3bd6c59 SS	174	reg = <0x21000800 0x200>;
	175	num-cs = <4>;
	176	ti,davinci-spi-intr-line = <0>;
	177	interrupts = <GIC_SPI 300 IRQ_TYPE_EDGE_RISING>;
	178	clocks = <&clkspi>;
509046a7 GS	179	#address-cells = <1>;
509046a7 GS	180	#size-cells = <0>;
b3bd6c59	181	};
08c36762 WK	182
	183	usb_phy: usb_phy@2620738 {
	184	compatible = "ti,keystone-usbphy";
	185	#address-cells = <1>;
	186	#size-cells = <1>;
cfb198ce	187	reg = <0x2620738 24>;
08c36762 WK	188	status = "disabled";
08c36762 WK	189	};
73207956 WK	190
	191	usb: usb@2680000 {
	192	compatible = "ti,keystone-dwc3";
	193	#address-cells = <1>;
	194	#size-cells = <1>;
	195	reg = <0x2680000 0x10000>;
	196	clocks = <&clkusb>;
	197	clock-names = "usb";
	198	interrupts = <GIC_SPI 393 IRQ_TYPE_EDGE_RISING>;
	199	ranges;
86156978 SS	200	dma-coherent;
86156978 SS	201	dma-ranges;
73207956 WK	202	status = "disabled";
	203
	204	dwc3@2690000 {
	205	compatible = "synopsys,dwc3";
	206	reg = <0x2690000 0x70000>;
	207	interrupts = <GIC_SPI 393 IRQ_TYPE_EDGE_RISING>;
	208	usb-phy = <&usb_phy>, <&usb_phy>;
	209	};
	210	};
20d89313 IK	211
	212	wdt: wdt@022f0080 {
	213	compatible = "ti,keystone-wdt","ti,davinci-wdt";
	214	reg = <0x022f0080 0x80>;
	215	clocks = <&clkwdtimer0>;
	216	};
2b4f76b6 IK	217
	218	clock_event: timer@22f0000 {
	219	compatible = "ti,keystone-timer";
	220	reg = <0x022f0000 0x80>;
	221	interrupts = <GIC_SPI 110 IRQ_TYPE_EDGE_RISING>;
	222	clocks = <&clktimer15>;
	223	};
970c2256 GS	224
	225	gpio0: gpio@260bf00 {
	226	compatible = "ti,keystone-gpio";
	227	reg = <0x0260bf00 0x100>;
	228	gpio-controller;
	229	#gpio-cells = <2>;
	230	/* HW Interrupts mapped to GPIO pins */
	231	interrupts = <GIC_SPI 120 IRQ_TYPE_EDGE_RISING>,
	232	<GIC_SPI 121 IRQ_TYPE_EDGE_RISING>,
	233	<GIC_SPI 122 IRQ_TYPE_EDGE_RISING>,
	234	<GIC_SPI 123 IRQ_TYPE_EDGE_RISING>,
	235	<GIC_SPI 124 IRQ_TYPE_EDGE_RISING>,
	236	<GIC_SPI 125 IRQ_TYPE_EDGE_RISING>,
	237	<GIC_SPI 126 IRQ_TYPE_EDGE_RISING>,
	238	<GIC_SPI 127 IRQ_TYPE_EDGE_RISING>,
	239	<GIC_SPI 128 IRQ_TYPE_EDGE_RISING>,
	240	<GIC_SPI 129 IRQ_TYPE_EDGE_RISING>,
	241	<GIC_SPI 130 IRQ_TYPE_EDGE_RISING>,
	242	<GIC_SPI 131 IRQ_TYPE_EDGE_RISING>,
	243	<GIC_SPI 132 IRQ_TYPE_EDGE_RISING>,
	244	<GIC_SPI 133 IRQ_TYPE_EDGE_RISING>,
	245	<GIC_SPI 134 IRQ_TYPE_EDGE_RISING>,
	246	<GIC_SPI 135 IRQ_TYPE_EDGE_RISING>,
	247	<GIC_SPI 136 IRQ_TYPE_EDGE_RISING>,
	248	<GIC_SPI 137 IRQ_TYPE_EDGE_RISING>,
	249	<GIC_SPI 138 IRQ_TYPE_EDGE_RISING>,
	250	<GIC_SPI 139 IRQ_TYPE_EDGE_RISING>,
	251	<GIC_SPI 140 IRQ_TYPE_EDGE_RISING>,
	252	<GIC_SPI 141 IRQ_TYPE_EDGE_RISING>,
	253	<GIC_SPI 142 IRQ_TYPE_EDGE_RISING>,
	254	<GIC_SPI 143 IRQ_TYPE_EDGE_RISING>,
	255	<GIC_SPI 144 IRQ_TYPE_EDGE_RISING>,
	256	<GIC_SPI 145 IRQ_TYPE_EDGE_RISING>,
	257	<GIC_SPI 146 IRQ_TYPE_EDGE_RISING>,
	258	<GIC_SPI 147 IRQ_TYPE_EDGE_RISING>,
	259	<GIC_SPI 148 IRQ_TYPE_EDGE_RISING>,
	260	<GIC_SPI 149 IRQ_TYPE_EDGE_RISING>,
	261	<GIC_SPI 150 IRQ_TYPE_EDGE_RISING>,
	262	<GIC_SPI 151 IRQ_TYPE_EDGE_RISING>;
	263	clocks = <&clkgpio>;
	264	clock-names = "gpio";
	265	ti,ngpio = <32>;
	266	ti,davinci-gpio-unbanked = <32>;
	267	};
82c04f71 IK	268
	269	aemif: aemif@21000A00 {
	270	compatible = "ti,keystone-aemif", "ti,davinci-aemif";
	271	#address-cells = <2>;
	272	#size-cells = <1>;
	273	clocks = <&clkaemif>;
	274	clock-names = "aemif";
	275	clock-ranges;
	276
	277	reg = <0x21000A00 0x00000100>;
	278	ranges = <0 0 0x30000000 0x10000000
	279	1 0 0x21000A00 0x00000100>;
	280	};
979c36c8	281
a392d42d GS	282	kirq0: keystone_irq@26202a0 {
	283	compatible = "ti,keystone-irq";
	284	interrupts = <GIC_SPI 4 IRQ_TYPE_EDGE_RISING>;
	285	interrupt-controller;
	286	#interrupt-cells = <1>;
	287	ti,syscon-dev = <&devctrl 0x2a0>;
	288	};
bed80507	289
8b4769cc	290	pcie0: pcie@21800000 {
bed80507 MK	291	compatible = "ti,keystone-pcie", "snps,dw-pcie";
	292	clocks = <&clkpcie>;
	293	clock-names = "pcie";
	294	#address-cells = <3>;
	295	#size-cells = <2>;
	296	reg = <0x21801000 0x2000>, <0x21800000 0x1000>, <0x02620128 4>;
59e13aac MK	297	ranges = <0x82000000 0 0x50000000 0x50000000
59e13aac MK	298	0 0x10000000>;
bed80507	299
9dd4f28f	300	status = "disabled";
bed80507 MK	301	device_type = "pci";
bed80507 MK	302	num-lanes = <2>;
59e13aac	303	bus-range = <0x00 0xff>;
bed80507	304
a9e5b20d MK	305	/* error interrupt */
a9e5b20d MK	306	interrupts = <GIC_SPI 38 IRQ_TYPE_EDGE_RISING>;
bed80507 MK	307	#interrupt-cells = <1>;
	308	interrupt-map-mask = <0 0 0 7>;
	309	interrupt-map = <0 0 0 1 &pcie_intc0 0>, /* INT A */
	310	<0 0 0 2 &pcie_intc0 1>, /* INT B */
	311	<0 0 0 3 &pcie_intc0 2>, /* INT C */
	312	<0 0 0 4 &pcie_intc0 3>; /* INT D */
	313
	314	pcie_msi_intc0: msi-interrupt-controller {
	315	interrupt-controller;
	316	#interrupt-cells = <1>;
	317	interrupt-parent = <&gic>;
	318	interrupts = <GIC_SPI 30 IRQ_TYPE_EDGE_RISING>,
	319	<GIC_SPI 31 IRQ_TYPE_EDGE_RISING>,
	320	<GIC_SPI 32 IRQ_TYPE_EDGE_RISING>,
	321	<GIC_SPI 33 IRQ_TYPE_EDGE_RISING>,
	322	<GIC_SPI 34 IRQ_TYPE_EDGE_RISING>,
	323	<GIC_SPI 35 IRQ_TYPE_EDGE_RISING>,
	324	<GIC_SPI 36 IRQ_TYPE_EDGE_RISING>,
	325	<GIC_SPI 37 IRQ_TYPE_EDGE_RISING>;
	326	};
	327
	328	pcie_intc0: legacy-interrupt-controller {
	329	interrupt-controller;
	330	#interrupt-cells = <1>;
	331	interrupt-parent = <&gic>;
	332	interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>,
	333	<GIC_SPI 27 IRQ_TYPE_EDGE_RISING>,
	334	<GIC_SPI 28 IRQ_TYPE_EDGE_RISING>,
	335	<GIC_SPI 29 IRQ_TYPE_EDGE_RISING>;
	336	};
	337	};
d5e9fe84 SS	338	};
d5e9fe84 SS	339	};