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bus: omap_l3_noc: Fix offset for DRA7 CLK1_HOST_CLK1_2 instance
[deliverable/linux.git] / arch / arm / boot / dts / omap5.dtsi
CommitLineData
6b5de091
S		 1/*
2 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 * Based on "omap4.dtsi"
8 */
9
6d624eab 10#include <dt-bindings/gpio/gpio.h>
8fea7d5a 11#include <dt-bindings/interrupt-controller/arm-gic.h>
bcd3cca7 12#include <dt-bindings/pinctrl/omap.h>
6b5de091 13
98ef7957 14#include "skeleton.dtsi"
6b5de091
S		 15
16/ {
ba1829bc
SS		 17 #address-cells = <1>;
18 #size-cells = <1>;
19
6b5de091 20 compatible = "ti,omap5";
7136d457 21 interrupt-parent = <&wakeupgen>;
6b5de091
S		 22
23 aliases {
20b80942
NM		 24 i2c0 = &i2c1;
25 i2c1 = &i2c2;
26 i2c2 = &i2c3;
27 i2c3 = &i2c4;
28 i2c4 = &i2c5;
6b5de091
S		 29 serial0 = &uart1;
30 serial1 = &uart2;
31 serial2 = &uart3;
32 serial3 = &uart4;
33 serial4 = &uart5;
34 serial5 = &uart6;
35 };
36
37 cpus {
eeb25fd5
LP		 38 #address-cells = <1>;
39 #size-cells = <0>;
40
b8981d71 41 cpu0: cpu@0 {
eeb25fd5 42 device_type = "cpu";
6b5de091 43 compatible = "arm,cortex-a15";
eeb25fd5 44 reg = <0x0>;
6c24894d
K		 45
46 operating-points = <
47 /* kHz uV */
6c24894d
K		 48 1000000 1060000
49 1500000 1250000
50 >;
8d766fa2
NM		 51
52 clocks = <&dpll_mpu_ck>;
53 clock-names = "cpu";
54
55 clock-latency = <300000>; /* From omap-cpufreq driver */
56
2cd29f63
EV		 57 /* cooling options */
58 cooling-min-level = <0>;
59 cooling-max-level = <2>;
60 #cooling-cells = <2>; /* min followed by max */
6b5de091
S		 61 };
62 cpu@1 {
eeb25fd5 63 device_type = "cpu";
6b5de091 64 compatible = "arm,cortex-a15";
eeb25fd5 65 reg = <0x1>;
6b5de091
S		 66 };
67 };
68
1b761fc5
EV		 69 thermal-zones {
70 #include "omap4-cpu-thermal.dtsi"
71 #include "omap5-gpu-thermal.dtsi"
72 #include "omap5-core-thermal.dtsi"
73 };
74
b45ccc4e
SS		 75 timer {
76 compatible = "arm,armv7-timer";
8fea7d5a
FV		 77 /* PPI secure/nonsecure IRQ */
78 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
79 <GIC_PPI 14 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
80 <GIC_PPI 11 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
81 <GIC_PPI 10 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>;
7136d457 82 interrupt-parent = <&gic>;
b45ccc4e
SS		 83 };
84
69a126cb
NL		 85 pmu {
86 compatible = "arm,cortex-a15-pmu";
87 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
88 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
89 };
90
ba1829bc
SS		 91 gic: interrupt-controller@48211000 {
92 compatible = "arm,cortex-a15-gic";
93 interrupt-controller;
94 #interrupt-cells = <3>;
95 reg = <0x48211000 0x1000>,
0129c16c
SS		 96 <0x48212000 0x1000>,
97 <0x48214000 0x2000>,
98 <0x48216000 0x2000>;
7136d457
MZ		 99 interrupt-parent = <&gic>;
100 };
101
102 wakeupgen: interrupt-controller@48281000 {
103 compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu";
104 interrupt-controller;
105 #interrupt-cells = <3>;
106 reg = <0x48281000 0x1000>;
107 interrupt-parent = <&gic>;
ba1829bc
SS		 108 };
109
6b5de091 110 /*
5c5be9db 111 * The soc node represents the soc top level view. It is used for IPs
6b5de091
S		 112 * that are not memory mapped in the MPU view or for the MPU itself.
113 */
114 soc {
115 compatible = "ti,omap-infra";
116 mpu {
1306c08a 117 compatible = "ti,omap4-mpu";
6b5de091 118 ti,hwmods = "mpu";
1306c08a 119 sram = <&ocmcram>;
6b5de091
S		 120 };
121 };
122
123 /*
124 * XXX: Use a flat representation of the OMAP3 interconnect.
125 * The real OMAP interconnect network is quite complex.
b7ab524b 126 * Since it will not bring real advantage to represent that in DT for
6b5de091
S		 127 * the moment, just use a fake OCP bus entry to represent the whole bus
128 * hierarchy.
129 */
130 ocp {
131 compatible = "ti,omap4-l3-noc", "simple-bus";
132 #address-cells = <1>;
133 #size-cells = <1>;
134 ranges;
135 ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
20a60eaa
SS		 136 reg = <0x44000000 0x2000>,
137 <0x44800000 0x3000>,
138 <0x45000000 0x4000>;
8fea7d5a
FV		 139 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
140 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
6b5de091 141
ed8509ed
TK		 142 l4_cfg: l4@4a000000 {
143 compatible = "ti,omap5-l4-cfg", "simple-bus";
144 #address-cells = <1>;
145 #size-cells = <1>;
146 ranges = <0 0x4a000000 0x22a000>;
85dc74e9 147
ed8509ed
TK		 148 scm_core: scm@2000 {
149 compatible = "ti,omap5-scm-core", "simple-bus";
150 reg = <0x2000 0x1000>;
85dc74e9 151 #address-cells = <1>;
ed8509ed
TK		 152 #size-cells = <1>;
153 ranges = <0 0x2000 0x800>;
154
155 scm_conf: scm_conf@0 {
156 compatible = "syscon";
157 reg = <0x0 0x800>;
158 #address-cells = <1>;
159 #size-cells = <1>;
160 };
85dc74e9
TK		 161 };
162
ed8509ed
TK		 163 scm_padconf_core: scm@2800 {
164 compatible = "ti,omap5-scm-padconf-core",
165 "simple-bus";
166 #address-cells = <1>;
167 #size-cells = <1>;
168 ranges = <0 0x2800 0x800>;
169
170 omap5_pmx_core: pinmux@40 {
171 compatible = "ti,omap5-padconf",
172 "pinctrl-single";
173 reg = <0x40 0x01b6>;
174 #address-cells = <1>;
175 #size-cells = <0>;
176 #interrupt-cells = <1>;
177 interrupt-controller;
178 pinctrl-single,register-width = <16>;
179 pinctrl-single,function-mask = <0x7fff>;
180 };
181
182 omap5_padconf_global: omap5_padconf_global@5a0 {
183 compatible = "syscon";
184 reg = <0x5a0 0xec>;
185 #address-cells = <1>;
186 #size-cells = <1>;
187
188 pbias_regulator: pbias_regulator {
189 compatible = "ti,pbias-omap";
190 reg = <0x60 0x4>;
191 syscon = <&omap5_padconf_global>;
192 pbias_mmc_reg: pbias_mmc_omap5 {
193 regulator-name = "pbias_mmc_omap5";
194 regulator-min-microvolt = <1800000>;
195 regulator-max-microvolt = <3000000>;
196 };
197 };
198 };
85dc74e9 199 };
85dc74e9 200
ed8509ed
TK		 201 cm_core_aon: cm_core_aon@4000 {
202 compatible = "ti,omap5-cm-core-aon";
203 reg = <0x4000 0x2000>;
85dc74e9 204
ed8509ed
TK		 205 cm_core_aon_clocks: clocks {
206 #address-cells = <1>;
207 #size-cells = <0>;
208 };
85dc74e9 209
ed8509ed
TK		 210 cm_core_aon_clockdomains: clockdomains {
211 };
85dc74e9 212 };
85dc74e9 213
ed8509ed
TK		 214 cm_core: cm_core@8000 {
215 compatible = "ti,omap5-cm-core";
216 reg = <0x8000 0x3000>;
85dc74e9 217
ed8509ed
TK		 218 cm_core_clocks: clocks {
219 #address-cells = <1>;
220 #size-cells = <0>;
221 };
85dc74e9 222
ed8509ed
TK		 223 cm_core_clockdomains: clockdomains {
224 };
85dc74e9
TK		 225 };
226 };
227
ed8509ed
TK		 228 l4_wkup: l4@4ae00000 {
229 compatible = "ti,omap5-l4-wkup", "simple-bus";
230 #address-cells = <1>;
231 #size-cells = <1>;
232 ranges = <0 0x4ae00000 0x2b000>;
85dc74e9 233
ed8509ed
TK		 234 counter32k: counter@4000 {
235 compatible = "ti,omap-counter32k";
236 reg = <0x4000 0x40>;
237 ti,hwmods = "counter_32k";
85dc74e9
TK		 238 };
239
ed8509ed
TK		 240 prm: prm@6000 {
241 compatible = "ti,omap5-prm";
242 reg = <0x6000 0x3000>;
243 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
244
245 prm_clocks: clocks {
246 #address-cells = <1>;
247 #size-cells = <0>;
248 };
249
250 prm_clockdomains: clockdomains {
251 };
85dc74e9 252 };
85dc74e9 253
ed8509ed
TK		 254 scrm: scrm@a000 {
255 compatible = "ti,omap5-scrm";
256 reg = <0xa000 0x2000>;
3b3132f7 257
ed8509ed
TK		 258 scrm_clocks: clocks {
259 #address-cells = <1>;
260 #size-cells = <0>;
261 };
5da6a2d5 262
ed8509ed
TK		 263 scrm_clockdomains: clockdomains {
264 };
265 };
cd042fe5 266
ed8509ed
TK		 267 omap5_pmx_wkup: pinmux@c840 {
268 compatible = "ti,omap5-padconf",
269 "pinctrl-single";
270 reg = <0xc840 0x0038>;
271 #address-cells = <1>;
272 #size-cells = <0>;
273 #interrupt-cells = <1>;
274 interrupt-controller;
275 pinctrl-single,register-width = <16>;
276 pinctrl-single,function-mask = <0x7fff>;
cd042fe5
B		 277 };
278 };
279
8b9a2810
RN		 280 ocmcram: ocmcram@40300000 {
281 compatible = "mmio-sram";
282 reg = <0x40300000 0x20000>; /* 128k */
283 };
284
2c2dc545
JH		 285 sdma: dma-controller@4a056000 {
286 compatible = "ti,omap4430-sdma";
287 reg = <0x4a056000 0x1000>;
8fea7d5a
FV		 288 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
289 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
290 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
291 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
2c2dc545 292 #dma-cells = <1>;
951c1c04
PU		 293 dma-channels = <32>;
294 dma-requests = <127>;
2c2dc545
JH		 295 };
296
6b5de091
S		 297 gpio1: gpio@4ae10000 {
298 compatible = "ti,omap4-gpio";
f4b224f2 299 reg = <0x4ae10000 0x200>;
8fea7d5a 300 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
6b5de091 301 ti,hwmods = "gpio1";
e4b9b9f3 302 ti,gpio-always-on;
6b5de091
S		 303 gpio-controller;
304 #gpio-cells = <2>;
305 interrupt-controller;
ff5c9059 306 #interrupt-cells = <2>;
6b5de091
S		 307 };
308
309 gpio2: gpio@48055000 {
310 compatible = "ti,omap4-gpio";
f4b224f2 311 reg = <0x48055000 0x200>;
8fea7d5a 312 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
6b5de091
S		 313 ti,hwmods = "gpio2";
314 gpio-controller;
315 #gpio-cells = <2>;
316 interrupt-controller;
ff5c9059 317 #interrupt-cells = <2>;
6b5de091
S		 318 };
319
320 gpio3: gpio@48057000 {
321 compatible = "ti,omap4-gpio";
f4b224f2 322 reg = <0x48057000 0x200>;
8fea7d5a 323 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
6b5de091
S		 324 ti,hwmods = "gpio3";
325 gpio-controller;
326 #gpio-cells = <2>;
327 interrupt-controller;
ff5c9059 328 #interrupt-cells = <2>;
6b5de091
S		 329 };
330
331 gpio4: gpio@48059000 {
332 compatible = "ti,omap4-gpio";
f4b224f2 333 reg = <0x48059000 0x200>;
8fea7d5a 334 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
6b5de091
S		 335 ti,hwmods = "gpio4";
336 gpio-controller;
337 #gpio-cells = <2>;
338 interrupt-controller;
ff5c9059 339 #interrupt-cells = <2>;
6b5de091
S		 340 };
341
342 gpio5: gpio@4805b000 {
343 compatible = "ti,omap4-gpio";
f4b224f2 344 reg = <0x4805b000 0x200>;
8fea7d5a 345 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
6b5de091
S		 346 ti,hwmods = "gpio5";
347 gpio-controller;
348 #gpio-cells = <2>;
349 interrupt-controller;
ff5c9059 350 #interrupt-cells = <2>;
6b5de091
S		 351 };
352
353 gpio6: gpio@4805d000 {
354 compatible = "ti,omap4-gpio";
f4b224f2 355 reg = <0x4805d000 0x200>;
8fea7d5a 356 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
6b5de091
S		 357 ti,hwmods = "gpio6";
358 gpio-controller;
359 #gpio-cells = <2>;
360 interrupt-controller;
ff5c9059 361 #interrupt-cells = <2>;
6b5de091
S		 362 };
363
364 gpio7: gpio@48051000 {
365 compatible = "ti,omap4-gpio";
f4b224f2 366 reg = <0x48051000 0x200>;
8fea7d5a 367 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
6b5de091
S		 368 ti,hwmods = "gpio7";
369 gpio-controller;
370 #gpio-cells = <2>;
371 interrupt-controller;
ff5c9059 372 #interrupt-cells = <2>;
6b5de091
S		 373 };
374
375 gpio8: gpio@48053000 {
376 compatible = "ti,omap4-gpio";
f4b224f2 377 reg = <0x48053000 0x200>;
8fea7d5a 378 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
6b5de091
S		 379 ti,hwmods = "gpio8";
380 gpio-controller;
381 #gpio-cells = <2>;
382 interrupt-controller;
ff5c9059 383 #interrupt-cells = <2>;
6b5de091
S		 384 };
385
1c7dbb55
JH		 386 gpmc: gpmc@50000000 {
387 compatible = "ti,omap4430-gpmc";
388 reg = <0x50000000 0x1000>;
389 #address-cells = <2>;
390 #size-cells = <1>;
8fea7d5a 391 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
1c7dbb55
JH		 392 gpmc,num-cs = <8>;
393 gpmc,num-waitpins = <4>;
394 ti,hwmods = "gpmc";
7b8b6af1
FV		 395 clocks = <&l3_iclk_div>;
396 clock-names = "fck";
1c7dbb55
JH		 397 };
398
6e6a9a50
SP		 399 i2c1: i2c@48070000 {
400 compatible = "ti,omap4-i2c";
d7118bbd 401 reg = <0x48070000 0x100>;
8fea7d5a 402 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
6e6a9a50
SP		 403 #address-cells = <1>;
404 #size-cells = <0>;
405 ti,hwmods = "i2c1";
406 };
407
408 i2c2: i2c@48072000 {
409 compatible = "ti,omap4-i2c";
d7118bbd 410 reg = <0x48072000 0x100>;
8fea7d5a 411 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
6e6a9a50
SP		 412 #address-cells = <1>;
413 #size-cells = <0>;
414 ti,hwmods = "i2c2";
415 };
416
417 i2c3: i2c@48060000 {
418 compatible = "ti,omap4-i2c";
d7118bbd 419 reg = <0x48060000 0x100>;
8fea7d5a 420 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
6e6a9a50
SP		 421 #address-cells = <1>;
422 #size-cells = <0>;
423 ti,hwmods = "i2c3";
424 };
425
d7118bbd 426 i2c4: i2c@4807a000 {
6e6a9a50 427 compatible = "ti,omap4-i2c";
d7118bbd 428 reg = <0x4807a000 0x100>;
8fea7d5a 429 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
6e6a9a50
SP		 430 #address-cells = <1>;
431 #size-cells = <0>;
432 ti,hwmods = "i2c4";
433 };
434
d7118bbd 435 i2c5: i2c@4807c000 {
6e6a9a50 436 compatible = "ti,omap4-i2c";
d7118bbd 437 reg = <0x4807c000 0x100>;
8fea7d5a 438 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
6e6a9a50
SP		 439 #address-cells = <1>;
440 #size-cells = <0>;
441 ti,hwmods = "i2c5";
442 };
443
fe0e09e4
SA		 444 hwspinlock: spinlock@4a0f6000 {
445 compatible = "ti,omap4-hwspinlock";
446 reg = <0x4a0f6000 0x1000>;
447 ti,hwmods = "spinlock";
34054213 448 #hwlock-cells = <1>;
fe0e09e4
SA		 449 };
450
43286b11
FB		 451 mcspi1: spi@48098000 {
452 compatible = "ti,omap4-mcspi";
453 reg = <0x48098000 0x200>;
8fea7d5a 454 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
43286b11
FB		 455 #address-cells = <1>;
456 #size-cells = <0>;
457 ti,hwmods = "mcspi1";
458 ti,spi-num-cs = <4>;
2c2dc545
JH		 459 dmas = <&sdma 35>,
460 <&sdma 36>,
461 <&sdma 37>,
462 <&sdma 38>,
463 <&sdma 39>,
464 <&sdma 40>,
465 <&sdma 41>,
466 <&sdma 42>;
467 dma-names = "tx0", "rx0", "tx1", "rx1",
468 "tx2", "rx2", "tx3", "rx3";
43286b11
FB		 469 };
470
471 mcspi2: spi@4809a000 {
472 compatible = "ti,omap4-mcspi";
473 reg = <0x4809a000 0x200>;
8fea7d5a 474 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
43286b11
FB		 475 #address-cells = <1>;
476 #size-cells = <0>;
477 ti,hwmods = "mcspi2";
478 ti,spi-num-cs = <2>;
2c2dc545
JH		 479 dmas = <&sdma 43>,
480 <&sdma 44>,
481 <&sdma 45>,
482 <&sdma 46>;
483 dma-names = "tx0", "rx0", "tx1", "rx1";
43286b11
FB		 484 };
485
486 mcspi3: spi@480b8000 {
487 compatible = "ti,omap4-mcspi";
488 reg = <0x480b8000 0x200>;
8fea7d5a 489 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
43286b11
FB		 490 #address-cells = <1>;
491 #size-cells = <0>;
492 ti,hwmods = "mcspi3";
493 ti,spi-num-cs = <2>;
2c2dc545
JH		 494 dmas = <&sdma 15>, <&sdma 16>;
495 dma-names = "tx0", "rx0";
43286b11
FB		 496 };
497
498 mcspi4: spi@480ba000 {
499 compatible = "ti,omap4-mcspi";
500 reg = <0x480ba000 0x200>;
8fea7d5a 501 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
43286b11
FB		 502 #address-cells = <1>;
503 #size-cells = <0>;
504 ti,hwmods = "mcspi4";
505 ti,spi-num-cs = <1>;
2c2dc545
JH		 506 dmas = <&sdma 70>, <&sdma 71>;
507 dma-names = "tx0", "rx0";
43286b11
FB		 508 };
509
6b5de091
S		 510 uart1: serial@4806a000 {
511 compatible = "ti,omap4-uart";
8e80f660 512 reg = <0x4806a000 0x100>;
7136d457 513 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
6b5de091
S		 514 ti,hwmods = "uart1";
515 clock-frequency = <48000000>;
516 };
517
518 uart2: serial@4806c000 {
519 compatible = "ti,omap4-uart";
8e80f660 520 reg = <0x4806c000 0x100>;
7136d457 521 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
6b5de091
S		 522 ti,hwmods = "uart2";
523 clock-frequency = <48000000>;
524 };
525
526 uart3: serial@48020000 {
527 compatible = "ti,omap4-uart";
8e80f660 528 reg = <0x48020000 0x100>;
7136d457 529 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
6b5de091
S		 530 ti,hwmods = "uart3";
531 clock-frequency = <48000000>;
532 };
533
534 uart4: serial@4806e000 {
535 compatible = "ti,omap4-uart";
8e80f660 536 reg = <0x4806e000 0x100>;
7136d457 537 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
6b5de091
S		 538 ti,hwmods = "uart4";
539 clock-frequency = <48000000>;
540 };
541
542 uart5: serial@48066000 {
8e80f660
SG		 543 compatible = "ti,omap4-uart";
544 reg = <0x48066000 0x100>;
7136d457 545 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
6b5de091
S		 546 ti,hwmods = "uart5";
547 clock-frequency = <48000000>;
548 };
549
550 uart6: serial@48068000 {
8e80f660
SG		 551 compatible = "ti,omap4-uart";
552 reg = <0x48068000 0x100>;
7136d457 553 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
6b5de091
S		 554 ti,hwmods = "uart6";
555 clock-frequency = <48000000>;
556 };
5dd18b01
B		 557
558 mmc1: mmc@4809c000 {
559 compatible = "ti,omap4-hsmmc";
9a642362 560 reg = <0x4809c000 0x400>;
8fea7d5a 561 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
5dd18b01
B		 562 ti,hwmods = "mmc1";
563 ti,dual-volt;
564 ti,needs-special-reset;
2c2dc545
JH		 565 dmas = <&sdma 61>, <&sdma 62>;
566 dma-names = "tx", "rx";
cd042fe5 567 pbias-supply = <&pbias_mmc_reg>;
5dd18b01
B		 568 };
569
570 mmc2: mmc@480b4000 {
571 compatible = "ti,omap4-hsmmc";
9a642362 572 reg = <0x480b4000 0x400>;
8fea7d5a 573 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
5dd18b01
B		 574 ti,hwmods = "mmc2";
575 ti,needs-special-reset;
2c2dc545
JH		 576 dmas = <&sdma 47>, <&sdma 48>;
577 dma-names = "tx", "rx";
5dd18b01
B		 578 };
579
580 mmc3: mmc@480ad000 {
581 compatible = "ti,omap4-hsmmc";
9a642362 582 reg = <0x480ad000 0x400>;
8fea7d5a 583 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
5dd18b01
B		 584 ti,hwmods = "mmc3";
585 ti,needs-special-reset;
2c2dc545
JH		 586 dmas = <&sdma 77>, <&sdma 78>;
587 dma-names = "tx", "rx";
5dd18b01
B		 588 };
589
590 mmc4: mmc@480d1000 {
591 compatible = "ti,omap4-hsmmc";
9a642362 592 reg = <0x480d1000 0x400>;
8fea7d5a 593 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
5dd18b01
B		 594 ti,hwmods = "mmc4";
595 ti,needs-special-reset;
2c2dc545
JH		 596 dmas = <&sdma 57>, <&sdma 58>;
597 dma-names = "tx", "rx";
5dd18b01
B		 598 };
599
600 mmc5: mmc@480d5000 {
601 compatible = "ti,omap4-hsmmc";
9a642362 602 reg = <0x480d5000 0x400>;
8fea7d5a 603 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
5dd18b01
B		 604 ti,hwmods = "mmc5";
605 ti,needs-special-reset;
2c2dc545
JH		 606 dmas = <&sdma 59>, <&sdma 60>;
607 dma-names = "tx", "rx";
5dd18b01 608 };
5449fbc2 609
2dcfa56e
SA		 610 mmu_dsp: mmu@4a066000 {
611 compatible = "ti,omap4-iommu";
612 reg = <0x4a066000 0x100>;
613 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
614 ti,hwmods = "mmu_dsp";
615 };
616
617 mmu_ipu: mmu@55082000 {
618 compatible = "ti,omap4-iommu";
619 reg = <0x55082000 0x100>;
620 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
621 ti,hwmods = "mmu_ipu";
622 ti,iommu-bus-err-back;
623 };
624
5449fbc2
SP		 625 keypad: keypad@4ae1c000 {
626 compatible = "ti,omap4-keypad";
8cc8b89f 627 reg = <0x4ae1c000 0x400>;
5449fbc2
SP		 628 ti,hwmods = "kbd";
629 };
ffd5db24 630
cbb57f07
PU		 631 mcpdm: mcpdm@40132000 {
632 compatible = "ti,omap4-mcpdm";
633 reg = <0x40132000 0x7f>, /* MPU private access */
634 <0x49032000 0x7f>; /* L3 Interconnect */
635 reg-names = "mpu", "dma";
8fea7d5a 636 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
cbb57f07 637 ti,hwmods = "mcpdm";
4e4ead73
SG		 638 dmas = <&sdma 65>,
639 <&sdma 66>;
640 dma-names = "up_link", "dn_link";
f15534ea 641 status = "disabled";
cbb57f07
PU		 642 };
643
644 dmic: dmic@4012e000 {
645 compatible = "ti,omap4-dmic";
646 reg = <0x4012e000 0x7f>, /* MPU private access */
647 <0x4902e000 0x7f>; /* L3 Interconnect */
648 reg-names = "mpu", "dma";
8fea7d5a 649 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
cbb57f07 650 ti,hwmods = "dmic";
4e4ead73
SG		 651 dmas = <&sdma 67>;
652 dma-names = "up_link";
f15534ea 653 status = "disabled";
cbb57f07
PU		 654 };
655
ffd5db24
PU		 656 mcbsp1: mcbsp@40122000 {
657 compatible = "ti,omap4-mcbsp";
658 reg = <0x40122000 0xff>, /* MPU private access */
659 <0x49022000 0xff>; /* L3 Interconnect */
660 reg-names = "mpu", "dma";
8fea7d5a 661 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
ffd5db24 662 interrupt-names = "common";
ffd5db24
PU		 663 ti,buffer-size = <128>;
664 ti,hwmods = "mcbsp1";
4e4ead73
SG		 665 dmas = <&sdma 33>,
666 <&sdma 34>;
667 dma-names = "tx", "rx";
f15534ea 668 status = "disabled";
ffd5db24
PU		 669 };
670
671 mcbsp2: mcbsp@40124000 {
672 compatible = "ti,omap4-mcbsp";
673 reg = <0x40124000 0xff>, /* MPU private access */
674 <0x49024000 0xff>; /* L3 Interconnect */
675 reg-names = "mpu", "dma";
8fea7d5a 676 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
ffd5db24 677 interrupt-names = "common";
ffd5db24
PU		 678 ti,buffer-size = <128>;
679 ti,hwmods = "mcbsp2";
4e4ead73
SG		 680 dmas = <&sdma 17>,
681 <&sdma 18>;
682 dma-names = "tx", "rx";
f15534ea 683 status = "disabled";
ffd5db24
PU		 684 };
685
686 mcbsp3: mcbsp@40126000 {
687 compatible = "ti,omap4-mcbsp";
688 reg = <0x40126000 0xff>, /* MPU private access */
689 <0x49026000 0xff>; /* L3 Interconnect */
690 reg-names = "mpu", "dma";
8fea7d5a 691 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
ffd5db24 692 interrupt-names = "common";
ffd5db24
PU		 693 ti,buffer-size = <128>;
694 ti,hwmods = "mcbsp3";
4e4ead73
SG		 695 dmas = <&sdma 19>,
696 <&sdma 20>;
697 dma-names = "tx", "rx";
f15534ea 698 status = "disabled";
ffd5db24 699 };
df692a92 700
84d89c31
SA		 701 mailbox: mailbox@4a0f4000 {
702 compatible = "ti,omap4-mailbox";
703 reg = <0x4a0f4000 0x200>;
704 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
705 ti,hwmods = "mailbox";
24df0453 706 #mbox-cells = <1>;
41ffada1
SA		 707 ti,mbox-num-users = <3>;
708 ti,mbox-num-fifos = <8>;
d27704d1
SA		 709 mbox_ipu: mbox_ipu {
710 ti,mbox-tx = <0 0 0>;
711 ti,mbox-rx = <1 0 0>;
712 };
713 mbox_dsp: mbox_dsp {
714 ti,mbox-tx = <3 0 0>;
715 ti,mbox-rx = <2 0 0>;
716 };
84d89c31
SA		 717 };
718
df692a92 719 timer1: timer@4ae18000 {
002e1ec5 720 compatible = "ti,omap5430-timer";
df692a92 721 reg = <0x4ae18000 0x80>;
8fea7d5a 722 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
df692a92
JH		 723 ti,hwmods = "timer1";
724 ti,timer-alwon;
725 };
726
727 timer2: timer@48032000 {
002e1ec5 728 compatible = "ti,omap5430-timer";
df692a92 729 reg = <0x48032000 0x80>;
8fea7d5a 730 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
df692a92
JH		 731 ti,hwmods = "timer2";
732 };
733
734 timer3: timer@48034000 {
002e1ec5 735 compatible = "ti,omap5430-timer";
df692a92 736 reg = <0x48034000 0x80>;
8fea7d5a 737 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
df692a92
JH		 738 ti,hwmods = "timer3";
739 };
740
741 timer4: timer@48036000 {
002e1ec5 742 compatible = "ti,omap5430-timer";
df692a92 743 reg = <0x48036000 0x80>;
8fea7d5a 744 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
df692a92
JH		 745 ti,hwmods = "timer4";
746 };
747
748 timer5: timer@40138000 {
002e1ec5 749 compatible = "ti,omap5430-timer";
df692a92
JH		 750 reg = <0x40138000 0x80>,
751 <0x49038000 0x80>;
8fea7d5a 752 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
df692a92
JH		 753 ti,hwmods = "timer5";
754 ti,timer-dsp;
8341613a 755 ti,timer-pwm;
df692a92
JH		 756 };
757
758 timer6: timer@4013a000 {
002e1ec5 759 compatible = "ti,omap5430-timer";
df692a92
JH		 760 reg = <0x4013a000 0x80>,
761 <0x4903a000 0x80>;
8fea7d5a 762 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
df692a92
JH		 763 ti,hwmods = "timer6";
764 ti,timer-dsp;
765 ti,timer-pwm;
766 };
767
768 timer7: timer@4013c000 {
002e1ec5 769 compatible = "ti,omap5430-timer";
df692a92
JH		 770 reg = <0x4013c000 0x80>,
771 <0x4903c000 0x80>;
8fea7d5a 772 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
df692a92
JH		 773 ti,hwmods = "timer7";
774 ti,timer-dsp;
775 };
776
777 timer8: timer@4013e000 {
002e1ec5 778 compatible = "ti,omap5430-timer";
df692a92
JH		 779 reg = <0x4013e000 0x80>,
780 <0x4903e000 0x80>;
8fea7d5a 781 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
df692a92
JH		 782 ti,hwmods = "timer8";
783 ti,timer-dsp;
784 ti,timer-pwm;
785 };
786
787 timer9: timer@4803e000 {
002e1ec5 788 compatible = "ti,omap5430-timer";
df692a92 789 reg = <0x4803e000 0x80>;
8fea7d5a 790 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
df692a92 791 ti,hwmods = "timer9";
8341613a 792 ti,timer-pwm;
df692a92
JH		 793 };
794
795 timer10: timer@48086000 {
002e1ec5 796 compatible = "ti,omap5430-timer";
df692a92 797 reg = <0x48086000 0x80>;
8fea7d5a 798 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
df692a92 799 ti,hwmods = "timer10";
8341613a 800 ti,timer-pwm;
df692a92
JH		 801 };
802
803 timer11: timer@48088000 {
002e1ec5 804 compatible = "ti,omap5430-timer";
df692a92 805 reg = <0x48088000 0x80>;
8fea7d5a 806 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
df692a92
JH		 807 ti,hwmods = "timer11";
808 ti,timer-pwm;
809 };
e6900ddf 810
55452197
LV		 811 wdt2: wdt@4ae14000 {
812 compatible = "ti,omap5-wdt", "ti,omap3-wdt";
813 reg = <0x4ae14000 0x80>;
8fea7d5a 814 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
55452197
LV		 815 ti,hwmods = "wd_timer2";
816 };
817
1a5fe3ca
AT		 818 dmm@4e000000 {
819 compatible = "ti,omap5-dmm";
820 reg = <0x4e000000 0x800>;
821 interrupts = <0 113 0x4>;
822 ti,hwmods = "dmm";
823 };
824
8906d654 825 emif1: emif@4c000000 {
e6900ddf
LV		 826 compatible = "ti,emif-4d5";
827 ti,hwmods = "emif1";
f12ecbe2 828 ti,no-idle-on-init;
e6900ddf
LV		 829 phy-type = <2>; /* DDR PHY type: Intelli PHY */
830 reg = <0x4c000000 0x400>;
8fea7d5a 831 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
e6900ddf
LV		 832 hw-caps-read-idle-ctrl;
833 hw-caps-ll-interface;
834 hw-caps-temp-alert;
835 };
836
8906d654 837 emif2: emif@4d000000 {
e6900ddf
LV		 838 compatible = "ti,emif-4d5";
839 ti,hwmods = "emif2";
f12ecbe2 840 ti,no-idle-on-init;
e6900ddf
LV		 841 phy-type = <2>; /* DDR PHY type: Intelli PHY */
842 reg = <0x4d000000 0x400>;
8fea7d5a 843 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
e6900ddf
LV		 844 hw-caps-read-idle-ctrl;
845 hw-caps-ll-interface;
846 hw-caps-temp-alert;
847 };
fedc428e 848
b297c292
RQ		 849 omap_control_usb2phy: control-phy@4a002300 {
850 compatible = "ti,control-phy-usb2";
851 reg = <0x4a002300 0x4>;
852 reg-names = "power";
853 };
854
855 omap_control_usb3phy: control-phy@4a002370 {
856 compatible = "ti,control-phy-pipe3";
857 reg = <0x4a002370 0x4>;
858 reg-names = "power";
fedc428e 859 };
e9831967 860
e3a412c9 861 usb3: omap_dwc3@4a020000 {
72f6f957
KVA		 862 compatible = "ti,dwc3";
863 ti,hwmods = "usb_otg_ss";
6f61ee23 864 reg = <0x4a020000 0x10000>;
8fea7d5a 865 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
72f6f957
KVA		 866 #address-cells = <1>;
867 #size-cells = <1>;
868 utmi-mode = <2>;
869 ranges;
870 dwc3@4a030000 {
22a5aa17 871 compatible = "snps,dwc3";
6f61ee23 872 reg = <0x4a030000 0x10000>;
8fea7d5a 873 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
073addc8
KVA		 874 phys = <&usb2_phy>, <&usb3_phy>;
875 phy-names = "usb2-phy", "usb3-phy";
c47ee6ee 876 dr_mode = "peripheral";
72f6f957
KVA		 877 tx-fifo-resize;
878 };
879 };
880
b6731f78 881 ocp2scp@4a080000 {
e9831967
KVA		 882 compatible = "ti,omap-ocp2scp";
883 #address-cells = <1>;
884 #size-cells = <1>;
b6731f78 885 reg = <0x4a080000 0x20>;
e9831967
KVA		 886 ranges;
887 ti,hwmods = "ocp2scp1";
ae6a32d2
KVA		 888 usb2_phy: usb2phy@4a084000 {
889 compatible = "ti,omap-usb2";
890 reg = <0x4a084000 0x7c>;
b297c292 891 ctrl-module = <&omap_control_usb2phy>;
c65d0ad5
RQ		 892 clocks = <&usb_phy_cm_clk32k>, <&usb_otg_ss_refclk960m>;
893 clock-names = "wkupclk", "refclk";
073addc8 894 #phy-cells = <0>;
ae6a32d2
KVA		 895 };
896
897 usb3_phy: usb3phy@4a084400 {
898 compatible = "ti,omap-usb3";
899 reg = <0x4a084400 0x80>,
900 <0x4a084800 0x64>,
901 <0x4a084c00 0x40>;
902 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
b297c292 903 ctrl-module = <&omap_control_usb3phy>;
ada76576
RQ		 904 clocks = <&usb_phy_cm_clk32k>,
905 <&sys_clkin>,
906 <&usb_otg_ss_refclk960m>;
907 clock-names = "wkupclk",
908 "sysclk",
909 "refclk";
073addc8 910 #phy-cells = <0>;
ae6a32d2 911 };
e9831967 912 };
ed7f8e8a
RQ		 913
914 usbhstll: usbhstll@4a062000 {
915 compatible = "ti,usbhs-tll";
916 reg = <0x4a062000 0x1000>;
917 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
918 ti,hwmods = "usb_tll_hs";
919 };
920
921 usbhshost: usbhshost@4a064000 {
922 compatible = "ti,usbhs-host";
923 reg = <0x4a064000 0x800>;
924 ti,hwmods = "usb_host_hs";
925 #address-cells = <1>;
926 #size-cells = <1>;
927 ranges;
051fc06d
RQ		 928 clocks = <&l3init_60m_fclk>,
929 <&xclk60mhsp1_ck>,
930 <&xclk60mhsp2_ck>;
931 clock-names = "refclk_60m_int",
932 "refclk_60m_ext_p1",
933 "refclk_60m_ext_p2";
ed7f8e8a
RQ		 934
935 usbhsohci: ohci@4a064800 {
a2525e54 936 compatible = "ti,ohci-omap3";
ed7f8e8a 937 reg = <0x4a064800 0x400>;
ed7f8e8a
RQ		 938 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
939 };
940
941 usbhsehci: ehci@4a064c00 {
a2525e54 942 compatible = "ti,ehci-omap";
ed7f8e8a 943 reg = <0x4a064c00 0x400>;
ed7f8e8a
RQ		 944 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
945 };
946 };
cbad26db 947
1b761fc5 948 bandgap: bandgap@4a0021e0 {
cbad26db
EV		 949 reg = <0x4a0021e0 0xc
950 0x4a00232c 0xc
951 0x4a002380 0x2c
952 0x4a0023C0 0x3c>;
953 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
954 compatible = "ti,omap5430-bandgap";
1b761fc5
EV		 955
956 #thermal-sensor-cells = <1>;
cbad26db 957 };
4f82952c
B		 958
959 omap_control_sata: control-phy@4a002374 {
960 compatible = "ti,control-phy-pipe3";
961 reg = <0x4a002374 0x4>;
962 reg-names = "power";
963 clocks = <&sys_clkin>;
964 clock-names = "sysclk";
965 };
966
967 /* OCP2SCP3 */
968 ocp2scp@4a090000 {
969 compatible = "ti,omap-ocp2scp";
970 #address-cells = <1>;
971 #size-cells = <1>;
972 reg = <0x4a090000 0x20>;
973 ranges;
974 ti,hwmods = "ocp2scp3";
975 sata_phy: phy@4a096000 {
976 compatible = "ti,phy-pipe3-sata";
977 reg = <0x4A096000 0x80>, /* phy_rx */
978 <0x4A096400 0x64>, /* phy_tx */
979 <0x4A096800 0x40>; /* pll_ctrl */
980 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
981 ctrl-module = <&omap_control_sata>;
a0182724
RQ		 982 clocks = <&sys_clkin>, <&sata_ref_clk>;
983 clock-names = "sysclk", "refclk";
4f82952c
B		 984 #phy-cells = <0>;
985 };
986 };
987
988 sata: sata@4a141100 {
989 compatible = "snps,dwc-ahci";
990 reg = <0x4a140000 0x1100>, <0x4a141100 0x7>;
991 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
992 phys = <&sata_phy>;
993 phy-names = "sata-phy";
994 clocks = <&sata_ref_clk>;
995 ti,hwmods = "sata";
996 };
997
e7585c4f
TV		 998 dss: dss@58000000 {
999 compatible = "ti,omap5-dss";
1000 reg = <0x58000000 0x80>;
1001 status = "disabled";
1002 ti,hwmods = "dss_core";
1003 clocks = <&dss_dss_clk>;
1004 clock-names = "fck";
1005 #address-cells = <1>;
1006 #size-cells = <1>;
1007 ranges;
1008
1009 dispc@58001000 {
1010 compatible = "ti,omap5-dispc";
1011 reg = <0x58001000 0x1000>;
1012 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
1013 ti,hwmods = "dss_dispc";
1014 clocks = <&dss_dss_clk>;
1015 clock-names = "fck";
1016 };
1017
84ace674
TV		 1018 rfbi: encoder@58002000 {
1019 compatible = "ti,omap5-rfbi";
1020 reg = <0x58002000 0x100>;
1021 status = "disabled";
1022 ti,hwmods = "dss_rfbi";
1023 clocks = <&dss_dss_clk>, <&l3_iclk_div>;
1024 clock-names = "fck", "ick";
1025 };
1026
e7585c4f
TV		 1027 dsi1: encoder@58004000 {
1028 compatible = "ti,omap5-dsi";
1029 reg = <0x58004000 0x200>,
1030 <0x58004200 0x40>,
1031 <0x58004300 0x40>;
1032 reg-names = "proto", "phy", "pll";
1033 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
1034 status = "disabled";
1035 ti,hwmods = "dss_dsi1";
1036 clocks = <&dss_dss_clk>, <&dss_sys_clk>;
1037 clock-names = "fck", "sys_clk";
1038 };
1039
1040 dsi2: encoder@58005000 {
1041 compatible = "ti,omap5-dsi";
1042 reg = <0x58009000 0x200>,
1043 <0x58009200 0x40>,
1044 <0x58009300 0x40>;
1045 reg-names = "proto", "phy", "pll";
1046 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
1047 status = "disabled";
1048 ti,hwmods = "dss_dsi2";
1049 clocks = <&dss_dss_clk>, <&dss_sys_clk>;
1050 clock-names = "fck", "sys_clk";
1051 };
1052
1053 hdmi: encoder@58060000 {
1054 compatible = "ti,omap5-hdmi";
1055 reg = <0x58040000 0x200>,
1056 <0x58040200 0x80>,
1057 <0x58040300 0x80>,
1058 <0x58060000 0x19000>;
1059 reg-names = "wp", "pll", "phy", "core";
1060 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1061 status = "disabled";
1062 ti,hwmods = "dss_hdmi";
1063 clocks = <&dss_48mhz_clk>, <&dss_sys_clk>;
1064 clock-names = "fck", "sys_clk";
7d0fde39
JS		 1065 dmas = <&sdma 76>;
1066 dma-names = "audio_tx";
e7585c4f
TV		 1067 };
1068 };
07b9b3d9
AT		 1069
1070 abb_mpu: regulator-abb-mpu {
1071 compatible = "ti,abb-v2";
1072 regulator-name = "abb_mpu";
1073 #address-cells = <0>;
1074 #size-cells = <0>;
1075 clocks = <&sys_clkin>;
1076 ti,settling-time = <50>;
1077 ti,clock-cycles = <16>;
1078
1079 reg = <0x4ae07cdc 0x8>, <0x4ae06014 0x4>,
1080 <0x4a0021c4 0x8>, <0x4ae0c318 0x4>;
1081 reg-names = "base-address", "int-address",
1082 "efuse-address", "ldo-address";
1083 ti,tranxdone-status-mask = <0x80>;
1084 /* LDOVBBMPU_MUX_CTRL */
1085 ti,ldovbb-override-mask = <0x400>;
1086 /* LDOVBBMPU_VSET_OUT */
1087 ti,ldovbb-vset-mask = <0x1F>;
1088
1089 /*
1090 * NOTE: only FBB mode used but actual vset will
1091 * determine final biasing
1092 */
1093 ti,abb_info = <
1094 /*uV ABB efuse rbb_m fbb_m vset_m*/
1095 1060000 0 0x0 0 0x02000000 0x01F00000
1096 1250000 0 0x4 0 0x02000000 0x01F00000
1097 >;
1098 };
1099
1100 abb_mm: regulator-abb-mm {
1101 compatible = "ti,abb-v2";
1102 regulator-name = "abb_mm";
1103 #address-cells = <0>;
1104 #size-cells = <0>;
1105 clocks = <&sys_clkin>;
1106 ti,settling-time = <50>;
1107 ti,clock-cycles = <16>;
1108
1109 reg = <0x4ae07ce4 0x8>, <0x4ae06010 0x4>,
1110 <0x4a0021a4 0x8>, <0x4ae0c314 0x4>;
1111 reg-names = "base-address", "int-address",
1112 "efuse-address", "ldo-address";
1113 ti,tranxdone-status-mask = <0x80000000>;
1114 /* LDOVBBMM_MUX_CTRL */
1115 ti,ldovbb-override-mask = <0x400>;
1116 /* LDOVBBMM_VSET_OUT */
1117 ti,ldovbb-vset-mask = <0x1F>;
1118
1119 /*
1120 * NOTE: only FBB mode used but actual vset will
1121 * determine final biasing
1122 */
1123 ti,abb_info = <
1124 /*uV ABB efuse rbb_m fbb_m vset_m*/
1125 1025000 0 0x0 0 0x02000000 0x01F00000
1126 1120000 0 0x4 0 0x02000000 0x01F00000
1127 >;
1128 };
6b5de091
S		 1129 };
1130};
85dc74e9 1131
38f5c8ba
TK		 1132&cpu_thermal {
1133 polling-delay = <500>; /* milliseconds */
1134};
1135
85dc74e9 1136/include/ "omap54xx-clocks.dtsi"
Linux kernel - Deliverables
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