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Merge remote-tracking branch 'spi/for-next'
[deliverable/linux.git] / arch / arm / boot / dts / omap5.dtsi
CommitLineData
6b5de091
S		 1/*
2 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 * Based on "omap4.dtsi"
8 */
9
6d624eab 10#include <dt-bindings/gpio/gpio.h>
8fea7d5a 11#include <dt-bindings/interrupt-controller/arm-gic.h>
bcd3cca7 12#include <dt-bindings/pinctrl/omap.h>
6b5de091 13
6b5de091 14/ {
ba1829bc
SS		 15 #address-cells = <1>;
16 #size-cells = <1>;
17
6b5de091 18 compatible = "ti,omap5";
7136d457 19 interrupt-parent = <&wakeupgen>;
6b5de091
S		 20
21 aliases {
20b80942
NM		 22 i2c0 = &i2c1;
23 i2c1 = &i2c2;
24 i2c2 = &i2c3;
25 i2c3 = &i2c4;
26 i2c4 = &i2c5;
6b5de091
S		 27 serial0 = &uart1;
28 serial1 = &uart2;
29 serial2 = &uart3;
30 serial3 = &uart4;
31 serial4 = &uart5;
32 serial5 = &uart6;
33 };
34
35 cpus {
eeb25fd5
LP		 36 #address-cells = <1>;
37 #size-cells = <0>;
38
b8981d71 39 cpu0: cpu@0 {
eeb25fd5 40 device_type = "cpu";
6b5de091 41 compatible = "arm,cortex-a15";
eeb25fd5 42 reg = <0x0>;
6c24894d
K		 43
44 operating-points = <
45 /* kHz uV */
6c24894d
K		 46 1000000 1060000
47 1500000 1250000
48 >;
8d766fa2
NM		 49
50 clocks = <&dpll_mpu_ck>;
51 clock-names = "cpu";
52
53 clock-latency = <300000>; /* From omap-cpufreq driver */
54
2cd29f63
EV		 55 /* cooling options */
56 cooling-min-level = <0>;
57 cooling-max-level = <2>;
58 #cooling-cells = <2>; /* min followed by max */
6b5de091
S		 59 };
60 cpu@1 {
eeb25fd5 61 device_type = "cpu";
6b5de091 62 compatible = "arm,cortex-a15";
eeb25fd5 63 reg = <0x1>;
6b5de091
S		 64 };
65 };
66
1b761fc5
EV		 67 thermal-zones {
68 #include "omap4-cpu-thermal.dtsi"
69 #include "omap5-gpu-thermal.dtsi"
70 #include "omap5-core-thermal.dtsi"
71 };
72
b45ccc4e
SS		 73 timer {
74 compatible = "arm,armv7-timer";
8fea7d5a
FV		 75 /* PPI secure/nonsecure IRQ */
76 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
77 <GIC_PPI 14 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
78 <GIC_PPI 11 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
79 <GIC_PPI 10 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>;
7136d457 80 interrupt-parent = <&gic>;
b45ccc4e
SS		 81 };
82
69a126cb
NL		 83 pmu {
84 compatible = "arm,cortex-a15-pmu";
85 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
86 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
87 };
88
ba1829bc
SS		 89 gic: interrupt-controller@48211000 {
90 compatible = "arm,cortex-a15-gic";
91 interrupt-controller;
92 #interrupt-cells = <3>;
93 reg = <0x48211000 0x1000>,
0129c16c
SS		 94 <0x48212000 0x1000>,
95 <0x48214000 0x2000>,
96 <0x48216000 0x2000>;
7136d457
MZ		 97 interrupt-parent = <&gic>;
98 };
99
100 wakeupgen: interrupt-controller@48281000 {
101 compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu";
102 interrupt-controller;
103 #interrupt-cells = <3>;
104 reg = <0x48281000 0x1000>;
105 interrupt-parent = <&gic>;
ba1829bc
SS		 106 };
107
6b5de091 108 /*
5c5be9db 109 * The soc node represents the soc top level view. It is used for IPs
6b5de091
S		 110 * that are not memory mapped in the MPU view or for the MPU itself.
111 */
112 soc {
113 compatible = "ti,omap-infra";
114 mpu {
1306c08a 115 compatible = "ti,omap4-mpu";
6b5de091 116 ti,hwmods = "mpu";
1306c08a 117 sram = <&ocmcram>;
6b5de091
S		 118 };
119 };
120
121 /*
122 * XXX: Use a flat representation of the OMAP3 interconnect.
123 * The real OMAP interconnect network is quite complex.
b7ab524b 124 * Since it will not bring real advantage to represent that in DT for
6b5de091
S		 125 * the moment, just use a fake OCP bus entry to represent the whole bus
126 * hierarchy.
127 */
128 ocp {
e7309c26 129 compatible = "ti,omap5-l3-noc", "simple-bus";
6b5de091
S		 130 #address-cells = <1>;
131 #size-cells = <1>;
132 ranges;
133 ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
20a60eaa
SS		 134 reg = <0x44000000 0x2000>,
135 <0x44800000 0x3000>,
136 <0x45000000 0x4000>;
8fea7d5a
FV		 137 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
138 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
6b5de091 139
ed8509ed
TK		 140 l4_cfg: l4@4a000000 {
141 compatible = "ti,omap5-l4-cfg", "simple-bus";
142 #address-cells = <1>;
143 #size-cells = <1>;
144 ranges = <0 0x4a000000 0x22a000>;
85dc74e9 145
ed8509ed
TK		 146 scm_core: scm@2000 {
147 compatible = "ti,omap5-scm-core", "simple-bus";
148 reg = <0x2000 0x1000>;
85dc74e9 149 #address-cells = <1>;
ed8509ed
TK		 150 #size-cells = <1>;
151 ranges = <0 0x2000 0x800>;
152
153 scm_conf: scm_conf@0 {
154 compatible = "syscon";
155 reg = <0x0 0x800>;
156 #address-cells = <1>;
157 #size-cells = <1>;
158 };
85dc74e9
TK		 159 };
160
ed8509ed
TK		 161 scm_padconf_core: scm@2800 {
162 compatible = "ti,omap5-scm-padconf-core",
163 "simple-bus";
164 #address-cells = <1>;
165 #size-cells = <1>;
166 ranges = <0 0x2800 0x800>;
167
168 omap5_pmx_core: pinmux@40 {
169 compatible = "ti,omap5-padconf",
170 "pinctrl-single";
171 reg = <0x40 0x01b6>;
172 #address-cells = <1>;
173 #size-cells = <0>;
174 #interrupt-cells = <1>;
175 interrupt-controller;
176 pinctrl-single,register-width = <16>;
177 pinctrl-single,function-mask = <0x7fff>;
178 };
179
180 omap5_padconf_global: omap5_padconf_global@5a0 {
70caac3f
KVA		 181 compatible = "syscon",
182 "simple-bus";
ed8509ed
TK		 183 reg = <0x5a0 0xec>;
184 #address-cells = <1>;
185 #size-cells = <1>;
9a5e3f27 186 ranges = <0 0x5a0 0xec>;
ed8509ed 187
308cfdaf 188 pbias_regulator: pbias_regulator@60 {
737f146f 189 compatible = "ti,pbias-omap5", "ti,pbias-omap";
ed8509ed
TK		 190 reg = <0x60 0x4>;
191 syscon = <&omap5_padconf_global>;
192 pbias_mmc_reg: pbias_mmc_omap5 {
193 regulator-name = "pbias_mmc_omap5";
194 regulator-min-microvolt = <1800000>;
195 regulator-max-microvolt = <3000000>;
196 };
197 };
198 };
85dc74e9 199 };
85dc74e9 200
ed8509ed
TK		 201 cm_core_aon: cm_core_aon@4000 {
202 compatible = "ti,omap5-cm-core-aon";
203 reg = <0x4000 0x2000>;
85dc74e9 204
ed8509ed
TK		 205 cm_core_aon_clocks: clocks {
206 #address-cells = <1>;
207 #size-cells = <0>;
208 };
85dc74e9 209
ed8509ed
TK		 210 cm_core_aon_clockdomains: clockdomains {
211 };
85dc74e9 212 };
85dc74e9 213
ed8509ed
TK		 214 cm_core: cm_core@8000 {
215 compatible = "ti,omap5-cm-core";
216 reg = <0x8000 0x3000>;
85dc74e9 217
ed8509ed
TK		 218 cm_core_clocks: clocks {
219 #address-cells = <1>;
220 #size-cells = <0>;
221 };
85dc74e9 222
ed8509ed
TK		 223 cm_core_clockdomains: clockdomains {
224 };
85dc74e9
TK		 225 };
226 };
227
ed8509ed
TK		 228 l4_wkup: l4@4ae00000 {
229 compatible = "ti,omap5-l4-wkup", "simple-bus";
230 #address-cells = <1>;
231 #size-cells = <1>;
232 ranges = <0 0x4ae00000 0x2b000>;
85dc74e9 233
ed8509ed
TK		 234 counter32k: counter@4000 {
235 compatible = "ti,omap-counter32k";
236 reg = <0x4000 0x40>;
237 ti,hwmods = "counter_32k";
85dc74e9
TK		 238 };
239
ed8509ed
TK		 240 prm: prm@6000 {
241 compatible = "ti,omap5-prm";
242 reg = <0x6000 0x3000>;
243 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
244
245 prm_clocks: clocks {
246 #address-cells = <1>;
247 #size-cells = <0>;
248 };
249
250 prm_clockdomains: clockdomains {
251 };
85dc74e9 252 };
85dc74e9 253
ed8509ed
TK		 254 scrm: scrm@a000 {
255 compatible = "ti,omap5-scrm";
256 reg = <0xa000 0x2000>;
3b3132f7 257
ed8509ed
TK		 258 scrm_clocks: clocks {
259 #address-cells = <1>;
260 #size-cells = <0>;
261 };
5da6a2d5 262
ed8509ed
TK		 263 scrm_clockdomains: clockdomains {
264 };
265 };
cd042fe5 266
ed8509ed
TK		 267 omap5_pmx_wkup: pinmux@c840 {
268 compatible = "ti,omap5-padconf",
269 "pinctrl-single";
7472931f 270 reg = <0xc840 0x003c>;
ed8509ed
TK		 271 #address-cells = <1>;
272 #size-cells = <0>;
273 #interrupt-cells = <1>;
274 interrupt-controller;
275 pinctrl-single,register-width = <16>;
276 pinctrl-single,function-mask = <0x7fff>;
cd042fe5
B		 277 };
278 };
279
8b9a2810
RN		 280 ocmcram: ocmcram@40300000 {
281 compatible = "mmio-sram";
282 reg = <0x40300000 0x20000>; /* 128k */
283 };
284
2c2dc545
JH		 285 sdma: dma-controller@4a056000 {
286 compatible = "ti,omap4430-sdma";
287 reg = <0x4a056000 0x1000>;
8fea7d5a
FV		 288 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
289 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
290 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
291 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
2c2dc545 292 #dma-cells = <1>;
951c1c04
PU		 293 dma-channels = <32>;
294 dma-requests = <127>;
2c2dc545
JH		 295 };
296
6b5de091
S		 297 gpio1: gpio@4ae10000 {
298 compatible = "ti,omap4-gpio";
f4b224f2 299 reg = <0x4ae10000 0x200>;
8fea7d5a 300 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
6b5de091 301 ti,hwmods = "gpio1";
e4b9b9f3 302 ti,gpio-always-on;
6b5de091
S		 303 gpio-controller;
304 #gpio-cells = <2>;
305 interrupt-controller;
ff5c9059 306 #interrupt-cells = <2>;
6b5de091
S		 307 };
308
309 gpio2: gpio@48055000 {
310 compatible = "ti,omap4-gpio";
f4b224f2 311 reg = <0x48055000 0x200>;
8fea7d5a 312 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
6b5de091
S		 313 ti,hwmods = "gpio2";
314 gpio-controller;
315 #gpio-cells = <2>;
316 interrupt-controller;
ff5c9059 317 #interrupt-cells = <2>;
6b5de091
S		 318 };
319
320 gpio3: gpio@48057000 {
321 compatible = "ti,omap4-gpio";
f4b224f2 322 reg = <0x48057000 0x200>;
8fea7d5a 323 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
6b5de091
S		 324 ti,hwmods = "gpio3";
325 gpio-controller;
326 #gpio-cells = <2>;
327 interrupt-controller;
ff5c9059 328 #interrupt-cells = <2>;
6b5de091
S		 329 };
330
331 gpio4: gpio@48059000 {
332 compatible = "ti,omap4-gpio";
f4b224f2 333 reg = <0x48059000 0x200>;
8fea7d5a 334 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
6b5de091
S		 335 ti,hwmods = "gpio4";
336 gpio-controller;
337 #gpio-cells = <2>;
338 interrupt-controller;
ff5c9059 339 #interrupt-cells = <2>;
6b5de091
S		 340 };
341
342 gpio5: gpio@4805b000 {
343 compatible = "ti,omap4-gpio";
f4b224f2 344 reg = <0x4805b000 0x200>;
8fea7d5a 345 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
6b5de091
S		 346 ti,hwmods = "gpio5";
347 gpio-controller;
348 #gpio-cells = <2>;
349 interrupt-controller;
ff5c9059 350 #interrupt-cells = <2>;
6b5de091
S		 351 };
352
353 gpio6: gpio@4805d000 {
354 compatible = "ti,omap4-gpio";
f4b224f2 355 reg = <0x4805d000 0x200>;
8fea7d5a 356 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
6b5de091
S		 357 ti,hwmods = "gpio6";
358 gpio-controller;
359 #gpio-cells = <2>;
360 interrupt-controller;
ff5c9059 361 #interrupt-cells = <2>;
6b5de091
S		 362 };
363
364 gpio7: gpio@48051000 {
365 compatible = "ti,omap4-gpio";
f4b224f2 366 reg = <0x48051000 0x200>;
8fea7d5a 367 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
6b5de091
S		 368 ti,hwmods = "gpio7";
369 gpio-controller;
370 #gpio-cells = <2>;
371 interrupt-controller;
ff5c9059 372 #interrupt-cells = <2>;
6b5de091
S		 373 };
374
375 gpio8: gpio@48053000 {
376 compatible = "ti,omap4-gpio";
f4b224f2 377 reg = <0x48053000 0x200>;
8fea7d5a 378 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
6b5de091
S		 379 ti,hwmods = "gpio8";
380 gpio-controller;
381 #gpio-cells = <2>;
382 interrupt-controller;
ff5c9059 383 #interrupt-cells = <2>;
6b5de091
S		 384 };
385
1c7dbb55
JH		 386 gpmc: gpmc@50000000 {
387 compatible = "ti,omap4430-gpmc";
388 reg = <0x50000000 0x1000>;
389 #address-cells = <2>;
390 #size-cells = <1>;
8fea7d5a 391 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
201c7e33
FCJ		 392 dmas = <&sdma 4>;
393 dma-names = "rxtx";
1c7dbb55
JH		 394 gpmc,num-cs = <8>;
395 gpmc,num-waitpins = <4>;
396 ti,hwmods = "gpmc";
7b8b6af1
FV		 397 clocks = <&l3_iclk_div>;
398 clock-names = "fck";
e99d413f
RQ		 399 interrupt-controller;
400 #interrupt-cells = <2>;
401 gpio-controller;
402 #gpio-cells = <2>;
1c7dbb55
JH		 403 };
404
6e6a9a50
SP		 405 i2c1: i2c@48070000 {
406 compatible = "ti,omap4-i2c";
d7118bbd 407 reg = <0x48070000 0x100>;
8fea7d5a 408 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
6e6a9a50
SP		 409 #address-cells = <1>;
410 #size-cells = <0>;
411 ti,hwmods = "i2c1";
412 };
413
414 i2c2: i2c@48072000 {
415 compatible = "ti,omap4-i2c";
d7118bbd 416 reg = <0x48072000 0x100>;
8fea7d5a 417 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
6e6a9a50
SP		 418 #address-cells = <1>;
419 #size-cells = <0>;
420 ti,hwmods = "i2c2";
421 };
422
423 i2c3: i2c@48060000 {
424 compatible = "ti,omap4-i2c";
d7118bbd 425 reg = <0x48060000 0x100>;
8fea7d5a 426 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
6e6a9a50
SP		 427 #address-cells = <1>;
428 #size-cells = <0>;
429 ti,hwmods = "i2c3";
430 };
431
d7118bbd 432 i2c4: i2c@4807a000 {
6e6a9a50 433 compatible = "ti,omap4-i2c";
d7118bbd 434 reg = <0x4807a000 0x100>;
8fea7d5a 435 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
6e6a9a50
SP		 436 #address-cells = <1>;
437 #size-cells = <0>;
438 ti,hwmods = "i2c4";
439 };
440
d7118bbd 441 i2c5: i2c@4807c000 {
6e6a9a50 442 compatible = "ti,omap4-i2c";
d7118bbd 443 reg = <0x4807c000 0x100>;
8fea7d5a 444 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
6e6a9a50
SP		 445 #address-cells = <1>;
446 #size-cells = <0>;
447 ti,hwmods = "i2c5";
448 };
449
fe0e09e4
SA		 450 hwspinlock: spinlock@4a0f6000 {
451 compatible = "ti,omap4-hwspinlock";
452 reg = <0x4a0f6000 0x1000>;
453 ti,hwmods = "spinlock";
34054213 454 #hwlock-cells = <1>;
fe0e09e4
SA		 455 };
456
43286b11
FB		 457 mcspi1: spi@48098000 {
458 compatible = "ti,omap4-mcspi";
459 reg = <0x48098000 0x200>;
8fea7d5a 460 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
43286b11
FB		 461 #address-cells = <1>;
462 #size-cells = <0>;
463 ti,hwmods = "mcspi1";
464 ti,spi-num-cs = <4>;
2c2dc545
JH		 465 dmas = <&sdma 35>,
466 <&sdma 36>,
467 <&sdma 37>,
468 <&sdma 38>,
469 <&sdma 39>,
470 <&sdma 40>,
471 <&sdma 41>,
472 <&sdma 42>;
473 dma-names = "tx0", "rx0", "tx1", "rx1",
474 "tx2", "rx2", "tx3", "rx3";
43286b11
FB		 475 };
476
477 mcspi2: spi@4809a000 {
478 compatible = "ti,omap4-mcspi";
479 reg = <0x4809a000 0x200>;
8fea7d5a 480 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
43286b11
FB		 481 #address-cells = <1>;
482 #size-cells = <0>;
483 ti,hwmods = "mcspi2";
484 ti,spi-num-cs = <2>;
2c2dc545
JH		 485 dmas = <&sdma 43>,
486 <&sdma 44>,
487 <&sdma 45>,
488 <&sdma 46>;
489 dma-names = "tx0", "rx0", "tx1", "rx1";
43286b11
FB		 490 };
491
492 mcspi3: spi@480b8000 {
493 compatible = "ti,omap4-mcspi";
494 reg = <0x480b8000 0x200>;
8fea7d5a 495 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
43286b11
FB		 496 #address-cells = <1>;
497 #size-cells = <0>;
498 ti,hwmods = "mcspi3";
499 ti,spi-num-cs = <2>;
2c2dc545
JH		 500 dmas = <&sdma 15>, <&sdma 16>;
501 dma-names = "tx0", "rx0";
43286b11
FB		 502 };
503
504 mcspi4: spi@480ba000 {
505 compatible = "ti,omap4-mcspi";
506 reg = <0x480ba000 0x200>;
8fea7d5a 507 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
43286b11
FB		 508 #address-cells = <1>;
509 #size-cells = <0>;
510 ti,hwmods = "mcspi4";
511 ti,spi-num-cs = <1>;
2c2dc545
JH		 512 dmas = <&sdma 70>, <&sdma 71>;
513 dma-names = "tx0", "rx0";
43286b11
FB		 514 };
515
6b5de091
S		 516 uart1: serial@4806a000 {
517 compatible = "ti,omap4-uart";
8e80f660 518 reg = <0x4806a000 0x100>;
7136d457 519 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
6b5de091
S		 520 ti,hwmods = "uart1";
521 clock-frequency = <48000000>;
522 };
523
524 uart2: serial@4806c000 {
525 compatible = "ti,omap4-uart";
8e80f660 526 reg = <0x4806c000 0x100>;
7136d457 527 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
6b5de091
S		 528 ti,hwmods = "uart2";
529 clock-frequency = <48000000>;
530 };
531
532 uart3: serial@48020000 {
533 compatible = "ti,omap4-uart";
8e80f660 534 reg = <0x48020000 0x100>;
7136d457 535 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
6b5de091
S		 536 ti,hwmods = "uart3";
537 clock-frequency = <48000000>;
538 };
539
540 uart4: serial@4806e000 {
541 compatible = "ti,omap4-uart";
8e80f660 542 reg = <0x4806e000 0x100>;
7136d457 543 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
6b5de091
S		 544 ti,hwmods = "uart4";
545 clock-frequency = <48000000>;
546 };
547
548 uart5: serial@48066000 {
8e80f660
SG		 549 compatible = "ti,omap4-uart";
550 reg = <0x48066000 0x100>;
7136d457 551 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
6b5de091
S		 552 ti,hwmods = "uart5";
553 clock-frequency = <48000000>;
554 };
555
556 uart6: serial@48068000 {
8e80f660
SG		 557 compatible = "ti,omap4-uart";
558 reg = <0x48068000 0x100>;
7136d457 559 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
6b5de091
S		 560 ti,hwmods = "uart6";
561 clock-frequency = <48000000>;
562 };
5dd18b01
B		 563
564 mmc1: mmc@4809c000 {
565 compatible = "ti,omap4-hsmmc";
9a642362 566 reg = <0x4809c000 0x400>;
8fea7d5a 567 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
5dd18b01
B		 568 ti,hwmods = "mmc1";
569 ti,dual-volt;
570 ti,needs-special-reset;
2c2dc545
JH		 571 dmas = <&sdma 61>, <&sdma 62>;
572 dma-names = "tx", "rx";
cd042fe5 573 pbias-supply = <&pbias_mmc_reg>;
5dd18b01
B		 574 };
575
576 mmc2: mmc@480b4000 {
577 compatible = "ti,omap4-hsmmc";
9a642362 578 reg = <0x480b4000 0x400>;
8fea7d5a 579 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
5dd18b01
B		 580 ti,hwmods = "mmc2";
581 ti,needs-special-reset;
2c2dc545
JH		 582 dmas = <&sdma 47>, <&sdma 48>;
583 dma-names = "tx", "rx";
5dd18b01
B		 584 };
585
586 mmc3: mmc@480ad000 {
587 compatible = "ti,omap4-hsmmc";
9a642362 588 reg = <0x480ad000 0x400>;
8fea7d5a 589 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
5dd18b01
B		 590 ti,hwmods = "mmc3";
591 ti,needs-special-reset;
2c2dc545
JH		 592 dmas = <&sdma 77>, <&sdma 78>;
593 dma-names = "tx", "rx";
5dd18b01
B		 594 };
595
596 mmc4: mmc@480d1000 {
597 compatible = "ti,omap4-hsmmc";
9a642362 598 reg = <0x480d1000 0x400>;
8fea7d5a 599 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
5dd18b01
B		 600 ti,hwmods = "mmc4";
601 ti,needs-special-reset;
2c2dc545
JH		 602 dmas = <&sdma 57>, <&sdma 58>;
603 dma-names = "tx", "rx";
5dd18b01
B		 604 };
605
606 mmc5: mmc@480d5000 {
607 compatible = "ti,omap4-hsmmc";
9a642362 608 reg = <0x480d5000 0x400>;
8fea7d5a 609 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
5dd18b01
B		 610 ti,hwmods = "mmc5";
611 ti,needs-special-reset;
2c2dc545
JH		 612 dmas = <&sdma 59>, <&sdma 60>;
613 dma-names = "tx", "rx";
5dd18b01 614 };
5449fbc2 615
2dcfa56e
SA		 616 mmu_dsp: mmu@4a066000 {
617 compatible = "ti,omap4-iommu";
618 reg = <0x4a066000 0x100>;
619 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
620 ti,hwmods = "mmu_dsp";
c1b5d0f6 621 #iommu-cells = <0>;
2dcfa56e
SA		 622 };
623
624 mmu_ipu: mmu@55082000 {
625 compatible = "ti,omap4-iommu";
626 reg = <0x55082000 0x100>;
627 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
628 ti,hwmods = "mmu_ipu";
c1b5d0f6 629 #iommu-cells = <0>;
2dcfa56e
SA		 630 ti,iommu-bus-err-back;
631 };
632
5449fbc2
SP		 633 keypad: keypad@4ae1c000 {
634 compatible = "ti,omap4-keypad";
8cc8b89f 635 reg = <0x4ae1c000 0x400>;
5449fbc2
SP		 636 ti,hwmods = "kbd";
637 };
ffd5db24 638
cbb57f07
PU		 639 mcpdm: mcpdm@40132000 {
640 compatible = "ti,omap4-mcpdm";
641 reg = <0x40132000 0x7f>, /* MPU private access */
642 <0x49032000 0x7f>; /* L3 Interconnect */
643 reg-names = "mpu", "dma";
8fea7d5a 644 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
cbb57f07 645 ti,hwmods = "mcpdm";
4e4ead73
SG		 646 dmas = <&sdma 65>,
647 <&sdma 66>;
648 dma-names = "up_link", "dn_link";
f15534ea 649 status = "disabled";
cbb57f07
PU		 650 };
651
652 dmic: dmic@4012e000 {
653 compatible = "ti,omap4-dmic";
654 reg = <0x4012e000 0x7f>, /* MPU private access */
655 <0x4902e000 0x7f>; /* L3 Interconnect */
656 reg-names = "mpu", "dma";
8fea7d5a 657 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
cbb57f07 658 ti,hwmods = "dmic";
4e4ead73
SG		 659 dmas = <&sdma 67>;
660 dma-names = "up_link";
f15534ea 661 status = "disabled";
cbb57f07
PU		 662 };
663
ffd5db24
PU		 664 mcbsp1: mcbsp@40122000 {
665 compatible = "ti,omap4-mcbsp";
666 reg = <0x40122000 0xff>, /* MPU private access */
667 <0x49022000 0xff>; /* L3 Interconnect */
668 reg-names = "mpu", "dma";
8fea7d5a 669 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
ffd5db24 670 interrupt-names = "common";
ffd5db24
PU		 671 ti,buffer-size = <128>;
672 ti,hwmods = "mcbsp1";
4e4ead73
SG		 673 dmas = <&sdma 33>,
674 <&sdma 34>;
675 dma-names = "tx", "rx";
f15534ea 676 status = "disabled";
ffd5db24
PU		 677 };
678
679 mcbsp2: mcbsp@40124000 {
680 compatible = "ti,omap4-mcbsp";
681 reg = <0x40124000 0xff>, /* MPU private access */
682 <0x49024000 0xff>; /* L3 Interconnect */
683 reg-names = "mpu", "dma";
8fea7d5a 684 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
ffd5db24 685 interrupt-names = "common";
ffd5db24
PU		 686 ti,buffer-size = <128>;
687 ti,hwmods = "mcbsp2";
4e4ead73
SG		 688 dmas = <&sdma 17>,
689 <&sdma 18>;
690 dma-names = "tx", "rx";
f15534ea 691 status = "disabled";
ffd5db24
PU		 692 };
693
694 mcbsp3: mcbsp@40126000 {
695 compatible = "ti,omap4-mcbsp";
696 reg = <0x40126000 0xff>, /* MPU private access */
697 <0x49026000 0xff>; /* L3 Interconnect */
698 reg-names = "mpu", "dma";
8fea7d5a 699 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
ffd5db24 700 interrupt-names = "common";
ffd5db24
PU		 701 ti,buffer-size = <128>;
702 ti,hwmods = "mcbsp3";
4e4ead73
SG		 703 dmas = <&sdma 19>,
704 <&sdma 20>;
705 dma-names = "tx", "rx";
f15534ea 706 status = "disabled";
ffd5db24 707 };
df692a92 708
84d89c31
SA		 709 mailbox: mailbox@4a0f4000 {
710 compatible = "ti,omap4-mailbox";
711 reg = <0x4a0f4000 0x200>;
712 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
713 ti,hwmods = "mailbox";
24df0453 714 #mbox-cells = <1>;
41ffada1
SA		 715 ti,mbox-num-users = <3>;
716 ti,mbox-num-fifos = <8>;
d27704d1
SA		 717 mbox_ipu: mbox_ipu {
718 ti,mbox-tx = <0 0 0>;
719 ti,mbox-rx = <1 0 0>;
720 };
721 mbox_dsp: mbox_dsp {
722 ti,mbox-tx = <3 0 0>;
723 ti,mbox-rx = <2 0 0>;
724 };
84d89c31
SA		 725 };
726
df692a92 727 timer1: timer@4ae18000 {
002e1ec5 728 compatible = "ti,omap5430-timer";
df692a92 729 reg = <0x4ae18000 0x80>;
8fea7d5a 730 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
df692a92
JH		 731 ti,hwmods = "timer1";
732 ti,timer-alwon;
733 };
734
735 timer2: timer@48032000 {
002e1ec5 736 compatible = "ti,omap5430-timer";
df692a92 737 reg = <0x48032000 0x80>;
8fea7d5a 738 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
df692a92
JH		 739 ti,hwmods = "timer2";
740 };
741
742 timer3: timer@48034000 {
002e1ec5 743 compatible = "ti,omap5430-timer";
df692a92 744 reg = <0x48034000 0x80>;
8fea7d5a 745 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
df692a92
JH		 746 ti,hwmods = "timer3";
747 };
748
749 timer4: timer@48036000 {
002e1ec5 750 compatible = "ti,omap5430-timer";
df692a92 751 reg = <0x48036000 0x80>;
8fea7d5a 752 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
df692a92
JH		 753 ti,hwmods = "timer4";
754 };
755
756 timer5: timer@40138000 {
002e1ec5 757 compatible = "ti,omap5430-timer";
df692a92
JH		 758 reg = <0x40138000 0x80>,
759 <0x49038000 0x80>;
8fea7d5a 760 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
df692a92
JH		 761 ti,hwmods = "timer5";
762 ti,timer-dsp;
8341613a 763 ti,timer-pwm;
df692a92
JH		 764 };
765
766 timer6: timer@4013a000 {
002e1ec5 767 compatible = "ti,omap5430-timer";
df692a92
JH		 768 reg = <0x4013a000 0x80>,
769 <0x4903a000 0x80>;
8fea7d5a 770 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
df692a92
JH		 771 ti,hwmods = "timer6";
772 ti,timer-dsp;
773 ti,timer-pwm;
774 };
775
776 timer7: timer@4013c000 {
002e1ec5 777 compatible = "ti,omap5430-timer";
df692a92
JH		 778 reg = <0x4013c000 0x80>,
779 <0x4903c000 0x80>;
8fea7d5a 780 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
df692a92
JH		 781 ti,hwmods = "timer7";
782 ti,timer-dsp;
783 };
784
785 timer8: timer@4013e000 {
002e1ec5 786 compatible = "ti,omap5430-timer";
df692a92
JH		 787 reg = <0x4013e000 0x80>,
788 <0x4903e000 0x80>;
8fea7d5a 789 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
df692a92
JH		 790 ti,hwmods = "timer8";
791 ti,timer-dsp;
792 ti,timer-pwm;
793 };
794
795 timer9: timer@4803e000 {
002e1ec5 796 compatible = "ti,omap5430-timer";
df692a92 797 reg = <0x4803e000 0x80>;
8fea7d5a 798 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
df692a92 799 ti,hwmods = "timer9";
8341613a 800 ti,timer-pwm;
df692a92
JH		 801 };
802
803 timer10: timer@48086000 {
002e1ec5 804 compatible = "ti,omap5430-timer";
df692a92 805 reg = <0x48086000 0x80>;
8fea7d5a 806 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
df692a92 807 ti,hwmods = "timer10";
8341613a 808 ti,timer-pwm;
df692a92
JH		 809 };
810
811 timer11: timer@48088000 {
002e1ec5 812 compatible = "ti,omap5430-timer";
df692a92 813 reg = <0x48088000 0x80>;
8fea7d5a 814 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
df692a92
JH		 815 ti,hwmods = "timer11";
816 ti,timer-pwm;
817 };
e6900ddf 818
55452197
LV		 819 wdt2: wdt@4ae14000 {
820 compatible = "ti,omap5-wdt", "ti,omap3-wdt";
821 reg = <0x4ae14000 0x80>;
8fea7d5a 822 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
55452197
LV		 823 ti,hwmods = "wd_timer2";
824 };
825
1a5fe3ca
AT		 826 dmm@4e000000 {
827 compatible = "ti,omap5-dmm";
828 reg = <0x4e000000 0x800>;
829 interrupts = <0 113 0x4>;
830 ti,hwmods = "dmm";
831 };
832
8906d654 833 emif1: emif@4c000000 {
e6900ddf
LV		 834 compatible = "ti,emif-4d5";
835 ti,hwmods = "emif1";
f12ecbe2 836 ti,no-idle-on-init;
e6900ddf
LV		 837 phy-type = <2>; /* DDR PHY type: Intelli PHY */
838 reg = <0x4c000000 0x400>;
8fea7d5a 839 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
e6900ddf
LV		 840 hw-caps-read-idle-ctrl;
841 hw-caps-ll-interface;
842 hw-caps-temp-alert;
843 };
844
8906d654 845 emif2: emif@4d000000 {
e6900ddf
LV		 846 compatible = "ti,emif-4d5";
847 ti,hwmods = "emif2";
f12ecbe2 848 ti,no-idle-on-init;
e6900ddf
LV		 849 phy-type = <2>; /* DDR PHY type: Intelli PHY */
850 reg = <0x4d000000 0x400>;
8fea7d5a 851 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
e6900ddf
LV		 852 hw-caps-read-idle-ctrl;
853 hw-caps-ll-interface;
854 hw-caps-temp-alert;
855 };
fedc428e 856
e3a412c9 857 usb3: omap_dwc3@4a020000 {
72f6f957
KVA		 858 compatible = "ti,dwc3";
859 ti,hwmods = "usb_otg_ss";
6f61ee23 860 reg = <0x4a020000 0x10000>;
8fea7d5a 861 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
72f6f957
KVA		 862 #address-cells = <1>;
863 #size-cells = <1>;
864 utmi-mode = <2>;
865 ranges;
866 dwc3@4a030000 {
22a5aa17 867 compatible = "snps,dwc3";
6f61ee23 868 reg = <0x4a030000 0x10000>;
8d33c093
RQ		 869 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
870 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
871 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
872 interrupt-names = "peripheral",
873 "host",
874 "otg";
073addc8
KVA		 875 phys = <&usb2_phy>, <&usb3_phy>;
876 phy-names = "usb2-phy", "usb3-phy";
c47ee6ee 877 dr_mode = "peripheral";
72f6f957
KVA		 878 };
879 };
880
b6731f78 881 ocp2scp@4a080000 {
e9831967
KVA		 882 compatible = "ti,omap-ocp2scp";
883 #address-cells = <1>;
884 #size-cells = <1>;
b6731f78 885 reg = <0x4a080000 0x20>;
e9831967
KVA		 886 ranges;
887 ti,hwmods = "ocp2scp1";
ae6a32d2
KVA		 888 usb2_phy: usb2phy@4a084000 {
889 compatible = "ti,omap-usb2";
890 reg = <0x4a084000 0x7c>;
2338c76a 891 syscon-phy-power = <&scm_conf 0x300>;
c65d0ad5
RQ		 892 clocks = <&usb_phy_cm_clk32k>, <&usb_otg_ss_refclk960m>;
893 clock-names = "wkupclk", "refclk";
073addc8 894 #phy-cells = <0>;
ae6a32d2
KVA		 895 };
896
897 usb3_phy: usb3phy@4a084400 {
898 compatible = "ti,omap-usb3";
899 reg = <0x4a084400 0x80>,
900 <0x4a084800 0x64>,
901 <0x4a084c00 0x40>;
902 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
2338c76a 903 syscon-phy-power = <&scm_conf 0x370>;
ada76576
RQ		 904 clocks = <&usb_phy_cm_clk32k>,
905 <&sys_clkin>,
906 <&usb_otg_ss_refclk960m>;
907 clock-names = "wkupclk",
908 "sysclk",
909 "refclk";
073addc8 910 #phy-cells = <0>;
ae6a32d2 911 };
e9831967 912 };
ed7f8e8a
RQ		 913
914 usbhstll: usbhstll@4a062000 {
915 compatible = "ti,usbhs-tll";
916 reg = <0x4a062000 0x1000>;
917 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
918 ti,hwmods = "usb_tll_hs";
919 };
920
921 usbhshost: usbhshost@4a064000 {
922 compatible = "ti,usbhs-host";
923 reg = <0x4a064000 0x800>;
924 ti,hwmods = "usb_host_hs";
925 #address-cells = <1>;
926 #size-cells = <1>;
927 ranges;
051fc06d
RQ		 928 clocks = <&l3init_60m_fclk>,
929 <&xclk60mhsp1_ck>,
930 <&xclk60mhsp2_ck>;
931 clock-names = "refclk_60m_int",
932 "refclk_60m_ext_p1",
933 "refclk_60m_ext_p2";
ed7f8e8a
RQ		 934
935 usbhsohci: ohci@4a064800 {
a2525e54 936 compatible = "ti,ohci-omap3";
ed7f8e8a 937 reg = <0x4a064800 0x400>;
ed7f8e8a
RQ		 938 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
939 };
940
941 usbhsehci: ehci@4a064c00 {
a2525e54 942 compatible = "ti,ehci-omap";
ed7f8e8a 943 reg = <0x4a064c00 0x400>;
ed7f8e8a
RQ		 944 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
945 };
946 };
cbad26db 947
1b761fc5 948 bandgap: bandgap@4a0021e0 {
cbad26db
EV		 949 reg = <0x4a0021e0 0xc
950 0x4a00232c 0xc
951 0x4a002380 0x2c
952 0x4a0023C0 0x3c>;
953 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
954 compatible = "ti,omap5430-bandgap";
1b761fc5
EV		 955
956 #thermal-sensor-cells = <1>;
cbad26db 957 };
4f82952c 958
4f82952c
B		 959 /* OCP2SCP3 */
960 ocp2scp@4a090000 {
961 compatible = "ti,omap-ocp2scp";
962 #address-cells = <1>;
963 #size-cells = <1>;
964 reg = <0x4a090000 0x20>;
965 ranges;
966 ti,hwmods = "ocp2scp3";
967 sata_phy: phy@4a096000 {
968 compatible = "ti,phy-pipe3-sata";
969 reg = <0x4A096000 0x80>, /* phy_rx */
970 <0x4A096400 0x64>, /* phy_tx */
971 <0x4A096800 0x40>; /* pll_ctrl */
972 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
2338c76a 973 syscon-phy-power = <&scm_conf 0x374>;
a0182724
RQ		 974 clocks = <&sys_clkin>, <&sata_ref_clk>;
975 clock-names = "sysclk", "refclk";
4f82952c
B		 976 #phy-cells = <0>;
977 };
978 };
979
980 sata: sata@4a141100 {
981 compatible = "snps,dwc-ahci";
982 reg = <0x4a140000 0x1100>, <0x4a141100 0x7>;
983 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
984 phys = <&sata_phy>;
985 phy-names = "sata-phy";
986 clocks = <&sata_ref_clk>;
987 ti,hwmods = "sata";
988 };
989
e7585c4f
TV		 990 dss: dss@58000000 {
991 compatible = "ti,omap5-dss";
992 reg = <0x58000000 0x80>;
993 status = "disabled";
994 ti,hwmods = "dss_core";
995 clocks = <&dss_dss_clk>;
996 clock-names = "fck";
997 #address-cells = <1>;
998 #size-cells = <1>;
999 ranges;
1000
1001 dispc@58001000 {
1002 compatible = "ti,omap5-dispc";
1003 reg = <0x58001000 0x1000>;
1004 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
1005 ti,hwmods = "dss_dispc";
1006 clocks = <&dss_dss_clk>;
1007 clock-names = "fck";
1008 };
1009
84ace674
TV		 1010 rfbi: encoder@58002000 {
1011 compatible = "ti,omap5-rfbi";
1012 reg = <0x58002000 0x100>;
1013 status = "disabled";
1014 ti,hwmods = "dss_rfbi";
1015 clocks = <&dss_dss_clk>, <&l3_iclk_div>;
1016 clock-names = "fck", "ick";
1017 };
1018
e7585c4f
TV		 1019 dsi1: encoder@58004000 {
1020 compatible = "ti,omap5-dsi";
1021 reg = <0x58004000 0x200>,
1022 <0x58004200 0x40>,
1023 <0x58004300 0x40>;
1024 reg-names = "proto", "phy", "pll";
1025 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
1026 status = "disabled";
1027 ti,hwmods = "dss_dsi1";
1028 clocks = <&dss_dss_clk>, <&dss_sys_clk>;
1029 clock-names = "fck", "sys_clk";
1030 };
1031
1032 dsi2: encoder@58005000 {
1033 compatible = "ti,omap5-dsi";
1034 reg = <0x58009000 0x200>,
1035 <0x58009200 0x40>,
1036 <0x58009300 0x40>;
1037 reg-names = "proto", "phy", "pll";
1038 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
1039 status = "disabled";
1040 ti,hwmods = "dss_dsi2";
1041 clocks = <&dss_dss_clk>, <&dss_sys_clk>;
1042 clock-names = "fck", "sys_clk";
1043 };
1044
1045 hdmi: encoder@58060000 {
1046 compatible = "ti,omap5-hdmi";
1047 reg = <0x58040000 0x200>,
1048 <0x58040200 0x80>,
1049 <0x58040300 0x80>,
1050 <0x58060000 0x19000>;
1051 reg-names = "wp", "pll", "phy", "core";
1052 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1053 status = "disabled";
1054 ti,hwmods = "dss_hdmi";
1055 clocks = <&dss_48mhz_clk>, <&dss_sys_clk>;
1056 clock-names = "fck", "sys_clk";
7d0fde39
JS		 1057 dmas = <&sdma 76>;
1058 dma-names = "audio_tx";
e7585c4f
TV		 1059 };
1060 };
07b9b3d9
AT		 1061
1062 abb_mpu: regulator-abb-mpu {
1063 compatible = "ti,abb-v2";
1064 regulator-name = "abb_mpu";
1065 #address-cells = <0>;
1066 #size-cells = <0>;
1067 clocks = <&sys_clkin>;
1068 ti,settling-time = <50>;
1069 ti,clock-cycles = <16>;
1070
1071 reg = <0x4ae07cdc 0x8>, <0x4ae06014 0x4>,
1072 <0x4a0021c4 0x8>, <0x4ae0c318 0x4>;
1073 reg-names = "base-address", "int-address",
1074 "efuse-address", "ldo-address";
1075 ti,tranxdone-status-mask = <0x80>;
1076 /* LDOVBBMPU_MUX_CTRL */
1077 ti,ldovbb-override-mask = <0x400>;
1078 /* LDOVBBMPU_VSET_OUT */
1079 ti,ldovbb-vset-mask = <0x1F>;
1080
1081 /*
1082 * NOTE: only FBB mode used but actual vset will
1083 * determine final biasing
1084 */
1085 ti,abb_info = <
1086 /*uV ABB efuse rbb_m fbb_m vset_m*/
1087 1060000 0 0x0 0 0x02000000 0x01F00000
1088 1250000 0 0x4 0 0x02000000 0x01F00000
1089 >;
1090 };
1091
1092 abb_mm: regulator-abb-mm {
1093 compatible = "ti,abb-v2";
1094 regulator-name = "abb_mm";
1095 #address-cells = <0>;
1096 #size-cells = <0>;
1097 clocks = <&sys_clkin>;
1098 ti,settling-time = <50>;
1099 ti,clock-cycles = <16>;
1100
1101 reg = <0x4ae07ce4 0x8>, <0x4ae06010 0x4>,
1102 <0x4a0021a4 0x8>, <0x4ae0c314 0x4>;
1103 reg-names = "base-address", "int-address",
1104 "efuse-address", "ldo-address";
1105 ti,tranxdone-status-mask = <0x80000000>;
1106 /* LDOVBBMM_MUX_CTRL */
1107 ti,ldovbb-override-mask = <0x400>;
1108 /* LDOVBBMM_VSET_OUT */
1109 ti,ldovbb-vset-mask = <0x1F>;
1110
1111 /*
1112 * NOTE: only FBB mode used but actual vset will
1113 * determine final biasing
1114 */
1115 ti,abb_info = <
1116 /*uV ABB efuse rbb_m fbb_m vset_m*/
1117 1025000 0 0x0 0 0x02000000 0x01F00000
1118 1120000 0 0x4 0 0x02000000 0x01F00000
1119 >;
1120 };
6b5de091
S		 1121 };
1122};
85dc74e9 1123
38f5c8ba
TK		 1124&cpu_thermal {
1125 polling-delay = <500>; /* milliseconds */
1126};
1127
85dc74e9 1128/include/ "omap54xx-clocks.dtsi"
Linux kernel - Deliverables
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