Commit | Line | Data |
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6b5de091 S |
1 | /* |
2 | * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | * Based on "omap4.dtsi" | |
8 | */ | |
9 | ||
6d624eab | 10 | #include <dt-bindings/gpio/gpio.h> |
8fea7d5a | 11 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
bcd3cca7 | 12 | #include <dt-bindings/pinctrl/omap.h> |
6b5de091 | 13 | |
98ef7957 | 14 | #include "skeleton.dtsi" |
6b5de091 S |
15 | |
16 | / { | |
ba1829bc SS |
17 | #address-cells = <1>; |
18 | #size-cells = <1>; | |
19 | ||
6b5de091 | 20 | compatible = "ti,omap5"; |
7136d457 | 21 | interrupt-parent = <&wakeupgen>; |
6b5de091 S |
22 | |
23 | aliases { | |
20b80942 NM |
24 | i2c0 = &i2c1; |
25 | i2c1 = &i2c2; | |
26 | i2c2 = &i2c3; | |
27 | i2c3 = &i2c4; | |
28 | i2c4 = &i2c5; | |
6b5de091 S |
29 | serial0 = &uart1; |
30 | serial1 = &uart2; | |
31 | serial2 = &uart3; | |
32 | serial3 = &uart4; | |
33 | serial4 = &uart5; | |
34 | serial5 = &uart6; | |
35 | }; | |
36 | ||
37 | cpus { | |
eeb25fd5 LP |
38 | #address-cells = <1>; |
39 | #size-cells = <0>; | |
40 | ||
b8981d71 | 41 | cpu0: cpu@0 { |
eeb25fd5 | 42 | device_type = "cpu"; |
6b5de091 | 43 | compatible = "arm,cortex-a15"; |
eeb25fd5 | 44 | reg = <0x0>; |
6c24894d K |
45 | |
46 | operating-points = < | |
47 | /* kHz uV */ | |
6c24894d K |
48 | 1000000 1060000 |
49 | 1500000 1250000 | |
50 | >; | |
8d766fa2 NM |
51 | |
52 | clocks = <&dpll_mpu_ck>; | |
53 | clock-names = "cpu"; | |
54 | ||
55 | clock-latency = <300000>; /* From omap-cpufreq driver */ | |
56 | ||
2cd29f63 EV |
57 | /* cooling options */ |
58 | cooling-min-level = <0>; | |
59 | cooling-max-level = <2>; | |
60 | #cooling-cells = <2>; /* min followed by max */ | |
6b5de091 S |
61 | }; |
62 | cpu@1 { | |
eeb25fd5 | 63 | device_type = "cpu"; |
6b5de091 | 64 | compatible = "arm,cortex-a15"; |
eeb25fd5 | 65 | reg = <0x1>; |
6b5de091 S |
66 | }; |
67 | }; | |
68 | ||
1b761fc5 EV |
69 | thermal-zones { |
70 | #include "omap4-cpu-thermal.dtsi" | |
71 | #include "omap5-gpu-thermal.dtsi" | |
72 | #include "omap5-core-thermal.dtsi" | |
73 | }; | |
74 | ||
b45ccc4e SS |
75 | timer { |
76 | compatible = "arm,armv7-timer"; | |
8fea7d5a FV |
77 | /* PPI secure/nonsecure IRQ */ |
78 | interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>, | |
79 | <GIC_PPI 14 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>, | |
80 | <GIC_PPI 11 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>, | |
81 | <GIC_PPI 10 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>; | |
7136d457 | 82 | interrupt-parent = <&gic>; |
b45ccc4e SS |
83 | }; |
84 | ||
69a126cb NL |
85 | pmu { |
86 | compatible = "arm,cortex-a15-pmu"; | |
87 | interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, | |
88 | <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; | |
89 | }; | |
90 | ||
ba1829bc SS |
91 | gic: interrupt-controller@48211000 { |
92 | compatible = "arm,cortex-a15-gic"; | |
93 | interrupt-controller; | |
94 | #interrupt-cells = <3>; | |
95 | reg = <0x48211000 0x1000>, | |
0129c16c SS |
96 | <0x48212000 0x1000>, |
97 | <0x48214000 0x2000>, | |
98 | <0x48216000 0x2000>; | |
7136d457 MZ |
99 | interrupt-parent = <&gic>; |
100 | }; | |
101 | ||
102 | wakeupgen: interrupt-controller@48281000 { | |
103 | compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu"; | |
104 | interrupt-controller; | |
105 | #interrupt-cells = <3>; | |
106 | reg = <0x48281000 0x1000>; | |
107 | interrupt-parent = <&gic>; | |
ba1829bc SS |
108 | }; |
109 | ||
6b5de091 | 110 | /* |
5c5be9db | 111 | * The soc node represents the soc top level view. It is used for IPs |
6b5de091 S |
112 | * that are not memory mapped in the MPU view or for the MPU itself. |
113 | */ | |
114 | soc { | |
115 | compatible = "ti,omap-infra"; | |
116 | mpu { | |
1306c08a | 117 | compatible = "ti,omap4-mpu"; |
6b5de091 | 118 | ti,hwmods = "mpu"; |
1306c08a | 119 | sram = <&ocmcram>; |
6b5de091 S |
120 | }; |
121 | }; | |
122 | ||
123 | /* | |
124 | * XXX: Use a flat representation of the OMAP3 interconnect. | |
125 | * The real OMAP interconnect network is quite complex. | |
b7ab524b | 126 | * Since it will not bring real advantage to represent that in DT for |
6b5de091 S |
127 | * the moment, just use a fake OCP bus entry to represent the whole bus |
128 | * hierarchy. | |
129 | */ | |
130 | ocp { | |
e7309c26 | 131 | compatible = "ti,omap5-l3-noc", "simple-bus"; |
6b5de091 S |
132 | #address-cells = <1>; |
133 | #size-cells = <1>; | |
134 | ranges; | |
135 | ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3"; | |
20a60eaa SS |
136 | reg = <0x44000000 0x2000>, |
137 | <0x44800000 0x3000>, | |
138 | <0x45000000 0x4000>; | |
8fea7d5a FV |
139 | interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, |
140 | <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; | |
6b5de091 | 141 | |
ed8509ed TK |
142 | l4_cfg: l4@4a000000 { |
143 | compatible = "ti,omap5-l4-cfg", "simple-bus"; | |
144 | #address-cells = <1>; | |
145 | #size-cells = <1>; | |
146 | ranges = <0 0x4a000000 0x22a000>; | |
85dc74e9 | 147 | |
ed8509ed TK |
148 | scm_core: scm@2000 { |
149 | compatible = "ti,omap5-scm-core", "simple-bus"; | |
150 | reg = <0x2000 0x1000>; | |
85dc74e9 | 151 | #address-cells = <1>; |
ed8509ed TK |
152 | #size-cells = <1>; |
153 | ranges = <0 0x2000 0x800>; | |
154 | ||
155 | scm_conf: scm_conf@0 { | |
156 | compatible = "syscon"; | |
157 | reg = <0x0 0x800>; | |
158 | #address-cells = <1>; | |
159 | #size-cells = <1>; | |
160 | }; | |
85dc74e9 TK |
161 | }; |
162 | ||
ed8509ed TK |
163 | scm_padconf_core: scm@2800 { |
164 | compatible = "ti,omap5-scm-padconf-core", | |
165 | "simple-bus"; | |
166 | #address-cells = <1>; | |
167 | #size-cells = <1>; | |
168 | ranges = <0 0x2800 0x800>; | |
169 | ||
170 | omap5_pmx_core: pinmux@40 { | |
171 | compatible = "ti,omap5-padconf", | |
172 | "pinctrl-single"; | |
173 | reg = <0x40 0x01b6>; | |
174 | #address-cells = <1>; | |
175 | #size-cells = <0>; | |
176 | #interrupt-cells = <1>; | |
177 | interrupt-controller; | |
178 | pinctrl-single,register-width = <16>; | |
179 | pinctrl-single,function-mask = <0x7fff>; | |
180 | }; | |
181 | ||
182 | omap5_padconf_global: omap5_padconf_global@5a0 { | |
183 | compatible = "syscon"; | |
184 | reg = <0x5a0 0xec>; | |
185 | #address-cells = <1>; | |
186 | #size-cells = <1>; | |
187 | ||
188 | pbias_regulator: pbias_regulator { | |
189 | compatible = "ti,pbias-omap"; | |
190 | reg = <0x60 0x4>; | |
191 | syscon = <&omap5_padconf_global>; | |
192 | pbias_mmc_reg: pbias_mmc_omap5 { | |
193 | regulator-name = "pbias_mmc_omap5"; | |
194 | regulator-min-microvolt = <1800000>; | |
195 | regulator-max-microvolt = <3000000>; | |
196 | }; | |
197 | }; | |
198 | }; | |
85dc74e9 | 199 | }; |
85dc74e9 | 200 | |
ed8509ed TK |
201 | cm_core_aon: cm_core_aon@4000 { |
202 | compatible = "ti,omap5-cm-core-aon"; | |
203 | reg = <0x4000 0x2000>; | |
85dc74e9 | 204 | |
ed8509ed TK |
205 | cm_core_aon_clocks: clocks { |
206 | #address-cells = <1>; | |
207 | #size-cells = <0>; | |
208 | }; | |
85dc74e9 | 209 | |
ed8509ed TK |
210 | cm_core_aon_clockdomains: clockdomains { |
211 | }; | |
85dc74e9 | 212 | }; |
85dc74e9 | 213 | |
ed8509ed TK |
214 | cm_core: cm_core@8000 { |
215 | compatible = "ti,omap5-cm-core"; | |
216 | reg = <0x8000 0x3000>; | |
85dc74e9 | 217 | |
ed8509ed TK |
218 | cm_core_clocks: clocks { |
219 | #address-cells = <1>; | |
220 | #size-cells = <0>; | |
221 | }; | |
85dc74e9 | 222 | |
ed8509ed TK |
223 | cm_core_clockdomains: clockdomains { |
224 | }; | |
85dc74e9 TK |
225 | }; |
226 | }; | |
227 | ||
ed8509ed TK |
228 | l4_wkup: l4@4ae00000 { |
229 | compatible = "ti,omap5-l4-wkup", "simple-bus"; | |
230 | #address-cells = <1>; | |
231 | #size-cells = <1>; | |
232 | ranges = <0 0x4ae00000 0x2b000>; | |
85dc74e9 | 233 | |
ed8509ed TK |
234 | counter32k: counter@4000 { |
235 | compatible = "ti,omap-counter32k"; | |
236 | reg = <0x4000 0x40>; | |
237 | ti,hwmods = "counter_32k"; | |
85dc74e9 TK |
238 | }; |
239 | ||
ed8509ed TK |
240 | prm: prm@6000 { |
241 | compatible = "ti,omap5-prm"; | |
242 | reg = <0x6000 0x3000>; | |
243 | interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; | |
244 | ||
245 | prm_clocks: clocks { | |
246 | #address-cells = <1>; | |
247 | #size-cells = <0>; | |
248 | }; | |
249 | ||
250 | prm_clockdomains: clockdomains { | |
251 | }; | |
85dc74e9 | 252 | }; |
85dc74e9 | 253 | |
ed8509ed TK |
254 | scrm: scrm@a000 { |
255 | compatible = "ti,omap5-scrm"; | |
256 | reg = <0xa000 0x2000>; | |
3b3132f7 | 257 | |
ed8509ed TK |
258 | scrm_clocks: clocks { |
259 | #address-cells = <1>; | |
260 | #size-cells = <0>; | |
261 | }; | |
5da6a2d5 | 262 | |
ed8509ed TK |
263 | scrm_clockdomains: clockdomains { |
264 | }; | |
265 | }; | |
cd042fe5 | 266 | |
ed8509ed TK |
267 | omap5_pmx_wkup: pinmux@c840 { |
268 | compatible = "ti,omap5-padconf", | |
269 | "pinctrl-single"; | |
270 | reg = <0xc840 0x0038>; | |
271 | #address-cells = <1>; | |
272 | #size-cells = <0>; | |
273 | #interrupt-cells = <1>; | |
274 | interrupt-controller; | |
275 | pinctrl-single,register-width = <16>; | |
276 | pinctrl-single,function-mask = <0x7fff>; | |
cd042fe5 B |
277 | }; |
278 | }; | |
279 | ||
8b9a2810 RN |
280 | ocmcram: ocmcram@40300000 { |
281 | compatible = "mmio-sram"; | |
282 | reg = <0x40300000 0x20000>; /* 128k */ | |
283 | }; | |
284 | ||
2c2dc545 JH |
285 | sdma: dma-controller@4a056000 { |
286 | compatible = "ti,omap4430-sdma"; | |
287 | reg = <0x4a056000 0x1000>; | |
8fea7d5a FV |
288 | interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, |
289 | <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, | |
290 | <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, | |
291 | <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; | |
2c2dc545 | 292 | #dma-cells = <1>; |
951c1c04 PU |
293 | dma-channels = <32>; |
294 | dma-requests = <127>; | |
2c2dc545 JH |
295 | }; |
296 | ||
6b5de091 S |
297 | gpio1: gpio@4ae10000 { |
298 | compatible = "ti,omap4-gpio"; | |
f4b224f2 | 299 | reg = <0x4ae10000 0x200>; |
8fea7d5a | 300 | interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; |
6b5de091 | 301 | ti,hwmods = "gpio1"; |
e4b9b9f3 | 302 | ti,gpio-always-on; |
6b5de091 S |
303 | gpio-controller; |
304 | #gpio-cells = <2>; | |
305 | interrupt-controller; | |
ff5c9059 | 306 | #interrupt-cells = <2>; |
6b5de091 S |
307 | }; |
308 | ||
309 | gpio2: gpio@48055000 { | |
310 | compatible = "ti,omap4-gpio"; | |
f4b224f2 | 311 | reg = <0x48055000 0x200>; |
8fea7d5a | 312 | interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; |
6b5de091 S |
313 | ti,hwmods = "gpio2"; |
314 | gpio-controller; | |
315 | #gpio-cells = <2>; | |
316 | interrupt-controller; | |
ff5c9059 | 317 | #interrupt-cells = <2>; |
6b5de091 S |
318 | }; |
319 | ||
320 | gpio3: gpio@48057000 { | |
321 | compatible = "ti,omap4-gpio"; | |
f4b224f2 | 322 | reg = <0x48057000 0x200>; |
8fea7d5a | 323 | interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; |
6b5de091 S |
324 | ti,hwmods = "gpio3"; |
325 | gpio-controller; | |
326 | #gpio-cells = <2>; | |
327 | interrupt-controller; | |
ff5c9059 | 328 | #interrupt-cells = <2>; |
6b5de091 S |
329 | }; |
330 | ||
331 | gpio4: gpio@48059000 { | |
332 | compatible = "ti,omap4-gpio"; | |
f4b224f2 | 333 | reg = <0x48059000 0x200>; |
8fea7d5a | 334 | interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; |
6b5de091 S |
335 | ti,hwmods = "gpio4"; |
336 | gpio-controller; | |
337 | #gpio-cells = <2>; | |
338 | interrupt-controller; | |
ff5c9059 | 339 | #interrupt-cells = <2>; |
6b5de091 S |
340 | }; |
341 | ||
342 | gpio5: gpio@4805b000 { | |
343 | compatible = "ti,omap4-gpio"; | |
f4b224f2 | 344 | reg = <0x4805b000 0x200>; |
8fea7d5a | 345 | interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; |
6b5de091 S |
346 | ti,hwmods = "gpio5"; |
347 | gpio-controller; | |
348 | #gpio-cells = <2>; | |
349 | interrupt-controller; | |
ff5c9059 | 350 | #interrupt-cells = <2>; |
6b5de091 S |
351 | }; |
352 | ||
353 | gpio6: gpio@4805d000 { | |
354 | compatible = "ti,omap4-gpio"; | |
f4b224f2 | 355 | reg = <0x4805d000 0x200>; |
8fea7d5a | 356 | interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; |
6b5de091 S |
357 | ti,hwmods = "gpio6"; |
358 | gpio-controller; | |
359 | #gpio-cells = <2>; | |
360 | interrupt-controller; | |
ff5c9059 | 361 | #interrupt-cells = <2>; |
6b5de091 S |
362 | }; |
363 | ||
364 | gpio7: gpio@48051000 { | |
365 | compatible = "ti,omap4-gpio"; | |
f4b224f2 | 366 | reg = <0x48051000 0x200>; |
8fea7d5a | 367 | interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; |
6b5de091 S |
368 | ti,hwmods = "gpio7"; |
369 | gpio-controller; | |
370 | #gpio-cells = <2>; | |
371 | interrupt-controller; | |
ff5c9059 | 372 | #interrupt-cells = <2>; |
6b5de091 S |
373 | }; |
374 | ||
375 | gpio8: gpio@48053000 { | |
376 | compatible = "ti,omap4-gpio"; | |
f4b224f2 | 377 | reg = <0x48053000 0x200>; |
8fea7d5a | 378 | interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; |
6b5de091 S |
379 | ti,hwmods = "gpio8"; |
380 | gpio-controller; | |
381 | #gpio-cells = <2>; | |
382 | interrupt-controller; | |
ff5c9059 | 383 | #interrupt-cells = <2>; |
6b5de091 S |
384 | }; |
385 | ||
1c7dbb55 JH |
386 | gpmc: gpmc@50000000 { |
387 | compatible = "ti,omap4430-gpmc"; | |
388 | reg = <0x50000000 0x1000>; | |
389 | #address-cells = <2>; | |
390 | #size-cells = <1>; | |
8fea7d5a | 391 | interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; |
1c7dbb55 JH |
392 | gpmc,num-cs = <8>; |
393 | gpmc,num-waitpins = <4>; | |
394 | ti,hwmods = "gpmc"; | |
7b8b6af1 FV |
395 | clocks = <&l3_iclk_div>; |
396 | clock-names = "fck"; | |
1c7dbb55 JH |
397 | }; |
398 | ||
6e6a9a50 SP |
399 | i2c1: i2c@48070000 { |
400 | compatible = "ti,omap4-i2c"; | |
d7118bbd | 401 | reg = <0x48070000 0x100>; |
8fea7d5a | 402 | interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; |
6e6a9a50 SP |
403 | #address-cells = <1>; |
404 | #size-cells = <0>; | |
405 | ti,hwmods = "i2c1"; | |
406 | }; | |
407 | ||
408 | i2c2: i2c@48072000 { | |
409 | compatible = "ti,omap4-i2c"; | |
d7118bbd | 410 | reg = <0x48072000 0x100>; |
8fea7d5a | 411 | interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; |
6e6a9a50 SP |
412 | #address-cells = <1>; |
413 | #size-cells = <0>; | |
414 | ti,hwmods = "i2c2"; | |
415 | }; | |
416 | ||
417 | i2c3: i2c@48060000 { | |
418 | compatible = "ti,omap4-i2c"; | |
d7118bbd | 419 | reg = <0x48060000 0x100>; |
8fea7d5a | 420 | interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; |
6e6a9a50 SP |
421 | #address-cells = <1>; |
422 | #size-cells = <0>; | |
423 | ti,hwmods = "i2c3"; | |
424 | }; | |
425 | ||
d7118bbd | 426 | i2c4: i2c@4807a000 { |
6e6a9a50 | 427 | compatible = "ti,omap4-i2c"; |
d7118bbd | 428 | reg = <0x4807a000 0x100>; |
8fea7d5a | 429 | interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; |
6e6a9a50 SP |
430 | #address-cells = <1>; |
431 | #size-cells = <0>; | |
432 | ti,hwmods = "i2c4"; | |
433 | }; | |
434 | ||
d7118bbd | 435 | i2c5: i2c@4807c000 { |
6e6a9a50 | 436 | compatible = "ti,omap4-i2c"; |
d7118bbd | 437 | reg = <0x4807c000 0x100>; |
8fea7d5a | 438 | interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; |
6e6a9a50 SP |
439 | #address-cells = <1>; |
440 | #size-cells = <0>; | |
441 | ti,hwmods = "i2c5"; | |
442 | }; | |
443 | ||
fe0e09e4 SA |
444 | hwspinlock: spinlock@4a0f6000 { |
445 | compatible = "ti,omap4-hwspinlock"; | |
446 | reg = <0x4a0f6000 0x1000>; | |
447 | ti,hwmods = "spinlock"; | |
34054213 | 448 | #hwlock-cells = <1>; |
fe0e09e4 SA |
449 | }; |
450 | ||
43286b11 FB |
451 | mcspi1: spi@48098000 { |
452 | compatible = "ti,omap4-mcspi"; | |
453 | reg = <0x48098000 0x200>; | |
8fea7d5a | 454 | interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; |
43286b11 FB |
455 | #address-cells = <1>; |
456 | #size-cells = <0>; | |
457 | ti,hwmods = "mcspi1"; | |
458 | ti,spi-num-cs = <4>; | |
2c2dc545 JH |
459 | dmas = <&sdma 35>, |
460 | <&sdma 36>, | |
461 | <&sdma 37>, | |
462 | <&sdma 38>, | |
463 | <&sdma 39>, | |
464 | <&sdma 40>, | |
465 | <&sdma 41>, | |
466 | <&sdma 42>; | |
467 | dma-names = "tx0", "rx0", "tx1", "rx1", | |
468 | "tx2", "rx2", "tx3", "rx3"; | |
43286b11 FB |
469 | }; |
470 | ||
471 | mcspi2: spi@4809a000 { | |
472 | compatible = "ti,omap4-mcspi"; | |
473 | reg = <0x4809a000 0x200>; | |
8fea7d5a | 474 | interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; |
43286b11 FB |
475 | #address-cells = <1>; |
476 | #size-cells = <0>; | |
477 | ti,hwmods = "mcspi2"; | |
478 | ti,spi-num-cs = <2>; | |
2c2dc545 JH |
479 | dmas = <&sdma 43>, |
480 | <&sdma 44>, | |
481 | <&sdma 45>, | |
482 | <&sdma 46>; | |
483 | dma-names = "tx0", "rx0", "tx1", "rx1"; | |
43286b11 FB |
484 | }; |
485 | ||
486 | mcspi3: spi@480b8000 { | |
487 | compatible = "ti,omap4-mcspi"; | |
488 | reg = <0x480b8000 0x200>; | |
8fea7d5a | 489 | interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; |
43286b11 FB |
490 | #address-cells = <1>; |
491 | #size-cells = <0>; | |
492 | ti,hwmods = "mcspi3"; | |
493 | ti,spi-num-cs = <2>; | |
2c2dc545 JH |
494 | dmas = <&sdma 15>, <&sdma 16>; |
495 | dma-names = "tx0", "rx0"; | |
43286b11 FB |
496 | }; |
497 | ||
498 | mcspi4: spi@480ba000 { | |
499 | compatible = "ti,omap4-mcspi"; | |
500 | reg = <0x480ba000 0x200>; | |
8fea7d5a | 501 | interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; |
43286b11 FB |
502 | #address-cells = <1>; |
503 | #size-cells = <0>; | |
504 | ti,hwmods = "mcspi4"; | |
505 | ti,spi-num-cs = <1>; | |
2c2dc545 JH |
506 | dmas = <&sdma 70>, <&sdma 71>; |
507 | dma-names = "tx0", "rx0"; | |
43286b11 FB |
508 | }; |
509 | ||
6b5de091 S |
510 | uart1: serial@4806a000 { |
511 | compatible = "ti,omap4-uart"; | |
8e80f660 | 512 | reg = <0x4806a000 0x100>; |
7136d457 | 513 | interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; |
6b5de091 S |
514 | ti,hwmods = "uart1"; |
515 | clock-frequency = <48000000>; | |
516 | }; | |
517 | ||
518 | uart2: serial@4806c000 { | |
519 | compatible = "ti,omap4-uart"; | |
8e80f660 | 520 | reg = <0x4806c000 0x100>; |
7136d457 | 521 | interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; |
6b5de091 S |
522 | ti,hwmods = "uart2"; |
523 | clock-frequency = <48000000>; | |
524 | }; | |
525 | ||
526 | uart3: serial@48020000 { | |
527 | compatible = "ti,omap4-uart"; | |
8e80f660 | 528 | reg = <0x48020000 0x100>; |
7136d457 | 529 | interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; |
6b5de091 S |
530 | ti,hwmods = "uart3"; |
531 | clock-frequency = <48000000>; | |
532 | }; | |
533 | ||
534 | uart4: serial@4806e000 { | |
535 | compatible = "ti,omap4-uart"; | |
8e80f660 | 536 | reg = <0x4806e000 0x100>; |
7136d457 | 537 | interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; |
6b5de091 S |
538 | ti,hwmods = "uart4"; |
539 | clock-frequency = <48000000>; | |
540 | }; | |
541 | ||
542 | uart5: serial@48066000 { | |
8e80f660 SG |
543 | compatible = "ti,omap4-uart"; |
544 | reg = <0x48066000 0x100>; | |
7136d457 | 545 | interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; |
6b5de091 S |
546 | ti,hwmods = "uart5"; |
547 | clock-frequency = <48000000>; | |
548 | }; | |
549 | ||
550 | uart6: serial@48068000 { | |
8e80f660 SG |
551 | compatible = "ti,omap4-uart"; |
552 | reg = <0x48068000 0x100>; | |
7136d457 | 553 | interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; |
6b5de091 S |
554 | ti,hwmods = "uart6"; |
555 | clock-frequency = <48000000>; | |
556 | }; | |
5dd18b01 B |
557 | |
558 | mmc1: mmc@4809c000 { | |
559 | compatible = "ti,omap4-hsmmc"; | |
9a642362 | 560 | reg = <0x4809c000 0x400>; |
8fea7d5a | 561 | interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; |
5dd18b01 B |
562 | ti,hwmods = "mmc1"; |
563 | ti,dual-volt; | |
564 | ti,needs-special-reset; | |
2c2dc545 JH |
565 | dmas = <&sdma 61>, <&sdma 62>; |
566 | dma-names = "tx", "rx"; | |
cd042fe5 | 567 | pbias-supply = <&pbias_mmc_reg>; |
5dd18b01 B |
568 | }; |
569 | ||
570 | mmc2: mmc@480b4000 { | |
571 | compatible = "ti,omap4-hsmmc"; | |
9a642362 | 572 | reg = <0x480b4000 0x400>; |
8fea7d5a | 573 | interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; |
5dd18b01 B |
574 | ti,hwmods = "mmc2"; |
575 | ti,needs-special-reset; | |
2c2dc545 JH |
576 | dmas = <&sdma 47>, <&sdma 48>; |
577 | dma-names = "tx", "rx"; | |
5dd18b01 B |
578 | }; |
579 | ||
580 | mmc3: mmc@480ad000 { | |
581 | compatible = "ti,omap4-hsmmc"; | |
9a642362 | 582 | reg = <0x480ad000 0x400>; |
8fea7d5a | 583 | interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; |
5dd18b01 B |
584 | ti,hwmods = "mmc3"; |
585 | ti,needs-special-reset; | |
2c2dc545 JH |
586 | dmas = <&sdma 77>, <&sdma 78>; |
587 | dma-names = "tx", "rx"; | |
5dd18b01 B |
588 | }; |
589 | ||
590 | mmc4: mmc@480d1000 { | |
591 | compatible = "ti,omap4-hsmmc"; | |
9a642362 | 592 | reg = <0x480d1000 0x400>; |
8fea7d5a | 593 | interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; |
5dd18b01 B |
594 | ti,hwmods = "mmc4"; |
595 | ti,needs-special-reset; | |
2c2dc545 JH |
596 | dmas = <&sdma 57>, <&sdma 58>; |
597 | dma-names = "tx", "rx"; | |
5dd18b01 B |
598 | }; |
599 | ||
600 | mmc5: mmc@480d5000 { | |
601 | compatible = "ti,omap4-hsmmc"; | |
9a642362 | 602 | reg = <0x480d5000 0x400>; |
8fea7d5a | 603 | interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; |
5dd18b01 B |
604 | ti,hwmods = "mmc5"; |
605 | ti,needs-special-reset; | |
2c2dc545 JH |
606 | dmas = <&sdma 59>, <&sdma 60>; |
607 | dma-names = "tx", "rx"; | |
5dd18b01 | 608 | }; |
5449fbc2 | 609 | |
2dcfa56e SA |
610 | mmu_dsp: mmu@4a066000 { |
611 | compatible = "ti,omap4-iommu"; | |
612 | reg = <0x4a066000 0x100>; | |
613 | interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; | |
614 | ti,hwmods = "mmu_dsp"; | |
c1b5d0f6 | 615 | #iommu-cells = <0>; |
2dcfa56e SA |
616 | }; |
617 | ||
618 | mmu_ipu: mmu@55082000 { | |
619 | compatible = "ti,omap4-iommu"; | |
620 | reg = <0x55082000 0x100>; | |
621 | interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; | |
622 | ti,hwmods = "mmu_ipu"; | |
c1b5d0f6 | 623 | #iommu-cells = <0>; |
2dcfa56e SA |
624 | ti,iommu-bus-err-back; |
625 | }; | |
626 | ||
5449fbc2 SP |
627 | keypad: keypad@4ae1c000 { |
628 | compatible = "ti,omap4-keypad"; | |
8cc8b89f | 629 | reg = <0x4ae1c000 0x400>; |
5449fbc2 SP |
630 | ti,hwmods = "kbd"; |
631 | }; | |
ffd5db24 | 632 | |
cbb57f07 PU |
633 | mcpdm: mcpdm@40132000 { |
634 | compatible = "ti,omap4-mcpdm"; | |
635 | reg = <0x40132000 0x7f>, /* MPU private access */ | |
636 | <0x49032000 0x7f>; /* L3 Interconnect */ | |
637 | reg-names = "mpu", "dma"; | |
8fea7d5a | 638 | interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; |
cbb57f07 | 639 | ti,hwmods = "mcpdm"; |
4e4ead73 SG |
640 | dmas = <&sdma 65>, |
641 | <&sdma 66>; | |
642 | dma-names = "up_link", "dn_link"; | |
f15534ea | 643 | status = "disabled"; |
cbb57f07 PU |
644 | }; |
645 | ||
646 | dmic: dmic@4012e000 { | |
647 | compatible = "ti,omap4-dmic"; | |
648 | reg = <0x4012e000 0x7f>, /* MPU private access */ | |
649 | <0x4902e000 0x7f>; /* L3 Interconnect */ | |
650 | reg-names = "mpu", "dma"; | |
8fea7d5a | 651 | interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; |
cbb57f07 | 652 | ti,hwmods = "dmic"; |
4e4ead73 SG |
653 | dmas = <&sdma 67>; |
654 | dma-names = "up_link"; | |
f15534ea | 655 | status = "disabled"; |
cbb57f07 PU |
656 | }; |
657 | ||
ffd5db24 PU |
658 | mcbsp1: mcbsp@40122000 { |
659 | compatible = "ti,omap4-mcbsp"; | |
660 | reg = <0x40122000 0xff>, /* MPU private access */ | |
661 | <0x49022000 0xff>; /* L3 Interconnect */ | |
662 | reg-names = "mpu", "dma"; | |
8fea7d5a | 663 | interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; |
ffd5db24 | 664 | interrupt-names = "common"; |
ffd5db24 PU |
665 | ti,buffer-size = <128>; |
666 | ti,hwmods = "mcbsp1"; | |
4e4ead73 SG |
667 | dmas = <&sdma 33>, |
668 | <&sdma 34>; | |
669 | dma-names = "tx", "rx"; | |
f15534ea | 670 | status = "disabled"; |
ffd5db24 PU |
671 | }; |
672 | ||
673 | mcbsp2: mcbsp@40124000 { | |
674 | compatible = "ti,omap4-mcbsp"; | |
675 | reg = <0x40124000 0xff>, /* MPU private access */ | |
676 | <0x49024000 0xff>; /* L3 Interconnect */ | |
677 | reg-names = "mpu", "dma"; | |
8fea7d5a | 678 | interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; |
ffd5db24 | 679 | interrupt-names = "common"; |
ffd5db24 PU |
680 | ti,buffer-size = <128>; |
681 | ti,hwmods = "mcbsp2"; | |
4e4ead73 SG |
682 | dmas = <&sdma 17>, |
683 | <&sdma 18>; | |
684 | dma-names = "tx", "rx"; | |
f15534ea | 685 | status = "disabled"; |
ffd5db24 PU |
686 | }; |
687 | ||
688 | mcbsp3: mcbsp@40126000 { | |
689 | compatible = "ti,omap4-mcbsp"; | |
690 | reg = <0x40126000 0xff>, /* MPU private access */ | |
691 | <0x49026000 0xff>; /* L3 Interconnect */ | |
692 | reg-names = "mpu", "dma"; | |
8fea7d5a | 693 | interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; |
ffd5db24 | 694 | interrupt-names = "common"; |
ffd5db24 PU |
695 | ti,buffer-size = <128>; |
696 | ti,hwmods = "mcbsp3"; | |
4e4ead73 SG |
697 | dmas = <&sdma 19>, |
698 | <&sdma 20>; | |
699 | dma-names = "tx", "rx"; | |
f15534ea | 700 | status = "disabled"; |
ffd5db24 | 701 | }; |
df692a92 | 702 | |
84d89c31 SA |
703 | mailbox: mailbox@4a0f4000 { |
704 | compatible = "ti,omap4-mailbox"; | |
705 | reg = <0x4a0f4000 0x200>; | |
706 | interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; | |
707 | ti,hwmods = "mailbox"; | |
24df0453 | 708 | #mbox-cells = <1>; |
41ffada1 SA |
709 | ti,mbox-num-users = <3>; |
710 | ti,mbox-num-fifos = <8>; | |
d27704d1 SA |
711 | mbox_ipu: mbox_ipu { |
712 | ti,mbox-tx = <0 0 0>; | |
713 | ti,mbox-rx = <1 0 0>; | |
714 | }; | |
715 | mbox_dsp: mbox_dsp { | |
716 | ti,mbox-tx = <3 0 0>; | |
717 | ti,mbox-rx = <2 0 0>; | |
718 | }; | |
84d89c31 SA |
719 | }; |
720 | ||
df692a92 | 721 | timer1: timer@4ae18000 { |
002e1ec5 | 722 | compatible = "ti,omap5430-timer"; |
df692a92 | 723 | reg = <0x4ae18000 0x80>; |
8fea7d5a | 724 | interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; |
df692a92 JH |
725 | ti,hwmods = "timer1"; |
726 | ti,timer-alwon; | |
727 | }; | |
728 | ||
729 | timer2: timer@48032000 { | |
002e1ec5 | 730 | compatible = "ti,omap5430-timer"; |
df692a92 | 731 | reg = <0x48032000 0x80>; |
8fea7d5a | 732 | interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; |
df692a92 JH |
733 | ti,hwmods = "timer2"; |
734 | }; | |
735 | ||
736 | timer3: timer@48034000 { | |
002e1ec5 | 737 | compatible = "ti,omap5430-timer"; |
df692a92 | 738 | reg = <0x48034000 0x80>; |
8fea7d5a | 739 | interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; |
df692a92 JH |
740 | ti,hwmods = "timer3"; |
741 | }; | |
742 | ||
743 | timer4: timer@48036000 { | |
002e1ec5 | 744 | compatible = "ti,omap5430-timer"; |
df692a92 | 745 | reg = <0x48036000 0x80>; |
8fea7d5a | 746 | interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; |
df692a92 JH |
747 | ti,hwmods = "timer4"; |
748 | }; | |
749 | ||
750 | timer5: timer@40138000 { | |
002e1ec5 | 751 | compatible = "ti,omap5430-timer"; |
df692a92 JH |
752 | reg = <0x40138000 0x80>, |
753 | <0x49038000 0x80>; | |
8fea7d5a | 754 | interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; |
df692a92 JH |
755 | ti,hwmods = "timer5"; |
756 | ti,timer-dsp; | |
8341613a | 757 | ti,timer-pwm; |
df692a92 JH |
758 | }; |
759 | ||
760 | timer6: timer@4013a000 { | |
002e1ec5 | 761 | compatible = "ti,omap5430-timer"; |
df692a92 JH |
762 | reg = <0x4013a000 0x80>, |
763 | <0x4903a000 0x80>; | |
8fea7d5a | 764 | interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; |
df692a92 JH |
765 | ti,hwmods = "timer6"; |
766 | ti,timer-dsp; | |
767 | ti,timer-pwm; | |
768 | }; | |
769 | ||
770 | timer7: timer@4013c000 { | |
002e1ec5 | 771 | compatible = "ti,omap5430-timer"; |
df692a92 JH |
772 | reg = <0x4013c000 0x80>, |
773 | <0x4903c000 0x80>; | |
8fea7d5a | 774 | interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; |
df692a92 JH |
775 | ti,hwmods = "timer7"; |
776 | ti,timer-dsp; | |
777 | }; | |
778 | ||
779 | timer8: timer@4013e000 { | |
002e1ec5 | 780 | compatible = "ti,omap5430-timer"; |
df692a92 JH |
781 | reg = <0x4013e000 0x80>, |
782 | <0x4903e000 0x80>; | |
8fea7d5a | 783 | interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; |
df692a92 JH |
784 | ti,hwmods = "timer8"; |
785 | ti,timer-dsp; | |
786 | ti,timer-pwm; | |
787 | }; | |
788 | ||
789 | timer9: timer@4803e000 { | |
002e1ec5 | 790 | compatible = "ti,omap5430-timer"; |
df692a92 | 791 | reg = <0x4803e000 0x80>; |
8fea7d5a | 792 | interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; |
df692a92 | 793 | ti,hwmods = "timer9"; |
8341613a | 794 | ti,timer-pwm; |
df692a92 JH |
795 | }; |
796 | ||
797 | timer10: timer@48086000 { | |
002e1ec5 | 798 | compatible = "ti,omap5430-timer"; |
df692a92 | 799 | reg = <0x48086000 0x80>; |
8fea7d5a | 800 | interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; |
df692a92 | 801 | ti,hwmods = "timer10"; |
8341613a | 802 | ti,timer-pwm; |
df692a92 JH |
803 | }; |
804 | ||
805 | timer11: timer@48088000 { | |
002e1ec5 | 806 | compatible = "ti,omap5430-timer"; |
df692a92 | 807 | reg = <0x48088000 0x80>; |
8fea7d5a | 808 | interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; |
df692a92 JH |
809 | ti,hwmods = "timer11"; |
810 | ti,timer-pwm; | |
811 | }; | |
e6900ddf | 812 | |
55452197 LV |
813 | wdt2: wdt@4ae14000 { |
814 | compatible = "ti,omap5-wdt", "ti,omap3-wdt"; | |
815 | reg = <0x4ae14000 0x80>; | |
8fea7d5a | 816 | interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; |
55452197 LV |
817 | ti,hwmods = "wd_timer2"; |
818 | }; | |
819 | ||
1a5fe3ca AT |
820 | dmm@4e000000 { |
821 | compatible = "ti,omap5-dmm"; | |
822 | reg = <0x4e000000 0x800>; | |
823 | interrupts = <0 113 0x4>; | |
824 | ti,hwmods = "dmm"; | |
825 | }; | |
826 | ||
8906d654 | 827 | emif1: emif@4c000000 { |
e6900ddf LV |
828 | compatible = "ti,emif-4d5"; |
829 | ti,hwmods = "emif1"; | |
f12ecbe2 | 830 | ti,no-idle-on-init; |
e6900ddf LV |
831 | phy-type = <2>; /* DDR PHY type: Intelli PHY */ |
832 | reg = <0x4c000000 0x400>; | |
8fea7d5a | 833 | interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; |
e6900ddf LV |
834 | hw-caps-read-idle-ctrl; |
835 | hw-caps-ll-interface; | |
836 | hw-caps-temp-alert; | |
837 | }; | |
838 | ||
8906d654 | 839 | emif2: emif@4d000000 { |
e6900ddf LV |
840 | compatible = "ti,emif-4d5"; |
841 | ti,hwmods = "emif2"; | |
f12ecbe2 | 842 | ti,no-idle-on-init; |
e6900ddf LV |
843 | phy-type = <2>; /* DDR PHY type: Intelli PHY */ |
844 | reg = <0x4d000000 0x400>; | |
8fea7d5a | 845 | interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; |
e6900ddf LV |
846 | hw-caps-read-idle-ctrl; |
847 | hw-caps-ll-interface; | |
848 | hw-caps-temp-alert; | |
849 | }; | |
fedc428e | 850 | |
b297c292 RQ |
851 | omap_control_usb2phy: control-phy@4a002300 { |
852 | compatible = "ti,control-phy-usb2"; | |
853 | reg = <0x4a002300 0x4>; | |
854 | reg-names = "power"; | |
855 | }; | |
856 | ||
857 | omap_control_usb3phy: control-phy@4a002370 { | |
858 | compatible = "ti,control-phy-pipe3"; | |
859 | reg = <0x4a002370 0x4>; | |
860 | reg-names = "power"; | |
fedc428e | 861 | }; |
e9831967 | 862 | |
e3a412c9 | 863 | usb3: omap_dwc3@4a020000 { |
72f6f957 KVA |
864 | compatible = "ti,dwc3"; |
865 | ti,hwmods = "usb_otg_ss"; | |
6f61ee23 | 866 | reg = <0x4a020000 0x10000>; |
8fea7d5a | 867 | interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; |
72f6f957 KVA |
868 | #address-cells = <1>; |
869 | #size-cells = <1>; | |
870 | utmi-mode = <2>; | |
871 | ranges; | |
872 | dwc3@4a030000 { | |
22a5aa17 | 873 | compatible = "snps,dwc3"; |
6f61ee23 | 874 | reg = <0x4a030000 0x10000>; |
8fea7d5a | 875 | interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; |
073addc8 KVA |
876 | phys = <&usb2_phy>, <&usb3_phy>; |
877 | phy-names = "usb2-phy", "usb3-phy"; | |
c47ee6ee | 878 | dr_mode = "peripheral"; |
72f6f957 KVA |
879 | tx-fifo-resize; |
880 | }; | |
881 | }; | |
882 | ||
b6731f78 | 883 | ocp2scp@4a080000 { |
e9831967 KVA |
884 | compatible = "ti,omap-ocp2scp"; |
885 | #address-cells = <1>; | |
886 | #size-cells = <1>; | |
b6731f78 | 887 | reg = <0x4a080000 0x20>; |
e9831967 KVA |
888 | ranges; |
889 | ti,hwmods = "ocp2scp1"; | |
ae6a32d2 KVA |
890 | usb2_phy: usb2phy@4a084000 { |
891 | compatible = "ti,omap-usb2"; | |
892 | reg = <0x4a084000 0x7c>; | |
b297c292 | 893 | ctrl-module = <&omap_control_usb2phy>; |
c65d0ad5 RQ |
894 | clocks = <&usb_phy_cm_clk32k>, <&usb_otg_ss_refclk960m>; |
895 | clock-names = "wkupclk", "refclk"; | |
073addc8 | 896 | #phy-cells = <0>; |
ae6a32d2 KVA |
897 | }; |
898 | ||
899 | usb3_phy: usb3phy@4a084400 { | |
900 | compatible = "ti,omap-usb3"; | |
901 | reg = <0x4a084400 0x80>, | |
902 | <0x4a084800 0x64>, | |
903 | <0x4a084c00 0x40>; | |
904 | reg-names = "phy_rx", "phy_tx", "pll_ctrl"; | |
b297c292 | 905 | ctrl-module = <&omap_control_usb3phy>; |
ada76576 RQ |
906 | clocks = <&usb_phy_cm_clk32k>, |
907 | <&sys_clkin>, | |
908 | <&usb_otg_ss_refclk960m>; | |
909 | clock-names = "wkupclk", | |
910 | "sysclk", | |
911 | "refclk"; | |
073addc8 | 912 | #phy-cells = <0>; |
ae6a32d2 | 913 | }; |
e9831967 | 914 | }; |
ed7f8e8a RQ |
915 | |
916 | usbhstll: usbhstll@4a062000 { | |
917 | compatible = "ti,usbhs-tll"; | |
918 | reg = <0x4a062000 0x1000>; | |
919 | interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; | |
920 | ti,hwmods = "usb_tll_hs"; | |
921 | }; | |
922 | ||
923 | usbhshost: usbhshost@4a064000 { | |
924 | compatible = "ti,usbhs-host"; | |
925 | reg = <0x4a064000 0x800>; | |
926 | ti,hwmods = "usb_host_hs"; | |
927 | #address-cells = <1>; | |
928 | #size-cells = <1>; | |
929 | ranges; | |
051fc06d RQ |
930 | clocks = <&l3init_60m_fclk>, |
931 | <&xclk60mhsp1_ck>, | |
932 | <&xclk60mhsp2_ck>; | |
933 | clock-names = "refclk_60m_int", | |
934 | "refclk_60m_ext_p1", | |
935 | "refclk_60m_ext_p2"; | |
ed7f8e8a RQ |
936 | |
937 | usbhsohci: ohci@4a064800 { | |
a2525e54 | 938 | compatible = "ti,ohci-omap3"; |
ed7f8e8a | 939 | reg = <0x4a064800 0x400>; |
ed7f8e8a RQ |
940 | interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; |
941 | }; | |
942 | ||
943 | usbhsehci: ehci@4a064c00 { | |
a2525e54 | 944 | compatible = "ti,ehci-omap"; |
ed7f8e8a | 945 | reg = <0x4a064c00 0x400>; |
ed7f8e8a RQ |
946 | interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; |
947 | }; | |
948 | }; | |
cbad26db | 949 | |
1b761fc5 | 950 | bandgap: bandgap@4a0021e0 { |
cbad26db EV |
951 | reg = <0x4a0021e0 0xc |
952 | 0x4a00232c 0xc | |
953 | 0x4a002380 0x2c | |
954 | 0x4a0023C0 0x3c>; | |
955 | interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; | |
956 | compatible = "ti,omap5430-bandgap"; | |
1b761fc5 EV |
957 | |
958 | #thermal-sensor-cells = <1>; | |
cbad26db | 959 | }; |
4f82952c B |
960 | |
961 | omap_control_sata: control-phy@4a002374 { | |
962 | compatible = "ti,control-phy-pipe3"; | |
963 | reg = <0x4a002374 0x4>; | |
964 | reg-names = "power"; | |
965 | clocks = <&sys_clkin>; | |
966 | clock-names = "sysclk"; | |
967 | }; | |
968 | ||
969 | /* OCP2SCP3 */ | |
970 | ocp2scp@4a090000 { | |
971 | compatible = "ti,omap-ocp2scp"; | |
972 | #address-cells = <1>; | |
973 | #size-cells = <1>; | |
974 | reg = <0x4a090000 0x20>; | |
975 | ranges; | |
976 | ti,hwmods = "ocp2scp3"; | |
977 | sata_phy: phy@4a096000 { | |
978 | compatible = "ti,phy-pipe3-sata"; | |
979 | reg = <0x4A096000 0x80>, /* phy_rx */ | |
980 | <0x4A096400 0x64>, /* phy_tx */ | |
981 | <0x4A096800 0x40>; /* pll_ctrl */ | |
982 | reg-names = "phy_rx", "phy_tx", "pll_ctrl"; | |
983 | ctrl-module = <&omap_control_sata>; | |
a0182724 RQ |
984 | clocks = <&sys_clkin>, <&sata_ref_clk>; |
985 | clock-names = "sysclk", "refclk"; | |
4f82952c B |
986 | #phy-cells = <0>; |
987 | }; | |
988 | }; | |
989 | ||
990 | sata: sata@4a141100 { | |
991 | compatible = "snps,dwc-ahci"; | |
992 | reg = <0x4a140000 0x1100>, <0x4a141100 0x7>; | |
993 | interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; | |
994 | phys = <&sata_phy>; | |
995 | phy-names = "sata-phy"; | |
996 | clocks = <&sata_ref_clk>; | |
997 | ti,hwmods = "sata"; | |
998 | }; | |
999 | ||
e7585c4f TV |
1000 | dss: dss@58000000 { |
1001 | compatible = "ti,omap5-dss"; | |
1002 | reg = <0x58000000 0x80>; | |
1003 | status = "disabled"; | |
1004 | ti,hwmods = "dss_core"; | |
1005 | clocks = <&dss_dss_clk>; | |
1006 | clock-names = "fck"; | |
1007 | #address-cells = <1>; | |
1008 | #size-cells = <1>; | |
1009 | ranges; | |
1010 | ||
1011 | dispc@58001000 { | |
1012 | compatible = "ti,omap5-dispc"; | |
1013 | reg = <0x58001000 0x1000>; | |
1014 | interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; | |
1015 | ti,hwmods = "dss_dispc"; | |
1016 | clocks = <&dss_dss_clk>; | |
1017 | clock-names = "fck"; | |
1018 | }; | |
1019 | ||
84ace674 TV |
1020 | rfbi: encoder@58002000 { |
1021 | compatible = "ti,omap5-rfbi"; | |
1022 | reg = <0x58002000 0x100>; | |
1023 | status = "disabled"; | |
1024 | ti,hwmods = "dss_rfbi"; | |
1025 | clocks = <&dss_dss_clk>, <&l3_iclk_div>; | |
1026 | clock-names = "fck", "ick"; | |
1027 | }; | |
1028 | ||
e7585c4f TV |
1029 | dsi1: encoder@58004000 { |
1030 | compatible = "ti,omap5-dsi"; | |
1031 | reg = <0x58004000 0x200>, | |
1032 | <0x58004200 0x40>, | |
1033 | <0x58004300 0x40>; | |
1034 | reg-names = "proto", "phy", "pll"; | |
1035 | interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; | |
1036 | status = "disabled"; | |
1037 | ti,hwmods = "dss_dsi1"; | |
1038 | clocks = <&dss_dss_clk>, <&dss_sys_clk>; | |
1039 | clock-names = "fck", "sys_clk"; | |
1040 | }; | |
1041 | ||
1042 | dsi2: encoder@58005000 { | |
1043 | compatible = "ti,omap5-dsi"; | |
1044 | reg = <0x58009000 0x200>, | |
1045 | <0x58009200 0x40>, | |
1046 | <0x58009300 0x40>; | |
1047 | reg-names = "proto", "phy", "pll"; | |
1048 | interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; | |
1049 | status = "disabled"; | |
1050 | ti,hwmods = "dss_dsi2"; | |
1051 | clocks = <&dss_dss_clk>, <&dss_sys_clk>; | |
1052 | clock-names = "fck", "sys_clk"; | |
1053 | }; | |
1054 | ||
1055 | hdmi: encoder@58060000 { | |
1056 | compatible = "ti,omap5-hdmi"; | |
1057 | reg = <0x58040000 0x200>, | |
1058 | <0x58040200 0x80>, | |
1059 | <0x58040300 0x80>, | |
1060 | <0x58060000 0x19000>; | |
1061 | reg-names = "wp", "pll", "phy", "core"; | |
1062 | interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; | |
1063 | status = "disabled"; | |
1064 | ti,hwmods = "dss_hdmi"; | |
1065 | clocks = <&dss_48mhz_clk>, <&dss_sys_clk>; | |
1066 | clock-names = "fck", "sys_clk"; | |
7d0fde39 JS |
1067 | dmas = <&sdma 76>; |
1068 | dma-names = "audio_tx"; | |
e7585c4f TV |
1069 | }; |
1070 | }; | |
07b9b3d9 AT |
1071 | |
1072 | abb_mpu: regulator-abb-mpu { | |
1073 | compatible = "ti,abb-v2"; | |
1074 | regulator-name = "abb_mpu"; | |
1075 | #address-cells = <0>; | |
1076 | #size-cells = <0>; | |
1077 | clocks = <&sys_clkin>; | |
1078 | ti,settling-time = <50>; | |
1079 | ti,clock-cycles = <16>; | |
1080 | ||
1081 | reg = <0x4ae07cdc 0x8>, <0x4ae06014 0x4>, | |
1082 | <0x4a0021c4 0x8>, <0x4ae0c318 0x4>; | |
1083 | reg-names = "base-address", "int-address", | |
1084 | "efuse-address", "ldo-address"; | |
1085 | ti,tranxdone-status-mask = <0x80>; | |
1086 | /* LDOVBBMPU_MUX_CTRL */ | |
1087 | ti,ldovbb-override-mask = <0x400>; | |
1088 | /* LDOVBBMPU_VSET_OUT */ | |
1089 | ti,ldovbb-vset-mask = <0x1F>; | |
1090 | ||
1091 | /* | |
1092 | * NOTE: only FBB mode used but actual vset will | |
1093 | * determine final biasing | |
1094 | */ | |
1095 | ti,abb_info = < | |
1096 | /*uV ABB efuse rbb_m fbb_m vset_m*/ | |
1097 | 1060000 0 0x0 0 0x02000000 0x01F00000 | |
1098 | 1250000 0 0x4 0 0x02000000 0x01F00000 | |
1099 | >; | |
1100 | }; | |
1101 | ||
1102 | abb_mm: regulator-abb-mm { | |
1103 | compatible = "ti,abb-v2"; | |
1104 | regulator-name = "abb_mm"; | |
1105 | #address-cells = <0>; | |
1106 | #size-cells = <0>; | |
1107 | clocks = <&sys_clkin>; | |
1108 | ti,settling-time = <50>; | |
1109 | ti,clock-cycles = <16>; | |
1110 | ||
1111 | reg = <0x4ae07ce4 0x8>, <0x4ae06010 0x4>, | |
1112 | <0x4a0021a4 0x8>, <0x4ae0c314 0x4>; | |
1113 | reg-names = "base-address", "int-address", | |
1114 | "efuse-address", "ldo-address"; | |
1115 | ti,tranxdone-status-mask = <0x80000000>; | |
1116 | /* LDOVBBMM_MUX_CTRL */ | |
1117 | ti,ldovbb-override-mask = <0x400>; | |
1118 | /* LDOVBBMM_VSET_OUT */ | |
1119 | ti,ldovbb-vset-mask = <0x1F>; | |
1120 | ||
1121 | /* | |
1122 | * NOTE: only FBB mode used but actual vset will | |
1123 | * determine final biasing | |
1124 | */ | |
1125 | ti,abb_info = < | |
1126 | /*uV ABB efuse rbb_m fbb_m vset_m*/ | |
1127 | 1025000 0 0x0 0 0x02000000 0x01F00000 | |
1128 | 1120000 0 0x4 0 0x02000000 0x01F00000 | |
1129 | >; | |
1130 | }; | |
6b5de091 S |
1131 | }; |
1132 | }; | |
85dc74e9 | 1133 | |
38f5c8ba TK |
1134 | &cpu_thermal { |
1135 | polling-delay = <500>; /* milliseconds */ | |
1136 | }; | |
1137 | ||
85dc74e9 | 1138 | /include/ "omap54xx-clocks.dtsi" |