[deliverable/linux.git] / arch / arm / boot / dts / omap5.dtsi

/*
 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 * Based on "omap4.dtsi"
 */

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pinctrl/omap.h>

#include "skeleton.dtsi"

/ {
	#address-cells = <1>;
	#size-cells = <1>;

	compatible = "ti,omap5";
	interrupt-parent = <&gic>;

	aliases {
		serial0 = &uart1;
		serial1 = &uart2;
		serial2 = &uart3;
		serial3 = &uart4;
		serial4 = &uart5;
		serial5 = &uart6;
	};

	cpus {
		cpu@0 {
			compatible = "arm,cortex-a15";
		};
		cpu@1 {
			compatible = "arm,cortex-a15";
		};
	};

	timer {
		compatible = "arm,armv7-timer";
		/* PPI secure/nonsecure IRQ */
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 14 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 11 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 10 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>;
		clock-frequency = <6144000>;
	};

	gic: interrupt-controller@48211000 {
		compatible = "arm,cortex-a15-gic";
		interrupt-controller;
		#interrupt-cells = <3>;
		reg = <0x48211000 0x1000>,
		      <0x48212000 0x1000>,
		      <0x48214000 0x2000>,
		      <0x48216000 0x2000>;
	};

	/*
	 * The soc node represents the soc top level view. It is uses for IPs
	 * that are not memory mapped in the MPU view or for the MPU itself.
	 */
	soc {
		compatible = "ti,omap-infra";
		mpu {
			compatible = "ti,omap5-mpu";
			ti,hwmods = "mpu";
		};
	};

	/*
	 * XXX: Use a flat representation of the OMAP3 interconnect.
	 * The real OMAP interconnect network is quite complex.
	 * Since that will not bring real advantage to represent that in DT for
	 * the moment, just use a fake OCP bus entry to represent the whole bus
	 * hierarchy.
	 */
	ocp {
		compatible = "ti,omap4-l3-noc", "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;
		ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
		reg = <0x44000000 0x2000>,
		      <0x44800000 0x3000>,
		      <0x45000000 0x4000>;
		interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;

		counter32k: counter@4ae04000 {
			compatible = "ti,omap-counter32k";
			reg = <0x4ae04000 0x40>;
			ti,hwmods = "counter_32k";
		};

		omap5_pmx_core: pinmux@4a002840 {
			compatible = "ti,omap4-padconf", "pinctrl-single";
			reg = <0x4a002840 0x01b6>;
			#address-cells = <1>;
			#size-cells = <0>;
			pinctrl-single,register-width = <16>;
			pinctrl-single,function-mask = <0x7fff>;
		};
		omap5_pmx_wkup: pinmux@4ae0c840 {
			compatible = "ti,omap4-padconf", "pinctrl-single";
			reg = <0x4ae0c840 0x0038>;
			#address-cells = <1>;
			#size-cells = <0>;
			pinctrl-single,register-width = <16>;
			pinctrl-single,function-mask = <0x7fff>;
		};

		sdma: dma-controller@4a056000 {
			compatible = "ti,omap4430-sdma";
			reg = <0x4a056000 0x1000>;
			interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
			#dma-cells = <1>;
			#dma-channels = <32>;
			#dma-requests = <127>;
		};

		gpio1: gpio@4ae10000 {
			compatible = "ti,omap4-gpio";
			reg = <0x4ae10000 0x200>;
			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "gpio1";
			ti,gpio-always-on;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio2: gpio@48055000 {
			compatible = "ti,omap4-gpio";
			reg = <0x48055000 0x200>;
			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "gpio2";
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio3: gpio@48057000 {
			compatible = "ti,omap4-gpio";
			reg = <0x48057000 0x200>;
			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "gpio3";
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio4: gpio@48059000 {
			compatible = "ti,omap4-gpio";
			reg = <0x48059000 0x200>;
			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "gpio4";
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio5: gpio@4805b000 {
			compatible = "ti,omap4-gpio";
			reg = <0x4805b000 0x200>;
			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "gpio5";
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio6: gpio@4805d000 {
			compatible = "ti,omap4-gpio";
			reg = <0x4805d000 0x200>;
			interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "gpio6";
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio7: gpio@48051000 {
			compatible = "ti,omap4-gpio";
			reg = <0x48051000 0x200>;
			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "gpio7";
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio8: gpio@48053000 {
			compatible = "ti,omap4-gpio";
			reg = <0x48053000 0x200>;
			interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "gpio8";
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpmc: gpmc@50000000 {
			compatible = "ti,omap4430-gpmc";
			reg = <0x50000000 0x1000>;
			#address-cells = <2>;
			#size-cells = <1>;
			interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
			gpmc,num-cs = <8>;
			gpmc,num-waitpins = <4>;
			ti,hwmods = "gpmc";
		};

		i2c1: i2c@48070000 {
			compatible = "ti,omap4-i2c";
			reg = <0x48070000 0x100>;
			interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
			#address-cells = <1>;
			#size-cells = <0>;
			ti,hwmods = "i2c1";
		};

		i2c2: i2c@48072000 {
			compatible = "ti,omap4-i2c";
			reg = <0x48072000 0x100>;
			interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
			#address-cells = <1>;
			#size-cells = <0>;
			ti,hwmods = "i2c2";
		};

		i2c3: i2c@48060000 {
			compatible = "ti,omap4-i2c";
			reg = <0x48060000 0x100>;
			interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
			#address-cells = <1>;
			#size-cells = <0>;
			ti,hwmods = "i2c3";
		};

		i2c4: i2c@4807a000 {
			compatible = "ti,omap4-i2c";
			reg = <0x4807a000 0x100>;
			interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
			#address-cells = <1>;
			#size-cells = <0>;
			ti,hwmods = "i2c4";
		};

		i2c5: i2c@4807c000 {
			compatible = "ti,omap4-i2c";
			reg = <0x4807c000 0x100>;
			interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
			#address-cells = <1>;
			#size-cells = <0>;
			ti,hwmods = "i2c5";
		};

		mcspi1: spi@48098000 {
			compatible = "ti,omap4-mcspi";
			reg = <0x48098000 0x200>;
			interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
			#address-cells = <1>;
			#size-cells = <0>;
			ti,hwmods = "mcspi1";
			ti,spi-num-cs = <4>;
			dmas = <&sdma 35>,
			       <&sdma 36>,
			       <&sdma 37>,
			       <&sdma 38>,
			       <&sdma 39>,
			       <&sdma 40>,
			       <&sdma 41>,
			       <&sdma 42>;
			dma-names = "tx0", "rx0", "tx1", "rx1",
				    "tx2", "rx2", "tx3", "rx3";
		};

		mcspi2: spi@4809a000 {
			compatible = "ti,omap4-mcspi";
			reg = <0x4809a000 0x200>;
			interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
			#address-cells = <1>;
			#size-cells = <0>;
			ti,hwmods = "mcspi2";
			ti,spi-num-cs = <2>;
			dmas = <&sdma 43>,
			       <&sdma 44>,
			       <&sdma 45>,
			       <&sdma 46>;
			dma-names = "tx0", "rx0", "tx1", "rx1";
		};

		mcspi3: spi@480b8000 {
			compatible = "ti,omap4-mcspi";
			reg = <0x480b8000 0x200>;
			interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
			#address-cells = <1>;
			#size-cells = <0>;
			ti,hwmods = "mcspi3";
			ti,spi-num-cs = <2>;
			dmas = <&sdma 15>, <&sdma 16>;
			dma-names = "tx0", "rx0";
		};

		mcspi4: spi@480ba000 {
			compatible = "ti,omap4-mcspi";
			reg = <0x480ba000 0x200>;
			interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
			#address-cells = <1>;
			#size-cells = <0>;
			ti,hwmods = "mcspi4";
			ti,spi-num-cs = <1>;
			dmas = <&sdma 70>, <&sdma 71>;
			dma-names = "tx0", "rx0";
		};

		uart1: serial@4806a000 {
			compatible = "ti,omap4-uart";
			reg = <0x4806a000 0x100>;
			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "uart1";
			clock-frequency = <48000000>;
		};

		uart2: serial@4806c000 {
			compatible = "ti,omap4-uart";
			reg = <0x4806c000 0x100>;
			interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "uart2";
			clock-frequency = <48000000>;
		};

		uart3: serial@48020000 {
			compatible = "ti,omap4-uart";
			reg = <0x48020000 0x100>;
			interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "uart3";
			clock-frequency = <48000000>;
		};

		uart4: serial@4806e000 {
			compatible = "ti,omap4-uart";
			reg = <0x4806e000 0x100>;
			interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "uart4";
			clock-frequency = <48000000>;
		};

		uart5: serial@48066000 {
			compatible = "ti,omap4-uart";
			reg = <0x48066000 0x100>;
			interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "uart5";
			clock-frequency = <48000000>;
		};

		uart6: serial@48068000 {
			compatible = "ti,omap4-uart";
			reg = <0x48068000 0x100>;
			interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "uart6";
			clock-frequency = <48000000>;
		};

		mmc1: mmc@4809c000 {
			compatible = "ti,omap4-hsmmc";
			reg = <0x4809c000 0x400>;
			interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "mmc1";
			ti,dual-volt;
			ti,needs-special-reset;
			dmas = <&sdma 61>, <&sdma 62>;
			dma-names = "tx", "rx";
		};

		mmc2: mmc@480b4000 {
			compatible = "ti,omap4-hsmmc";
			reg = <0x480b4000 0x400>;
			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "mmc2";
			ti,needs-special-reset;
			dmas = <&sdma 47>, <&sdma 48>;
			dma-names = "tx", "rx";
		};

		mmc3: mmc@480ad000 {
			compatible = "ti,omap4-hsmmc";
			reg = <0x480ad000 0x400>;
			interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "mmc3";
			ti,needs-special-reset;
			dmas = <&sdma 77>, <&sdma 78>;
			dma-names = "tx", "rx";
		};

		mmc4: mmc@480d1000 {
			compatible = "ti,omap4-hsmmc";
			reg = <0x480d1000 0x400>;
			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "mmc4";
			ti,needs-special-reset;
			dmas = <&sdma 57>, <&sdma 58>;
			dma-names = "tx", "rx";
		};

		mmc5: mmc@480d5000 {
			compatible = "ti,omap4-hsmmc";
			reg = <0x480d5000 0x400>;
			interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "mmc5";
			ti,needs-special-reset;
			dmas = <&sdma 59>, <&sdma 60>;
			dma-names = "tx", "rx";
		};

		keypad: keypad@4ae1c000 {
			compatible = "ti,omap4-keypad";
			reg = <0x4ae1c000 0x400>;
			ti,hwmods = "kbd";
		};

		mcpdm: mcpdm@40132000 {
			compatible = "ti,omap4-mcpdm";
			reg = <0x40132000 0x7f>, /* MPU private access */
			      <0x49032000 0x7f>; /* L3 Interconnect */
			reg-names = "mpu", "dma";
			interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "mcpdm";
			dmas = <&sdma 65>,
			       <&sdma 66>;
			dma-names = "up_link", "dn_link";
		};

		dmic: dmic@4012e000 {
			compatible = "ti,omap4-dmic";
			reg = <0x4012e000 0x7f>, /* MPU private access */
			      <0x4902e000 0x7f>; /* L3 Interconnect */
			reg-names = "mpu", "dma";
			interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "dmic";
			dmas = <&sdma 67>;
			dma-names = "up_link";
		};

		mcbsp1: mcbsp@40122000 {
			compatible = "ti,omap4-mcbsp";
			reg = <0x40122000 0xff>, /* MPU private access */
			      <0x49022000 0xff>; /* L3 Interconnect */
			reg-names = "mpu", "dma";
			interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "common";
			ti,buffer-size = <128>;
			ti,hwmods = "mcbsp1";
			dmas = <&sdma 33>,
			       <&sdma 34>;
			dma-names = "tx", "rx";
		};

		mcbsp2: mcbsp@40124000 {
			compatible = "ti,omap4-mcbsp";
			reg = <0x40124000 0xff>, /* MPU private access */
			      <0x49024000 0xff>; /* L3 Interconnect */
			reg-names = "mpu", "dma";
			interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "common";
			ti,buffer-size = <128>;
			ti,hwmods = "mcbsp2";
			dmas = <&sdma 17>,
			       <&sdma 18>;
			dma-names = "tx", "rx";
		};

		mcbsp3: mcbsp@40126000 {
			compatible = "ti,omap4-mcbsp";
			reg = <0x40126000 0xff>, /* MPU private access */
			      <0x49026000 0xff>; /* L3 Interconnect */
			reg-names = "mpu", "dma";
			interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "common";
			ti,buffer-size = <128>;
			ti,hwmods = "mcbsp3";
			dmas = <&sdma 19>,
			       <&sdma 20>;
			dma-names = "tx", "rx";
		};

		timer1: timer@4ae18000 {
			compatible = "ti,omap5430-timer";
			reg = <0x4ae18000 0x80>;
			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "timer1";
			ti,timer-alwon;
		};

		timer2: timer@48032000 {
			compatible = "ti,omap5430-timer";
			reg = <0x48032000 0x80>;
			interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "timer2";
		};

		timer3: timer@48034000 {
			compatible = "ti,omap5430-timer";
			reg = <0x48034000 0x80>;
			interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "timer3";
		};

		timer4: timer@48036000 {
			compatible = "ti,omap5430-timer";
			reg = <0x48036000 0x80>;
			interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "timer4";
		};

		timer5: timer@40138000 {
			compatible = "ti,omap5430-timer";
			reg = <0x40138000 0x80>,
			      <0x49038000 0x80>;
			interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "timer5";
			ti,timer-dsp;
			ti,timer-pwm;
		};

		timer6: timer@4013a000 {
			compatible = "ti,omap5430-timer";
			reg = <0x4013a000 0x80>,
			      <0x4903a000 0x80>;
			interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "timer6";
			ti,timer-dsp;
			ti,timer-pwm;
		};

		timer7: timer@4013c000 {
			compatible = "ti,omap5430-timer";
			reg = <0x4013c000 0x80>,
			      <0x4903c000 0x80>;
			interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "timer7";
			ti,timer-dsp;
		};

		timer8: timer@4013e000 {
			compatible = "ti,omap5430-timer";
			reg = <0x4013e000 0x80>,
			      <0x4903e000 0x80>;
			interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "timer8";
			ti,timer-dsp;
			ti,timer-pwm;
		};

		timer9: timer@4803e000 {
			compatible = "ti,omap5430-timer";
			reg = <0x4803e000 0x80>;
			interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "timer9";
			ti,timer-pwm;
		};

		timer10: timer@48086000 {
			compatible = "ti,omap5430-timer";
			reg = <0x48086000 0x80>;
			interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "timer10";
			ti,timer-pwm;
		};

		timer11: timer@48088000 {
			compatible = "ti,omap5430-timer";
			reg = <0x48088000 0x80>;
			interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "timer11";
			ti,timer-pwm;
		};

		wdt2: wdt@4ae14000 {
			compatible = "ti,omap5-wdt", "ti,omap3-wdt";
			reg = <0x4ae14000 0x80>;
			interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "wd_timer2";
		};

		emif1: emif@0x4c000000 {
			compatible	= "ti,emif-4d5";
			ti,hwmods	= "emif1";
			phy-type	= <2>; /* DDR PHY type: Intelli PHY */
			reg = <0x4c000000 0x400>;
			interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
			hw-caps-read-idle-ctrl;
			hw-caps-ll-interface;
			hw-caps-temp-alert;
		};

		emif2: emif@0x4d000000 {
			compatible	= "ti,emif-4d5";
			ti,hwmods	= "emif2";
			phy-type	= <2>; /* DDR PHY type: Intelli PHY */
			reg = <0x4d000000 0x400>;
			interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
			hw-caps-read-idle-ctrl;
			hw-caps-ll-interface;
			hw-caps-temp-alert;
		};

		omap_control_usb: omap-control-usb@4a002300 {
			compatible = "ti,omap-control-usb";
			reg = <0x4a002300 0x4>,
			      <0x4a002370 0x4>;
			reg-names = "control_dev_conf", "phy_power_usb";
			ti,type = <2>;
		};

		omap_dwc3@4a020000 {
			compatible = "ti,dwc3";
			ti,hwmods = "usb_otg_ss";
			reg = <0x4a020000 0x1000>;
			interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
			#address-cells = <1>;
			#size-cells = <1>;
			utmi-mode = <2>;
			ranges;
			dwc3@4a030000 {
				compatible = "synopsys,dwc3";
				reg = <0x4a030000 0x1000>;
				interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
				usb-phy = <&usb2_phy>, <&usb3_phy>;
				tx-fifo-resize;
			};
		};

		ocp2scp {
			compatible = "ti,omap-ocp2scp";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;
			ti,hwmods = "ocp2scp1";
			usb2_phy: usb2phy@4a084000 {
				compatible = "ti,omap-usb2";
				reg = <0x4a084000 0x7c>;
				ctrl-module = <&omap_control_usb>;
			};

			usb3_phy: usb3phy@4a084400 {
				compatible = "ti,omap-usb3";
				reg = <0x4a084400 0x80>,
				      <0x4a084800 0x64>,
				      <0x4a084c00 0x40>;
				reg-names = "phy_rx", "phy_tx", "pll_ctrl";
				ctrl-module = <&omap_control_usb>;
			};
		};
	};
};
Commit	Line	Data
6b5de091 S	1	/*
	2	* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License version 2 as
	6	* published by the Free Software Foundation.
	7	* Based on "omap4.dtsi"
	8	*/
	9
6d624eab	10	#include <dt-bindings/gpio/gpio.h>
8fea7d5a	11	#include <dt-bindings/interrupt-controller/arm-gic.h>
bcd3cca7	12	#include <dt-bindings/pinctrl/omap.h>
6d624eab	13
98ef7957	14	#include "skeleton.dtsi"
6b5de091 S	15
6b5de091 S	16	/ {
ba1829bc SS	17	#address-cells = <1>;
	18	#size-cells = <1>;
	19
6b5de091 S	20	compatible = "ti,omap5";
	21	interrupt-parent = <&gic>;
	22
	23	aliases {
	24	serial0 = &uart1;
	25	serial1 = &uart2;
	26	serial2 = &uart3;
	27	serial3 = &uart4;
	28	serial4 = &uart5;
	29	serial5 = &uart6;
	30	};
	31
	32	cpus {
	33	cpu@0 {
	34	compatible = "arm,cortex-a15";
	35	};
	36	cpu@1 {
	37	compatible = "arm,cortex-a15";
	38	};
	39	};
	40
b45ccc4e SS	41	timer {
b45ccc4e SS	42	compatible = "arm,armv7-timer";
8fea7d5a FV	43	/* PPI secure/nonsecure IRQ */
	44	interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) \| IRQ_TYPE_LEVEL_LOW)>,
	45	<GIC_PPI 14 (GIC_CPU_MASK_RAW(3) \| IRQ_TYPE_LEVEL_LOW)>,
	46	<GIC_PPI 11 (GIC_CPU_MASK_RAW(3) \| IRQ_TYPE_LEVEL_LOW)>,
	47	<GIC_PPI 10 (GIC_CPU_MASK_RAW(3) \| IRQ_TYPE_LEVEL_LOW)>;
b45ccc4e SS	48	clock-frequency = <6144000>;
	49	};
	50
ba1829bc SS	51	gic: interrupt-controller@48211000 {
	52	compatible = "arm,cortex-a15-gic";
	53	interrupt-controller;
	54	#interrupt-cells = <3>;
	55	reg = <0x48211000 0x1000>,
0129c16c SS	56	<0x48212000 0x1000>,
	57	<0x48214000 0x2000>,
	58	<0x48216000 0x2000>;
ba1829bc SS	59	};
ba1829bc SS	60
6b5de091 S	61	/*
	62	* The soc node represents the soc top level view. It is uses for IPs
	63	* that are not memory mapped in the MPU view or for the MPU itself.
	64	*/
	65	soc {
	66	compatible = "ti,omap-infra";
	67	mpu {
	68	compatible = "ti,omap5-mpu";
	69	ti,hwmods = "mpu";
	70	};
	71	};
	72
	73	/*
	74	* XXX: Use a flat representation of the OMAP3 interconnect.
	75	* The real OMAP interconnect network is quite complex.
	76	* Since that will not bring real advantage to represent that in DT for
	77	* the moment, just use a fake OCP bus entry to represent the whole bus
	78	* hierarchy.
	79	*/
	80	ocp {
	81	compatible = "ti,omap4-l3-noc", "simple-bus";
	82	#address-cells = <1>;
	83	#size-cells = <1>;
	84	ranges;
	85	ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
20a60eaa SS	86	reg = <0x44000000 0x2000>,
	87	<0x44800000 0x3000>,
	88	<0x45000000 0x4000>;
8fea7d5a FV	89	interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
8fea7d5a FV	90	<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
6b5de091	91
3b3132f7 JH	92	counter32k: counter@4ae04000 {
	93	compatible = "ti,omap-counter32k";
	94	reg = <0x4ae04000 0x40>;
	95	ti,hwmods = "counter_32k";
	96	};
	97
5da6a2d5 PU	98	omap5_pmx_core: pinmux@4a002840 {
	99	compatible = "ti,omap4-padconf", "pinctrl-single";
	100	reg = <0x4a002840 0x01b6>;
	101	#address-cells = <1>;
	102	#size-cells = <0>;
	103	pinctrl-single,register-width = <16>;
	104	pinctrl-single,function-mask = <0x7fff>;
	105	};
	106	omap5_pmx_wkup: pinmux@4ae0c840 {
	107	compatible = "ti,omap4-padconf", "pinctrl-single";
	108	reg = <0x4ae0c840 0x0038>;
	109	#address-cells = <1>;
	110	#size-cells = <0>;
	111	pinctrl-single,register-width = <16>;
	112	pinctrl-single,function-mask = <0x7fff>;
	113	};
	114
2c2dc545 JH	115	sdma: dma-controller@4a056000 {
	116	compatible = "ti,omap4430-sdma";
	117	reg = <0x4a056000 0x1000>;
8fea7d5a FV	118	interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
	119	<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
	120	<GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
	121	<GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
2c2dc545 JH	122	#dma-cells = <1>;
	123	#dma-channels = <32>;
	124	#dma-requests = <127>;
	125	};
	126
6b5de091 S	127	gpio1: gpio@4ae10000 {
6b5de091 S	128	compatible = "ti,omap4-gpio";
f4b224f2	129	reg = <0x4ae10000 0x200>;
8fea7d5a	130	interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
6b5de091	131	ti,hwmods = "gpio1";
e4b9b9f3	132	ti,gpio-always-on;
6b5de091 S	133	gpio-controller;
	134	#gpio-cells = <2>;
	135	interrupt-controller;
ff5c9059	136	#interrupt-cells = <2>;
6b5de091 S	137	};
	138
	139	gpio2: gpio@48055000 {
	140	compatible = "ti,omap4-gpio";
f4b224f2	141	reg = <0x48055000 0x200>;
8fea7d5a	142	interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
6b5de091 S	143	ti,hwmods = "gpio2";
	144	gpio-controller;
	145	#gpio-cells = <2>;
	146	interrupt-controller;
ff5c9059	147	#interrupt-cells = <2>;
6b5de091 S	148	};
	149
	150	gpio3: gpio@48057000 {
	151	compatible = "ti,omap4-gpio";
f4b224f2	152	reg = <0x48057000 0x200>;
8fea7d5a	153	interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
6b5de091 S	154	ti,hwmods = "gpio3";
	155	gpio-controller;
	156	#gpio-cells = <2>;
	157	interrupt-controller;
ff5c9059	158	#interrupt-cells = <2>;
6b5de091 S	159	};
	160
	161	gpio4: gpio@48059000 {
	162	compatible = "ti,omap4-gpio";
f4b224f2	163	reg = <0x48059000 0x200>;
8fea7d5a	164	interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
6b5de091 S	165	ti,hwmods = "gpio4";
	166	gpio-controller;
	167	#gpio-cells = <2>;
	168	interrupt-controller;
ff5c9059	169	#interrupt-cells = <2>;
6b5de091 S	170	};
	171
	172	gpio5: gpio@4805b000 {
	173	compatible = "ti,omap4-gpio";
f4b224f2	174	reg = <0x4805b000 0x200>;
8fea7d5a	175	interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
6b5de091 S	176	ti,hwmods = "gpio5";
	177	gpio-controller;
	178	#gpio-cells = <2>;
	179	interrupt-controller;
ff5c9059	180	#interrupt-cells = <2>;
6b5de091 S	181	};
	182
	183	gpio6: gpio@4805d000 {
	184	compatible = "ti,omap4-gpio";
f4b224f2	185	reg = <0x4805d000 0x200>;
8fea7d5a	186	interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
6b5de091 S	187	ti,hwmods = "gpio6";
	188	gpio-controller;
	189	#gpio-cells = <2>;
	190	interrupt-controller;
ff5c9059	191	#interrupt-cells = <2>;
6b5de091 S	192	};
	193
	194	gpio7: gpio@48051000 {
	195	compatible = "ti,omap4-gpio";
f4b224f2	196	reg = <0x48051000 0x200>;
8fea7d5a	197	interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
6b5de091 S	198	ti,hwmods = "gpio7";
	199	gpio-controller;
	200	#gpio-cells = <2>;
	201	interrupt-controller;
ff5c9059	202	#interrupt-cells = <2>;
6b5de091 S	203	};
	204
	205	gpio8: gpio@48053000 {
	206	compatible = "ti,omap4-gpio";
f4b224f2	207	reg = <0x48053000 0x200>;
8fea7d5a	208	interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
6b5de091 S	209	ti,hwmods = "gpio8";
	210	gpio-controller;
	211	#gpio-cells = <2>;
	212	interrupt-controller;
ff5c9059	213	#interrupt-cells = <2>;
6b5de091 S	214	};
6b5de091 S	215
1c7dbb55 JH	216	gpmc: gpmc@50000000 {
	217	compatible = "ti,omap4430-gpmc";
	218	reg = <0x50000000 0x1000>;
	219	#address-cells = <2>;
	220	#size-cells = <1>;
8fea7d5a	221	interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
1c7dbb55 JH	222	gpmc,num-cs = <8>;
	223	gpmc,num-waitpins = <4>;
	224	ti,hwmods = "gpmc";
	225	};
	226
6e6a9a50 SP	227	i2c1: i2c@48070000 {
6e6a9a50 SP	228	compatible = "ti,omap4-i2c";
d7118bbd	229	reg = <0x48070000 0x100>;
8fea7d5a	230	interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
6e6a9a50 SP	231	#address-cells = <1>;
	232	#size-cells = <0>;
	233	ti,hwmods = "i2c1";
	234	};
	235
	236	i2c2: i2c@48072000 {
	237	compatible = "ti,omap4-i2c";
d7118bbd	238	reg = <0x48072000 0x100>;
8fea7d5a	239	interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
6e6a9a50 SP	240	#address-cells = <1>;
	241	#size-cells = <0>;
	242	ti,hwmods = "i2c2";
	243	};
	244
	245	i2c3: i2c@48060000 {
	246	compatible = "ti,omap4-i2c";
d7118bbd	247	reg = <0x48060000 0x100>;
8fea7d5a	248	interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
6e6a9a50 SP	249	#address-cells = <1>;
	250	#size-cells = <0>;
	251	ti,hwmods = "i2c3";
	252	};
	253
d7118bbd	254	i2c4: i2c@4807a000 {
6e6a9a50	255	compatible = "ti,omap4-i2c";
d7118bbd	256	reg = <0x4807a000 0x100>;
8fea7d5a	257	interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
6e6a9a50 SP	258	#address-cells = <1>;
	259	#size-cells = <0>;
	260	ti,hwmods = "i2c4";
	261	};
	262
d7118bbd	263	i2c5: i2c@4807c000 {
6e6a9a50	264	compatible = "ti,omap4-i2c";
d7118bbd	265	reg = <0x4807c000 0x100>;
8fea7d5a	266	interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
6e6a9a50 SP	267	#address-cells = <1>;
	268	#size-cells = <0>;
	269	ti,hwmods = "i2c5";
	270	};
	271
43286b11 FB	272	mcspi1: spi@48098000 {
	273	compatible = "ti,omap4-mcspi";
	274	reg = <0x48098000 0x200>;
8fea7d5a	275	interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
43286b11 FB	276	#address-cells = <1>;
	277	#size-cells = <0>;
	278	ti,hwmods = "mcspi1";
	279	ti,spi-num-cs = <4>;
2c2dc545 JH	280	dmas = <&sdma 35>,
	281	<&sdma 36>,
	282	<&sdma 37>,
	283	<&sdma 38>,
	284	<&sdma 39>,
	285	<&sdma 40>,
	286	<&sdma 41>,
	287	<&sdma 42>;
	288	dma-names = "tx0", "rx0", "tx1", "rx1",
	289	"tx2", "rx2", "tx3", "rx3";
43286b11 FB	290	};
	291
	292	mcspi2: spi@4809a000 {
	293	compatible = "ti,omap4-mcspi";
	294	reg = <0x4809a000 0x200>;
8fea7d5a	295	interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
43286b11 FB	296	#address-cells = <1>;
	297	#size-cells = <0>;
	298	ti,hwmods = "mcspi2";
	299	ti,spi-num-cs = <2>;
2c2dc545 JH	300	dmas = <&sdma 43>,
	301	<&sdma 44>,
	302	<&sdma 45>,
	303	<&sdma 46>;
	304	dma-names = "tx0", "rx0", "tx1", "rx1";
43286b11 FB	305	};
	306
	307	mcspi3: spi@480b8000 {
	308	compatible = "ti,omap4-mcspi";
	309	reg = <0x480b8000 0x200>;
8fea7d5a	310	interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
43286b11 FB	311	#address-cells = <1>;
	312	#size-cells = <0>;
	313	ti,hwmods = "mcspi3";
	314	ti,spi-num-cs = <2>;
2c2dc545 JH	315	dmas = <&sdma 15>, <&sdma 16>;
2c2dc545 JH	316	dma-names = "tx0", "rx0";
43286b11 FB	317	};
	318
	319	mcspi4: spi@480ba000 {
	320	compatible = "ti,omap4-mcspi";
	321	reg = <0x480ba000 0x200>;
8fea7d5a	322	interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
43286b11 FB	323	#address-cells = <1>;
	324	#size-cells = <0>;
	325	ti,hwmods = "mcspi4";
	326	ti,spi-num-cs = <1>;
2c2dc545 JH	327	dmas = <&sdma 70>, <&sdma 71>;
2c2dc545 JH	328	dma-names = "tx0", "rx0";
43286b11 FB	329	};
43286b11 FB	330
6b5de091 S	331	uart1: serial@4806a000 {
6b5de091 S	332	compatible = "ti,omap4-uart";
8e80f660	333	reg = <0x4806a000 0x100>;
8fea7d5a	334	interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
6b5de091 S	335	ti,hwmods = "uart1";
	336	clock-frequency = <48000000>;
	337	};
	338
	339	uart2: serial@4806c000 {
	340	compatible = "ti,omap4-uart";
8e80f660	341	reg = <0x4806c000 0x100>;
8fea7d5a	342	interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
6b5de091 S	343	ti,hwmods = "uart2";
	344	clock-frequency = <48000000>;
	345	};
	346
	347	uart3: serial@48020000 {
	348	compatible = "ti,omap4-uart";
8e80f660	349	reg = <0x48020000 0x100>;
8fea7d5a	350	interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
6b5de091 S	351	ti,hwmods = "uart3";
	352	clock-frequency = <48000000>;
	353	};
	354
	355	uart4: serial@4806e000 {
	356	compatible = "ti,omap4-uart";
8e80f660	357	reg = <0x4806e000 0x100>;
8fea7d5a	358	interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
6b5de091 S	359	ti,hwmods = "uart4";
	360	clock-frequency = <48000000>;
	361	};
	362
	363	uart5: serial@48066000 {
8e80f660 SG	364	compatible = "ti,omap4-uart";
8e80f660 SG	365	reg = <0x48066000 0x100>;
8fea7d5a	366	interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
6b5de091 S	367	ti,hwmods = "uart5";
	368	clock-frequency = <48000000>;
	369	};
	370
	371	uart6: serial@48068000 {
8e80f660 SG	372	compatible = "ti,omap4-uart";
8e80f660 SG	373	reg = <0x48068000 0x100>;
8fea7d5a	374	interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
6b5de091 S	375	ti,hwmods = "uart6";
	376	clock-frequency = <48000000>;
	377	};
5dd18b01 B	378
	379	mmc1: mmc@4809c000 {
	380	compatible = "ti,omap4-hsmmc";
9a642362	381	reg = <0x4809c000 0x400>;
8fea7d5a	382	interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
5dd18b01 B	383	ti,hwmods = "mmc1";
	384	ti,dual-volt;
	385	ti,needs-special-reset;
2c2dc545 JH	386	dmas = <&sdma 61>, <&sdma 62>;
2c2dc545 JH	387	dma-names = "tx", "rx";
5dd18b01 B	388	};
	389
	390	mmc2: mmc@480b4000 {
	391	compatible = "ti,omap4-hsmmc";
9a642362	392	reg = <0x480b4000 0x400>;
8fea7d5a	393	interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
5dd18b01 B	394	ti,hwmods = "mmc2";
5dd18b01 B	395	ti,needs-special-reset;
2c2dc545 JH	396	dmas = <&sdma 47>, <&sdma 48>;
2c2dc545 JH	397	dma-names = "tx", "rx";
5dd18b01 B	398	};
	399
	400	mmc3: mmc@480ad000 {
	401	compatible = "ti,omap4-hsmmc";
9a642362	402	reg = <0x480ad000 0x400>;
8fea7d5a	403	interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
5dd18b01 B	404	ti,hwmods = "mmc3";
5dd18b01 B	405	ti,needs-special-reset;
2c2dc545 JH	406	dmas = <&sdma 77>, <&sdma 78>;
2c2dc545 JH	407	dma-names = "tx", "rx";
5dd18b01 B	408	};
	409
	410	mmc4: mmc@480d1000 {
	411	compatible = "ti,omap4-hsmmc";
9a642362	412	reg = <0x480d1000 0x400>;
8fea7d5a	413	interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
5dd18b01 B	414	ti,hwmods = "mmc4";
5dd18b01 B	415	ti,needs-special-reset;
2c2dc545 JH	416	dmas = <&sdma 57>, <&sdma 58>;
2c2dc545 JH	417	dma-names = "tx", "rx";
5dd18b01 B	418	};
	419
	420	mmc5: mmc@480d5000 {
	421	compatible = "ti,omap4-hsmmc";
9a642362	422	reg = <0x480d5000 0x400>;
8fea7d5a	423	interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
5dd18b01 B	424	ti,hwmods = "mmc5";
5dd18b01 B	425	ti,needs-special-reset;
2c2dc545 JH	426	dmas = <&sdma 59>, <&sdma 60>;
2c2dc545 JH	427	dma-names = "tx", "rx";
5dd18b01	428	};
5449fbc2 SP	429
	430	keypad: keypad@4ae1c000 {
	431	compatible = "ti,omap4-keypad";
8cc8b89f	432	reg = <0x4ae1c000 0x400>;
5449fbc2 SP	433	ti,hwmods = "kbd";
5449fbc2 SP	434	};
ffd5db24	435
cbb57f07 PU	436	mcpdm: mcpdm@40132000 {
	437	compatible = "ti,omap4-mcpdm";
	438	reg = <0x40132000 0x7f>, /* MPU private access */
	439	<0x49032000 0x7f>; /* L3 Interconnect */
	440	reg-names = "mpu", "dma";
8fea7d5a	441	interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
cbb57f07	442	ti,hwmods = "mcpdm";
4e4ead73 SG	443	dmas = <&sdma 65>,
	444	<&sdma 66>;
	445	dma-names = "up_link", "dn_link";
cbb57f07 PU	446	};
	447
	448	dmic: dmic@4012e000 {
	449	compatible = "ti,omap4-dmic";
	450	reg = <0x4012e000 0x7f>, /* MPU private access */
	451	<0x4902e000 0x7f>; /* L3 Interconnect */
	452	reg-names = "mpu", "dma";
8fea7d5a	453	interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
cbb57f07	454	ti,hwmods = "dmic";
4e4ead73 SG	455	dmas = <&sdma 67>;
4e4ead73 SG	456	dma-names = "up_link";
cbb57f07 PU	457	};
cbb57f07 PU	458
ffd5db24 PU	459	mcbsp1: mcbsp@40122000 {
	460	compatible = "ti,omap4-mcbsp";
	461	reg = <0x40122000 0xff>, /* MPU private access */
	462	<0x49022000 0xff>; /* L3 Interconnect */
	463	reg-names = "mpu", "dma";
8fea7d5a	464	interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
ffd5db24	465	interrupt-names = "common";
ffd5db24 PU	466	ti,buffer-size = <128>;
ffd5db24 PU	467	ti,hwmods = "mcbsp1";
4e4ead73 SG	468	dmas = <&sdma 33>,
	469	<&sdma 34>;
	470	dma-names = "tx", "rx";
ffd5db24 PU	471	};
	472
	473	mcbsp2: mcbsp@40124000 {
	474	compatible = "ti,omap4-mcbsp";
	475	reg = <0x40124000 0xff>, /* MPU private access */
	476	<0x49024000 0xff>; /* L3 Interconnect */
	477	reg-names = "mpu", "dma";
8fea7d5a	478	interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
ffd5db24	479	interrupt-names = "common";
ffd5db24 PU	480	ti,buffer-size = <128>;
ffd5db24 PU	481	ti,hwmods = "mcbsp2";
4e4ead73 SG	482	dmas = <&sdma 17>,
	483	<&sdma 18>;
	484	dma-names = "tx", "rx";
ffd5db24 PU	485	};
	486
	487	mcbsp3: mcbsp@40126000 {
	488	compatible = "ti,omap4-mcbsp";
	489	reg = <0x40126000 0xff>, /* MPU private access */
	490	<0x49026000 0xff>; /* L3 Interconnect */
	491	reg-names = "mpu", "dma";
8fea7d5a	492	interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
ffd5db24	493	interrupt-names = "common";
ffd5db24 PU	494	ti,buffer-size = <128>;
ffd5db24 PU	495	ti,hwmods = "mcbsp3";
4e4ead73 SG	496	dmas = <&sdma 19>,
	497	<&sdma 20>;
	498	dma-names = "tx", "rx";
ffd5db24	499	};
df692a92 JH	500
df692a92 JH	501	timer1: timer@4ae18000 {
002e1ec5	502	compatible = "ti,omap5430-timer";
df692a92	503	reg = <0x4ae18000 0x80>;
8fea7d5a	504	interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
df692a92 JH	505	ti,hwmods = "timer1";
	506	ti,timer-alwon;
	507	};
	508
	509	timer2: timer@48032000 {
002e1ec5	510	compatible = "ti,omap5430-timer";
df692a92	511	reg = <0x48032000 0x80>;
8fea7d5a	512	interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
df692a92 JH	513	ti,hwmods = "timer2";
	514	};
	515
	516	timer3: timer@48034000 {
002e1ec5	517	compatible = "ti,omap5430-timer";
df692a92	518	reg = <0x48034000 0x80>;
8fea7d5a	519	interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
df692a92 JH	520	ti,hwmods = "timer3";
	521	};
	522
	523	timer4: timer@48036000 {
002e1ec5	524	compatible = "ti,omap5430-timer";
df692a92	525	reg = <0x48036000 0x80>;
8fea7d5a	526	interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
df692a92 JH	527	ti,hwmods = "timer4";
	528	};
	529
	530	timer5: timer@40138000 {
002e1ec5	531	compatible = "ti,omap5430-timer";
df692a92 JH	532	reg = <0x40138000 0x80>,
df692a92 JH	533	<0x49038000 0x80>;
8fea7d5a	534	interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
df692a92 JH	535	ti,hwmods = "timer5";
df692a92 JH	536	ti,timer-dsp;
8341613a	537	ti,timer-pwm;
df692a92 JH	538	};
	539
	540	timer6: timer@4013a000 {
002e1ec5	541	compatible = "ti,omap5430-timer";
df692a92 JH	542	reg = <0x4013a000 0x80>,
df692a92 JH	543	<0x4903a000 0x80>;
8fea7d5a	544	interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
df692a92 JH	545	ti,hwmods = "timer6";
	546	ti,timer-dsp;
	547	ti,timer-pwm;
	548	};
	549
	550	timer7: timer@4013c000 {
002e1ec5	551	compatible = "ti,omap5430-timer";
df692a92 JH	552	reg = <0x4013c000 0x80>,
df692a92 JH	553	<0x4903c000 0x80>;
8fea7d5a	554	interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
df692a92 JH	555	ti,hwmods = "timer7";
	556	ti,timer-dsp;
	557	};
	558
	559	timer8: timer@4013e000 {
002e1ec5	560	compatible = "ti,omap5430-timer";
df692a92 JH	561	reg = <0x4013e000 0x80>,
df692a92 JH	562	<0x4903e000 0x80>;
8fea7d5a	563	interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
df692a92 JH	564	ti,hwmods = "timer8";
	565	ti,timer-dsp;
	566	ti,timer-pwm;
	567	};
	568
	569	timer9: timer@4803e000 {
002e1ec5	570	compatible = "ti,omap5430-timer";
df692a92	571	reg = <0x4803e000 0x80>;
8fea7d5a	572	interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
df692a92	573	ti,hwmods = "timer9";
8341613a	574	ti,timer-pwm;
df692a92 JH	575	};
	576
	577	timer10: timer@48086000 {
002e1ec5	578	compatible = "ti,omap5430-timer";
df692a92	579	reg = <0x48086000 0x80>;
8fea7d5a	580	interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
df692a92	581	ti,hwmods = "timer10";
8341613a	582	ti,timer-pwm;
df692a92 JH	583	};
	584
	585	timer11: timer@48088000 {
002e1ec5	586	compatible = "ti,omap5430-timer";
df692a92	587	reg = <0x48088000 0x80>;
8fea7d5a	588	interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
df692a92 JH	589	ti,hwmods = "timer11";
	590	ti,timer-pwm;
	591	};
e6900ddf	592
55452197 LV	593	wdt2: wdt@4ae14000 {
	594	compatible = "ti,omap5-wdt", "ti,omap3-wdt";
	595	reg = <0x4ae14000 0x80>;
8fea7d5a	596	interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
55452197 LV	597	ti,hwmods = "wd_timer2";
	598	};
	599
e6900ddf LV	600	emif1: emif@0x4c000000 {
	601	compatible = "ti,emif-4d5";
	602	ti,hwmods = "emif1";
	603	phy-type = <2>; /* DDR PHY type: Intelli PHY */
	604	reg = <0x4c000000 0x400>;
8fea7d5a	605	interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
e6900ddf LV	606	hw-caps-read-idle-ctrl;
	607	hw-caps-ll-interface;
	608	hw-caps-temp-alert;
	609	};
	610
	611	emif2: emif@0x4d000000 {
	612	compatible = "ti,emif-4d5";
	613	ti,hwmods = "emif2";
	614	phy-type = <2>; /* DDR PHY type: Intelli PHY */
	615	reg = <0x4d000000 0x400>;
8fea7d5a	616	interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
e6900ddf LV	617	hw-caps-read-idle-ctrl;
	618	hw-caps-ll-interface;
	619	hw-caps-temp-alert;
	620	};
fedc428e KVA	621
	622	omap_control_usb: omap-control-usb@4a002300 {
	623	compatible = "ti,omap-control-usb";
	624	reg = <0x4a002300 0x4>,
	625	<0x4a002370 0x4>;
	626	reg-names = "control_dev_conf", "phy_power_usb";
	627	ti,type = <2>;
	628	};
e9831967	629
72f6f957 KVA	630	omap_dwc3@4a020000 {
	631	compatible = "ti,dwc3";
	632	ti,hwmods = "usb_otg_ss";
	633	reg = <0x4a020000 0x1000>;
8fea7d5a	634	interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
72f6f957 KVA	635	#address-cells = <1>;
	636	#size-cells = <1>;
	637	utmi-mode = <2>;
	638	ranges;
	639	dwc3@4a030000 {
	640	compatible = "synopsys,dwc3";
	641	reg = <0x4a030000 0x1000>;
8fea7d5a	642	interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
72f6f957 KVA	643	usb-phy = <&usb2_phy>, <&usb3_phy>;
	644	tx-fifo-resize;
	645	};
	646	};
	647
e9831967 KVA	648	ocp2scp {
	649	compatible = "ti,omap-ocp2scp";
	650	#address-cells = <1>;
	651	#size-cells = <1>;
	652	ranges;
	653	ti,hwmods = "ocp2scp1";
ae6a32d2 KVA	654	usb2_phy: usb2phy@4a084000 {
	655	compatible = "ti,omap-usb2";
	656	reg = <0x4a084000 0x7c>;
	657	ctrl-module = <&omap_control_usb>;
	658	};
	659
	660	usb3_phy: usb3phy@4a084400 {
	661	compatible = "ti,omap-usb3";
	662	reg = <0x4a084400 0x80>,
	663	<0x4a084800 0x64>,
	664	<0x4a084c00 0x40>;
	665	reg-names = "phy_rx", "phy_tx", "pll_ctrl";
	666	ctrl-module = <&omap_control_usb>;
	667	};
e9831967	668	};
6b5de091 S	669	};
6b5de091 S	670	};