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Merge remote-tracking branch 'mfd/for-mfd-next'
[deliverable/linux.git] / arch / arm / boot / dts / qcom-apq8064.dtsi
CommitLineData
f335b8af
KG		 1/dts-v1/;
2
3#include "skeleton.dtsi"
4#include <dt-bindings/clock/qcom,gcc-msm8960.h>
223280b1 5#include <dt-bindings/reset/qcom,gcc-msm8960.h>
3fe5e3ce 6#include <dt-bindings/clock/qcom,mmcc-msm8960.h>
f335b8af 7#include <dt-bindings/soc/qcom,gsbi.h>
ca88696e 8#include <dt-bindings/interrupt-controller/irq.h>
8b8936fc 9#include <dt-bindings/interrupt-controller/arm-gic.h>
f335b8af
KG		 10/ {
11 model = "Qualcomm APQ8064";
12 compatible = "qcom,apq8064";
13 interrupt-parent = <&intc>;
14
24a9baf9
BA		 15 reserved-memory {
16 #address-cells = <1>;
17 #size-cells = <1>;
18 ranges;
19
20 smem_region: smem@80000000 {
21 reg = <0x80000000 0x200000>;
22 no-map;
23 };
24 };
25
f335b8af
KG		 26 cpus {
27 #address-cells = <1>;
28 #size-cells = <0>;
29
30 cpu@0 {
31 compatible = "qcom,krait";
32 enable-method = "qcom,kpss-acc-v1";
33 device_type = "cpu";
34 reg = <0>;
35 next-level-cache = <&L2>;
36 qcom,acc = <&acc0>;
37 qcom,saw = <&saw0>;
06c49f2b 38 cpu-idle-states = <&CPU_SPC>;
f335b8af
KG		 39 };
40
41 cpu@1 {
42 compatible = "qcom,krait";
43 enable-method = "qcom,kpss-acc-v1";
44 device_type = "cpu";
45 reg = <1>;
46 next-level-cache = <&L2>;
47 qcom,acc = <&acc1>;
48 qcom,saw = <&saw1>;
06c49f2b 49 cpu-idle-states = <&CPU_SPC>;
f335b8af
KG		 50 };
51
52 cpu@2 {
53 compatible = "qcom,krait";
54 enable-method = "qcom,kpss-acc-v1";
55 device_type = "cpu";
56 reg = <2>;
57 next-level-cache = <&L2>;
58 qcom,acc = <&acc2>;
59 qcom,saw = <&saw2>;
06c49f2b 60 cpu-idle-states = <&CPU_SPC>;
f335b8af
KG		 61 };
62
63 cpu@3 {
64 compatible = "qcom,krait";
65 enable-method = "qcom,kpss-acc-v1";
66 device_type = "cpu";
67 reg = <3>;
68 next-level-cache = <&L2>;
69 qcom,acc = <&acc3>;
70 qcom,saw = <&saw3>;
06c49f2b 71 cpu-idle-states = <&CPU_SPC>;
f335b8af
KG		 72 };
73
74 L2: l2-cache {
75 compatible = "cache";
76 cache-level = <2>;
77 };
06c49f2b
LI		 78
79 idle-states {
80 CPU_SPC: spc {
81 compatible = "qcom,idle-state-spc",
82 "arm,idle-state";
83 entry-latency-us = <400>;
84 exit-latency-us = <900>;
85 min-residency-us = <3000>;
86 };
87 };
f335b8af
KG		 88 };
89
c8c87689
RN		 90 thermal-zones {
91 cpu-thermal0 {
92 polling-delay-passive = <250>;
93 polling-delay = <1000>;
94
95 thermal-sensors = <&gcc 7>;
96 coefficients = <1199 0>;
97
98 trips {
99 cpu_alert0: trip0 {
100 temperature = <75000>;
101 hysteresis = <2000>;
102 type = "passive";
103 };
104 cpu_crit0: trip1 {
105 temperature = <110000>;
106 hysteresis = <2000>;
107 type = "critical";
108 };
109 };
110 };
111
112 cpu-thermal1 {
113 polling-delay-passive = <250>;
114 polling-delay = <1000>;
115
116 thermal-sensors = <&gcc 8>;
117 coefficients = <1132 0>;
118
119 trips {
120 cpu_alert1: trip0 {
121 temperature = <75000>;
122 hysteresis = <2000>;
123 type = "passive";
124 };
125 cpu_crit1: trip1 {
126 temperature = <110000>;
127 hysteresis = <2000>;
128 type = "critical";
129 };
130 };
131 };
132
133 cpu-thermal2 {
134 polling-delay-passive = <250>;
135 polling-delay = <1000>;
136
137 thermal-sensors = <&gcc 9>;
138 coefficients = <1199 0>;
139
140 trips {
141 cpu_alert2: trip0 {
142 temperature = <75000>;
143 hysteresis = <2000>;
144 type = "passive";
145 };
146 cpu_crit2: trip1 {
147 temperature = <110000>;
148 hysteresis = <2000>;
149 type = "critical";
150 };
151 };
152 };
153
154 cpu-thermal3 {
155 polling-delay-passive = <250>;
156 polling-delay = <1000>;
157
158 thermal-sensors = <&gcc 10>;
159 coefficients = <1132 0>;
160
161 trips {
162 cpu_alert3: trip0 {
163 temperature = <75000>;
164 hysteresis = <2000>;
165 type = "passive";
166 };
167 cpu_crit3: trip1 {
168 temperature = <110000>;
169 hysteresis = <2000>;
170 type = "critical";
171 };
172 };
173 };
174 };
175
f335b8af
KG		 176 cpu-pmu {
177 compatible = "qcom,krait-pmu";
178 interrupts = <1 10 0x304>;
179 };
180
aa269127
GD		 181 clocks {
182 cxo_board {
183 compatible = "fixed-clock";
184 #clock-cells = <0>;
185 clock-frequency = <19200000>;
186 };
187
188 pxo_board {
189 compatible = "fixed-clock";
190 #clock-cells = <0>;
191 clock-frequency = <27000000>;
192 };
193
194 sleep_clk {
195 compatible = "fixed-clock";
196 #clock-cells = <0>;
197 clock-frequency = <32768>;
198 };
199 };
200
24a9baf9
BA		 201 sfpb_mutex: hwmutex {
202 compatible = "qcom,sfpb-mutex";
203 syscon = <&sfpb_wrapper_mutex 0x604 0x4>;
204 #hwlock-cells = <1>;
205 };
206
207 smem {
208 compatible = "qcom,smem";
209 memory-region = <&smem_region>;
210
211 hwlocks = <&sfpb_mutex 3>;
212 };
213
2afc5287
BA		 214 smd {
215 compatible = "qcom,smd";
216
217 modem@0 {
218 interrupts = <0 37 IRQ_TYPE_EDGE_RISING>;
219
220 qcom,ipc = <&l2cc 8 3>;
221 qcom,smd-edge = <0>;
222
223 status = "disabled";
224 };
225
226 q6@1 {
227 interrupts = <0 90 IRQ_TYPE_EDGE_RISING>;
228
229 qcom,ipc = <&l2cc 8 15>;
230 qcom,smd-edge = <1>;
231
232 status = "disabled";
233 };
234
235 dsps@3 {
236 interrupts = <0 138 IRQ_TYPE_EDGE_RISING>;
237
238 qcom,ipc = <&sps_sic_non_secure 0x4080 0>;
239 qcom,smd-edge = <3>;
240
241 status = "disabled";
242 };
243
244 riva@6 {
245 interrupts = <0 198 IRQ_TYPE_EDGE_RISING>;
246
247 qcom,ipc = <&l2cc 8 25>;
248 qcom,smd-edge = <6>;
249
250 status = "disabled";
251 };
252 };
253
b4d4582f
BA		 254 smsm {
255 compatible = "qcom,smsm";
256
257 #address-cells = <1>;
258 #size-cells = <0>;
259
260 qcom,ipc-1 = <&l2cc 8 4>;
261 qcom,ipc-2 = <&l2cc 8 14>;
262 qcom,ipc-3 = <&l2cc 8 23>;
263 qcom,ipc-4 = <&sps_sic_non_secure 0x4094 0>;
264
265 apps_smsm: apps@0 {
266 reg = <0>;
30f1e2dd 267 #qcom,smem-state-cells = <1>;
b4d4582f
BA		 268 };
269
270 modem_smsm: modem@1 {
271 reg = <1>;
272 interrupts = <0 38 IRQ_TYPE_EDGE_RISING>;
273
274 interrupt-controller;
275 #interrupt-cells = <2>;
276 };
277
278 q6_smsm: q6@2 {
279 reg = <2>;
280 interrupts = <0 89 IRQ_TYPE_EDGE_RISING>;
281
282 interrupt-controller;
283 #interrupt-cells = <2>;
284 };
285
286 wcnss_smsm: wcnss@3 {
287 reg = <3>;
288 interrupts = <0 204 IRQ_TYPE_EDGE_RISING>;
289
290 interrupt-controller;
291 #interrupt-cells = <2>;
292 };
293
294 dsps_smsm: dsps@4 {
295 reg = <4>;
296 interrupts = <0 137 IRQ_TYPE_EDGE_RISING>;
297
298 interrupt-controller;
299 #interrupt-cells = <2>;
300 };
301 };
302
9e5d41d4
AG		 303 firmware {
304 scm {
305 compatible = "qcom,scm-apq8064";
306 };
307 };
308
f335b8af
KG		 309 soc: soc {
310 #address-cells = <1>;
311 #size-cells = <1>;
312 ranges;
313 compatible = "simple-bus";
314
8b8936fc
PG		 315 tlmm_pinmux: pinctrl@800000 {
316 compatible = "qcom,apq8064-pinctrl";
317 reg = <0x800000 0x4000>;
318
319 gpio-controller;
320 #gpio-cells = <2>;
321 interrupt-controller;
322 #interrupt-cells = <2>;
323 interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>;
cd6dd11a
PG		 324
325 pinctrl-names = "default";
326 pinctrl-0 = <&ps_hold>;
8b8936fc
PG		 327 };
328
24a9baf9
BA		 329 sfpb_wrapper_mutex: syscon@1200000 {
330 compatible = "syscon";
331 reg = <0x01200000 0x8000>;
332 };
333
f335b8af
KG		 334 intc: interrupt-controller@2000000 {
335 compatible = "qcom,msm-qgic2";
336 interrupt-controller;
337 #interrupt-cells = <3>;
338 reg = <0x02000000 0x1000>,
339 <0x02002000 0x1000>;
340 };
341
342 timer@200a000 {
6e062696
MM		 343 compatible = "qcom,kpss-timer",
344 "qcom,kpss-wdt-apq8064", "qcom,msm-timer";
f335b8af
KG		 345 interrupts = <1 1 0x301>,
346 <1 2 0x301>,
347 <1 3 0x301>;
348 reg = <0x0200a000 0x100>;
349 clock-frequency = <27000000>,
350 <32768>;
351 cpu-offset = <0x80000>;
352 };
353
354 acc0: clock-controller@2088000 {
355 compatible = "qcom,kpss-acc-v1";
356 reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
357 };
358
359 acc1: clock-controller@2098000 {
360 compatible = "qcom,kpss-acc-v1";
361 reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
362 };
363
364 acc2: clock-controller@20a8000 {
365 compatible = "qcom,kpss-acc-v1";
366 reg = <0x020a8000 0x1000>, <0x02008000 0x1000>;
367 };
368
369 acc3: clock-controller@20b8000 {
370 compatible = "qcom,kpss-acc-v1";
371 reg = <0x020b8000 0x1000>, <0x02008000 0x1000>;
372 };
373
9fc23ce3
LI		 374 saw0: power-controller@2089000 {
375 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
f335b8af
KG		 376 reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
377 regulator;
378 };
379
9fc23ce3
LI		 380 saw1: power-controller@2099000 {
381 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
f335b8af
KG		 382 reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
383 regulator;
384 };
385
9fc23ce3
LI		 386 saw2: power-controller@20a9000 {
387 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
f335b8af
KG		 388 reg = <0x020a9000 0x1000>, <0x02009000 0x1000>;
389 regulator;
390 };
391
9fc23ce3
LI		 392 saw3: power-controller@20b9000 {
393 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
f335b8af
KG		 394 reg = <0x020b9000 0x1000>, <0x02009000 0x1000>;
395 regulator;
396 };
397
b9e4c5e6
BA		 398 sps_sic_non_secure: sps-sic-non-secure@12100000 {
399 compatible = "syscon";
400 reg = <0x12100000 0x10000>;
401 };
402
8c3166f5 403 gsbi1: gsbi@12440000 {
404 status = "disabled";
405 compatible = "qcom,gsbi-v1.0.0";
4105d9d6 406 cell-index = <1>;
8c3166f5 407 reg = <0x12440000 0x100>;
408 clocks = <&gcc GSBI1_H_CLK>;
409 clock-names = "iface";
410 #address-cells = <1>;
411 #size-cells = <1>;
412 ranges;
413
4105d9d6
AG		 414 syscon-tcsr = <&tcsr>;
415
12861674
SK		 416 gsbi1_serial: serial@12450000 {
417 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
418 reg = <0x12450000 0x100>,
419 <0x12400000 0x03>;
420 interrupts = <0 193 0x0>;
421 clocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>;
422 clock-names = "core", "iface";
423 status = "disabled";
424 };
425
e07214db 426 gsbi1_i2c: i2c@12460000 {
8c3166f5 427 compatible = "qcom,i2c-qup-v1.1.1";
67b5ad57
SK		 428 pinctrl-0 = <&i2c1_pins>;
429 pinctrl-1 = <&i2c1_pins_sleep>;
64b22b25 430 pinctrl-names = "default", "sleep";
8c3166f5 431 reg = <0x12460000 0x1000>;
432 interrupts = <0 194 IRQ_TYPE_NONE>;
433 clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
434 clock-names = "core", "iface";
435 #address-cells = <1>;
436 #size-cells = <0>;
437 };
b2dc04c5 438
8c3166f5 439 };
440
441 gsbi2: gsbi@12480000 {
442 status = "disabled";
443 compatible = "qcom,gsbi-v1.0.0";
4105d9d6 444 cell-index = <2>;
8c3166f5 445 reg = <0x12480000 0x100>;
446 clocks = <&gcc GSBI2_H_CLK>;
447 clock-names = "iface";
448 #address-cells = <1>;
449 #size-cells = <1>;
450 ranges;
451
4105d9d6
AG		 452 syscon-tcsr = <&tcsr>;
453
e07214db 454 gsbi2_i2c: i2c@124a0000 {
8c3166f5 455 compatible = "qcom,i2c-qup-v1.1.1";
456 reg = <0x124a0000 0x1000>;
67b5ad57
SK		 457 pinctrl-0 = <&i2c2_pins>;
458 pinctrl-1 = <&i2c2_pins_sleep>;
7788d439 459 pinctrl-names = "default", "sleep";
8c3166f5 460 interrupts = <0 196 IRQ_TYPE_NONE>;
461 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
462 clock-names = "core", "iface";
463 #address-cells = <1>;
464 #size-cells = <0>;
465 };
466 };
467
3f62b46b
SK		 468 gsbi3: gsbi@16200000 {
469 status = "disabled";
470 compatible = "qcom,gsbi-v1.0.0";
504155ca 471 cell-index = <3>;
3f62b46b
SK		 472 reg = <0x16200000 0x100>;
473 clocks = <&gcc GSBI3_H_CLK>;
474 clock-names = "iface";
475 #address-cells = <1>;
476 #size-cells = <1>;
477 ranges;
e07214db 478 gsbi3_i2c: i2c@16280000 {
3f62b46b 479 compatible = "qcom,i2c-qup-v1.1.1";
67b5ad57
SK		 480 pinctrl-0 = <&i2c3_pins>;
481 pinctrl-1 = <&i2c3_pins_sleep>;
64b22b25 482 pinctrl-names = "default", "sleep";
3f62b46b
SK		 483 reg = <0x16280000 0x1000>;
484 interrupts = <GIC_SPI 151 IRQ_TYPE_NONE>;
485 clocks = <&gcc GSBI3_QUP_CLK>,
486 <&gcc GSBI3_H_CLK>;
487 clock-names = "core", "iface";
5d31f606
JS		 488 #address-cells = <1>;
489 #size-cells = <0>;
1099b26e
BA		 490 };
491 };
492
2a5cbc15
SK		 493 gsbi4: gsbi@16300000 {
494 status = "disabled";
495 compatible = "qcom,gsbi-v1.0.0";
496 cell-index = <4>;
497 reg = <0x16300000 0x03>;
498 clocks = <&gcc GSBI4_H_CLK>;
499 clock-names = "iface";
500 #address-cells = <1>;
501 #size-cells = <1>;
502 ranges;
503
504 gsbi4_i2c: i2c@16380000 {
505 compatible = "qcom,i2c-qup-v1.1.1";
67b5ad57
SK		 506 pinctrl-0 = <&i2c4_pins>;
507 pinctrl-1 = <&i2c4_pins_sleep>;
2a5cbc15
SK		 508 pinctrl-names = "default", "sleep";
509 reg = <0x16380000 0x1000>;
510 interrupts = <GIC_SPI 153 IRQ_TYPE_NONE>;
511 clocks = <&gcc GSBI4_QUP_CLK>,
512 <&gcc GSBI4_H_CLK>;
513 clock-names = "core", "iface";
514 };
515 };
516
1099b26e
BA		 517 gsbi5: gsbi@1a200000 {
518 status = "disabled";
519 compatible = "qcom,gsbi-v1.0.0";
520 cell-index = <5>;
521 reg = <0x1a200000 0x03>;
522 clocks = <&gcc GSBI5_H_CLK>;
523 clock-names = "iface";
524 #address-cells = <1>;
525 #size-cells = <1>;
526 ranges;
527
528 gsbi5_serial: serial@1a240000 {
529 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
530 reg = <0x1a240000 0x100>,
531 <0x1a200000 0x03>;
532 interrupts = <0 154 0x0>;
533 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
534 clock-names = "core", "iface";
535 status = "disabled";
3f62b46b 536 };
b2dc04c5
SK		 537
538 gsbi5_spi: spi@1a280000 {
539 compatible = "qcom,spi-qup-v1.1.1";
540 reg = <0x1a280000 0x1000>;
541 interrupts = <0 155 0>;
67b5ad57
SK		 542 pinctrl-0 = <&spi5_default>;
543 pinctrl-1 = <&spi5_sleep>;
b2dc04c5
SK		 544 pinctrl-names = "default", "sleep";
545 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
546 clock-names = "core", "iface";
547 status = "disabled";
548 #address-cells = <1>;
549 #size-cells = <0>;
550 };
3f62b46b
SK		 551 };
552
86e252a4
PG		 553 gsbi6: gsbi@16500000 {
554 status = "disabled";
555 compatible = "qcom,gsbi-v1.0.0";
556 cell-index = <6>;
557 reg = <0x16500000 0x03>;
558 clocks = <&gcc GSBI6_H_CLK>;
559 clock-names = "iface";
560 #address-cells = <1>;
561 #size-cells = <1>;
562 ranges;
563
564 gsbi6_serial: serial@16540000 {
565 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
566 reg = <0x16540000 0x100>,
567 <0x16500000 0x03>;
568 interrupts = <0 156 0x0>;
569 clocks = <&gcc GSBI6_UART_CLK>, <&gcc GSBI6_H_CLK>;
570 clock-names = "core", "iface";
571 status = "disabled";
572 };
806334ed
SK		 573
574 gsbi6_i2c: i2c@16580000 {
575 compatible = "qcom,i2c-qup-v1.1.1";
67b5ad57
SK		 576 pinctrl-0 = <&i2c6_pins>;
577 pinctrl-1 = <&i2c6_pins_sleep>;
806334ed
SK		 578 pinctrl-names = "default", "sleep";
579 reg = <0x16580000 0x1000>;
580 interrupts = <GIC_SPI 157 IRQ_TYPE_NONE>;
581 clocks = <&gcc GSBI6_QUP_CLK>,
582 <&gcc GSBI6_H_CLK>;
583 clock-names = "core", "iface";
584 };
86e252a4
PG		 585 };
586
f335b8af
KG		 587 gsbi7: gsbi@16600000 {
588 status = "disabled";
589 compatible = "qcom,gsbi-v1.0.0";
4105d9d6 590 cell-index = <7>;
f335b8af
KG		 591 reg = <0x16600000 0x100>;
592 clocks = <&gcc GSBI7_H_CLK>;
593 clock-names = "iface";
594 #address-cells = <1>;
595 #size-cells = <1>;
596 ranges;
4105d9d6
AG		 597 syscon-tcsr = <&tcsr>;
598
d5d4654e 599 gsbi7_serial: serial@16640000 {
f335b8af
KG		 600 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
601 reg = <0x16640000 0x1000>,
602 <0x16600000 0x1000>;
603 interrupts = <0 158 0x0>;
604 clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
605 clock-names = "core", "iface";
606 status = "disabled";
607 };
e4b01fda
SK		 608
609 gsbi7_i2c: i2c@16680000 {
610 compatible = "qcom,i2c-qup-v1.1.1";
611 pinctrl-0 = <&i2c7_pins>;
612 pinctrl-1 = <&i2c7_pins_sleep>;
613 pinctrl-names = "default", "sleep";
614 reg = <0x16680000 0x1000>;
615 interrupts = <GIC_SPI 159 IRQ_TYPE_NONE>;
616 clocks = <&gcc GSBI7_QUP_CLK>,
617 <&gcc GSBI7_H_CLK>;
618 clock-names = "core", "iface";
619 status = "disabled";
620 };
f335b8af
KG		 621 };
622
6a607e03
JS		 623 rng@1a500000 {
624 compatible = "qcom,prng";
625 reg = <0x1a500000 0x200>;
626 clocks = <&gcc PRNG_CLK>;
627 clock-names = "core";
628 };
629
f335b8af
KG		 630 qcom,ssbi@500000 {
631 compatible = "qcom,ssbi";
632 reg = <0x00500000 0x1000>;
633 qcom,controller-type = "pmic-arbiter";
874443fe
SK		 634
635 pmicintc: pmic@0 {
636 compatible = "qcom,pm8921";
637 interrupt-parent = <&tlmm_pinmux>;
638 interrupts = <74 8>;
639 #interrupt-cells = <2>;
640 interrupt-controller;
641 #address-cells = <1>;
642 #size-cells = <0>;
643
644 pm8921_gpio: gpio@150 {
645
2ca9c2a4
SB		 646 compatible = "qcom,pm8921-gpio",
647 "qcom,ssbi-gpio";
874443fe 648 reg = <0x150>;
ca88696e
LW		 649 interrupts = <192 IRQ_TYPE_NONE>,
650 <193 IRQ_TYPE_NONE>,
651 <194 IRQ_TYPE_NONE>,
652 <195 IRQ_TYPE_NONE>,
653 <196 IRQ_TYPE_NONE>,
654 <197 IRQ_TYPE_NONE>,
655 <198 IRQ_TYPE_NONE>,
656 <199 IRQ_TYPE_NONE>,
657 <200 IRQ_TYPE_NONE>,
658 <201 IRQ_TYPE_NONE>,
659 <202 IRQ_TYPE_NONE>,
660 <203 IRQ_TYPE_NONE>,
661 <204 IRQ_TYPE_NONE>,
662 <205 IRQ_TYPE_NONE>,
663 <206 IRQ_TYPE_NONE>,
664 <207 IRQ_TYPE_NONE>,
665 <208 IRQ_TYPE_NONE>,
666 <209 IRQ_TYPE_NONE>,
667 <210 IRQ_TYPE_NONE>,
668 <211 IRQ_TYPE_NONE>,
669 <212 IRQ_TYPE_NONE>,
670 <213 IRQ_TYPE_NONE>,
671 <214 IRQ_TYPE_NONE>,
672 <215 IRQ_TYPE_NONE>,
673 <216 IRQ_TYPE_NONE>,
674 <217 IRQ_TYPE_NONE>,
675 <218 IRQ_TYPE_NONE>,
676 <219 IRQ_TYPE_NONE>,
677 <220 IRQ_TYPE_NONE>,
678 <221 IRQ_TYPE_NONE>,
679 <222 IRQ_TYPE_NONE>,
680 <223 IRQ_TYPE_NONE>,
681 <224 IRQ_TYPE_NONE>,
682 <225 IRQ_TYPE_NONE>,
683 <226 IRQ_TYPE_NONE>,
684 <227 IRQ_TYPE_NONE>,
685 <228 IRQ_TYPE_NONE>,
686 <229 IRQ_TYPE_NONE>,
687 <230 IRQ_TYPE_NONE>,
688 <231 IRQ_TYPE_NONE>,
689 <232 IRQ_TYPE_NONE>,
690 <233 IRQ_TYPE_NONE>,
691 <234 IRQ_TYPE_NONE>,
692 <235 IRQ_TYPE_NONE>;
874443fe
SK		 693 gpio-controller;
694 #gpio-cells = <2>;
695
696 };
bce36046
SK		 697
698 pm8921_mpps: mpps@50 {
2ca9c2a4
SB		 699 compatible = "qcom,pm8921-mpp",
700 "qcom,ssbi-mpp";
bce36046
SK		 701 reg = <0x50>;
702 gpio-controller;
703 #gpio-cells = <2>;
704 interrupts =
ca88696e
LW		 705 <128 IRQ_TYPE_NONE>,
706 <129 IRQ_TYPE_NONE>,
707 <130 IRQ_TYPE_NONE>,
708 <131 IRQ_TYPE_NONE>,
709 <132 IRQ_TYPE_NONE>,
710 <133 IRQ_TYPE_NONE>,
711 <134 IRQ_TYPE_NONE>,
712 <135 IRQ_TYPE_NONE>,
713 <136 IRQ_TYPE_NONE>,
714 <137 IRQ_TYPE_NONE>,
715 <138 IRQ_TYPE_NONE>,
716 <139 IRQ_TYPE_NONE>;
bce36046
SK		 717 };
718
bbf89b96
SK		 719 rtc@11d {
720 compatible = "qcom,pm8921-rtc";
721 interrupt-parent = <&pmicintc>;
722 interrupts = <39 1>;
723 reg = <0x11d>;
724 allow-set-time;
725 };
726
3050c5f5
SK		 727 pwrkey@1c {
728 compatible = "qcom,pm8921-pwrkey";
729 reg = <0x1c>;
730 interrupt-parent = <&pmicintc>;
731 interrupts = <50 1>, <51 1>;
732 debounce = <15625>;
733 pull-up;
734 };
874443fe 735 };
f335b8af
KG		 736 };
737
c8c87689
RN		 738 qfprom: qfprom@700000 {
739 compatible = "qcom,qfprom";
740 reg = <0x00700000 0x1000>;
741 #address-cells = <1>;
742 #size-cells = <1>;
743 ranges;
744 tsens_calib: calib {
745 reg = <0x404 0x10>;
746 };
747 tsens_backup: backup_calib {
748 reg = <0x414 0x10>;
749 };
750 };
751
f335b8af
KG		 752 gcc: clock-controller@900000 {
753 compatible = "qcom,gcc-apq8064";
754 reg = <0x00900000 0x4000>;
c8c87689
RN		 755 nvmem-cells = <&tsens_calib>, <&tsens_backup>;
756 nvmem-cell-names = "calib", "calib_backup";
f335b8af
KG		 757 #clock-cells = <1>;
758 #reset-cells = <1>;
c8c87689 759 #thermal-sensor-cells = <1>;
f335b8af 760 };
3fe5e3ce 761
1e1177bf
KG		 762 lcc: clock-controller@28000000 {
763 compatible = "qcom,lcc-apq8064";
764 reg = <0x28000000 0x1000>;
765 #clock-cells = <1>;
766 #reset-cells = <1>;
767 };
768
3fe5e3ce
SB		 769 mmcc: clock-controller@4000000 {
770 compatible = "qcom,mmcc-apq8064";
771 reg = <0x4000000 0x1000>;
772 #clock-cells = <1>;
773 #reset-cells = <1>;
774 };
045644ff 775
dc2f8152
SK		 776 l2cc: clock-controller@2011000 {
777 compatible = "syscon";
778 reg = <0x2011000 0x1000>;
779 };
780
781 rpm@108000 {
782 compatible = "qcom,rpm-apq8064";
783 reg = <0x108000 0x1000>;
784 qcom,ipc = <&l2cc 0x8 2>;
785
786 interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
787 <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
788 <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
789 interrupt-names = "ack", "err", "wakeup";
790
aac1b297
GD		 791 rpmcc: clock-controller {
792 compatible = "qcom,rpmcc-apq8064", "qcom,rpmcc";
793 #clock-cells = <1>;
794 };
795
dc2f8152
SK		 796 regulators {
797 compatible = "qcom,rpm-pm8921-regulators";
798
2bce6e26
BA		 799 pm8921_s1: s1 {};
800 pm8921_s2: s2 {};
801 pm8921_s3: s3 {};
802 pm8921_s4: s4 {};
803 pm8921_s7: s7 {};
804 pm8921_s8: s8 {};
805
806 pm8921_l1: l1 {};
807 pm8921_l2: l2 {};
808 pm8921_l3: l3 {};
809 pm8921_l4: l4 {};
810 pm8921_l5: l5 {};
811 pm8921_l6: l6 {};
812 pm8921_l7: l7 {};
813 pm8921_l8: l8 {};
814 pm8921_l9: l9 {};
815 pm8921_l10: l10 {};
816 pm8921_l11: l11 {};
817 pm8921_l12: l12 {};
818 pm8921_l14: l14 {};
819 pm8921_l15: l15 {};
820 pm8921_l16: l16 {};
821 pm8921_l17: l17 {};
822 pm8921_l18: l18 {};
823 pm8921_l21: l21 {};
824 pm8921_l22: l22 {};
825 pm8921_l23: l23 {};
826 pm8921_l24: l24 {};
827 pm8921_l25: l25 {};
828 pm8921_l26: l26 {};
829 pm8921_l27: l27 {};
830 pm8921_l28: l28 {};
831 pm8921_l29: l29 {};
832
833 pm8921_lvs1: lvs1 {};
834 pm8921_lvs2: lvs2 {};
835 pm8921_lvs3: lvs3 {};
836 pm8921_lvs4: lvs4 {};
837 pm8921_lvs5: lvs5 {};
838 pm8921_lvs6: lvs6 {};
839 pm8921_lvs7: lvs7 {};
840
841 pm8921_usb_switch: usb-switch {};
842
dc2f8152
SK		 843 pm8921_hdmi_switch: hdmi-switch {
844 bias-pull-down;
845 };
2bce6e26
BA		 846
847 pm8921_ncp: ncp {};
dc2f8152
SK		 848 };
849 };
850
ea986611
SK		 851 usb1_phy: phy@12500000 {
852 compatible = "qcom,usb-otg-ci";
853 reg = <0x12500000 0x400>;
854 interrupts = <GIC_SPI 100 IRQ_TYPE_NONE>;
855 status = "disabled";
ea986611
SK		 856
857 clocks = <&gcc USB_HS1_XCVR_CLK>,
858 <&gcc USB_HS1_H_CLK>;
859 clock-names = "core", "iface";
860
861 resets = <&gcc USB_HS1_RESET>;
862 reset-names = "link";
863 };
864
223280b1
SK		 865 usb3_phy: phy@12520000 {
866 compatible = "qcom,usb-otg-ci";
867 reg = <0x12520000 0x400>;
868 interrupts = <GIC_SPI 188 IRQ_TYPE_NONE>;
869 status = "disabled";
870 dr_mode = "host";
871
872 clocks = <&gcc USB_HS3_XCVR_CLK>,
873 <&gcc USB_HS3_H_CLK>;
874 clock-names = "core", "iface";
875
876 resets = <&gcc USB_HS3_RESET>;
877 reset-names = "link";
878 };
879
880 usb4_phy: phy@12530000 {
881 compatible = "qcom,usb-otg-ci";
882 reg = <0x12530000 0x400>;
883 interrupts = <GIC_SPI 215 IRQ_TYPE_NONE>;
884 status = "disabled";
885 dr_mode = "host";
886
887 clocks = <&gcc USB_HS4_XCVR_CLK>,
888 <&gcc USB_HS4_H_CLK>;
889 clock-names = "core", "iface";
890
891 resets = <&gcc USB_HS4_RESET>;
892 reset-names = "link";
893 };
894
ea986611
SK		 895 gadget1: gadget@12500000 {
896 compatible = "qcom,ci-hdrc";
897 reg = <0x12500000 0x400>;
898 status = "disabled";
899 dr_mode = "peripheral";
900 interrupts = <GIC_SPI 100 IRQ_TYPE_NONE>;
901 usb-phy = <&usb1_phy>;
902 };
903
904 usb1: usb@12500000 {
905 compatible = "qcom,ehci-host";
906 reg = <0x12500000 0x400>;
907 interrupts = <GIC_SPI 100 IRQ_TYPE_NONE>;
908 status = "disabled";
909 usb-phy = <&usb1_phy>;
910 };
911
223280b1
SK		 912 usb3: usb@12520000 {
913 compatible = "qcom,ehci-host";
914 reg = <0x12520000 0x400>;
915 interrupts = <GIC_SPI 188 IRQ_TYPE_NONE>;
916 status = "disabled";
917 usb-phy = <&usb3_phy>;
918 };
919
920 usb4: usb@12530000 {
921 compatible = "qcom,ehci-host";
922 reg = <0x12530000 0x400>;
923 interrupts = <GIC_SPI 215 IRQ_TYPE_NONE>;
924 status = "disabled";
925 usb-phy = <&usb4_phy>;
926 };
927
e629335f
SK		 928 sata_phy0: phy@1b400000 {
929 compatible = "qcom,apq8064-sata-phy";
930 status = "disabled";
931 reg = <0x1b400000 0x200>;
932 reg-names = "phy_mem";
933 clocks = <&gcc SATA_PHY_CFG_CLK>;
934 clock-names = "cfg";
935 #phy-cells = <0>;
936 };
937
938 sata0: sata@29000000 {
bb4add2c 939 compatible = "qcom,apq8064-ahci", "generic-ahci";
e629335f
SK		 940 status = "disabled";
941 reg = <0x29000000 0x180>;
942 interrupts = <GIC_SPI 209 IRQ_TYPE_NONE>;
943
944 clocks = <&gcc SFAB_SATA_S_H_CLK>,
945 <&gcc SATA_H_CLK>,
946 <&gcc SATA_A_CLK>,
947 <&gcc SATA_RXOOB_CLK>,
948 <&gcc SATA_PMALIVE_CLK>;
949 clock-names = "slave_iface",
950 "iface",
951 "bus",
952 "rxoob",
953 "core_pmalive";
954
955 assigned-clocks = <&gcc SATA_RXOOB_CLK>,
956 <&gcc SATA_PMALIVE_CLK>;
957 assigned-clock-rates = <100000000>, <100000000>;
958
959 phys = <&sata_phy0>;
960 phy-names = "sata-phy";
bb4add2c 961 ports-implemented = <0x1>;
e629335f
SK		 962 };
963
045644ff 964 /* Temporary fixed regulator */
edb81ca3
SK		 965 sdcc1bam:dma@12402000{
966 compatible = "qcom,bam-v1.3.0";
967 reg = <0x12402000 0x8000>;
968 interrupts = <0 98 0>;
969 clocks = <&gcc SDC1_H_CLK>;
970 clock-names = "bam_clk";
971 #dma-cells = <1>;
972 qcom,ee = <0>;
973 };
974
975 sdcc3bam:dma@12182000{
976 compatible = "qcom,bam-v1.3.0";
977 reg = <0x12182000 0x8000>;
978 interrupts = <0 96 0>;
979 clocks = <&gcc SDC3_H_CLK>;
980 clock-names = "bam_clk";
981 #dma-cells = <1>;
982 qcom,ee = <0>;
983 };
984
0be5fef1
SK		 985 sdcc4bam:dma@121c2000{
986 compatible = "qcom,bam-v1.3.0";
987 reg = <0x121c2000 0x8000>;
988 interrupts = <0 95 0>;
989 clocks = <&gcc SDC4_H_CLK>;
990 clock-names = "bam_clk";
991 #dma-cells = <1>;
992 qcom,ee = <0>;
993 };
994
045644ff 995 amba {
2ef7d5f3 996 compatible = "simple-bus";
045644ff
SK		 997 #address-cells = <1>;
998 #size-cells = <1>;
999 ranges;
1000 sdcc1: sdcc@12400000 {
1001 status = "disabled";
1002 compatible = "arm,pl18x", "arm,primecell";
ccd140b5
SK		 1003 pinctrl-names = "default";
1004 pinctrl-0 = <&sdcc1_pins>;
045644ff
SK		 1005 arm,primecell-periphid = <0x00051180>;
1006 reg = <0x12400000 0x2000>;
1007 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
1008 interrupt-names = "cmd_irq";
1009 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
1010 clock-names = "mclk", "apb_pclk";
1011 bus-width = <8>;
1012 max-frequency = <96000000>;
1013 non-removable;
1014 cap-sd-highspeed;
1015 cap-mmc-highspeed;
edb81ca3
SK		 1016 dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
1017 dma-names = "tx", "rx";
045644ff
SK		 1018 };
1019
1020 sdcc3: sdcc@12180000 {
1021 compatible = "arm,pl18x", "arm,primecell";
1022 arm,primecell-periphid = <0x00051180>;
1023 status = "disabled";
1024 reg = <0x12180000 0x2000>;
1025 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
1026 interrupt-names = "cmd_irq";
1027 clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
1028 clock-names = "mclk", "apb_pclk";
1029 bus-width = <4>;
1030 cap-sd-highspeed;
1031 cap-mmc-highspeed;
1032 max-frequency = <192000000>;
1033 no-1-8-v;
edb81ca3
SK		 1034 dmas = <&sdcc3bam 2>, <&sdcc3bam 1>;
1035 dma-names = "tx", "rx";
045644ff 1036 };
0be5fef1
SK		 1037
1038 sdcc4: sdcc@121c0000 {
1039 compatible = "arm,pl18x", "arm,primecell";
1040 arm,primecell-periphid = <0x00051180>;
1041 status = "disabled";
1042 reg = <0x121c0000 0x2000>;
1043 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1044 interrupt-names = "cmd_irq";
1045 clocks = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>;
1046 clock-names = "mclk", "apb_pclk";
1047 bus-width = <4>;
1048 cap-sd-highspeed;
1049 cap-mmc-highspeed;
1050 max-frequency = <48000000>;
0be5fef1
SK		 1051 dmas = <&sdcc4bam 2>, <&sdcc4bam 1>;
1052 dma-names = "tx", "rx";
1053 pinctrl-names = "default";
1054 pinctrl-0 = <&sdc4_gpios>;
1055 };
045644ff 1056 };
4105d9d6
AG		 1057
1058 tcsr: syscon@1a400000 {
1059 compatible = "qcom,tcsr-apq8064", "syscon";
1060 reg = <0x1a400000 0x100>;
1061 };
bcc74b09
SV		 1062
1063 pcie: pci@1b500000 {
1064 compatible = "qcom,pcie-apq8064", "snps,dw-pcie";
1065 reg = <0x1b500000 0x1000
1066 0x1b502000 0x80
1067 0x1b600000 0x100
1068 0x0ff00000 0x100000>;
1069 reg-names = "dbi", "elbi", "parf", "config";
1070 device_type = "pci";
1071 linux,pci-domain = <0>;
1072 bus-range = <0x00 0xff>;
1073 num-lanes = <1>;
1074 #address-cells = <3>;
1075 #size-cells = <2>;
1076 ranges = <0x81000000 0 0 0x0fe00000 0 0x00100000 /* I/O */
1077 0x82000000 0 0 0x08000000 0 0x07e00000>; /* memory */
1078 interrupts = <GIC_SPI 238 IRQ_TYPE_NONE>;
1079 interrupt-names = "msi";
1080 #interrupt-cells = <1>;
1081 interrupt-map-mask = <0 0 0 0x7>;
1082 interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1083 <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1084 <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1085 <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1086 clocks = <&gcc PCIE_A_CLK>,
1087 <&gcc PCIE_H_CLK>,
1088 <&gcc PCIE_PHY_REF_CLK>;
1089 clock-names = "core", "iface", "phy";
1090 resets = <&gcc PCIE_ACLK_RESET>,
1091 <&gcc PCIE_HCLK_RESET>,
1092 <&gcc PCIE_POR_RESET>,
1093 <&gcc PCIE_PCI_RESET>,
1094 <&gcc PCIE_PHY_RESET>;
1095 reset-names = "axi", "ahb", "por", "pci", "phy";
1096 status = "disabled";
1097 };
f335b8af
KG		 1098 };
1099};
a30e78bd 1100#include "qcom-apq8064-pins.dtsi"
Linux kernel - Deliverables
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