[deliverable/linux.git] / arch / arm / boot / dts / r7s72100.dtsi

/*
 * Device Tree Source for the r7s72100 SoC
 *
 * Copyright (C) 2013-14 Renesas Solutions Corp.
 * Copyright (C) 2014 Wolfram Sang, Sang Engineering <wsa@sang-engineering.com>
 *
 * This file is licensed under the terms of the GNU General Public License
 * version 2.  This program is licensed "as is" without any warranty of any
 * kind, whether express or implied.
 */

#include <dt-bindings/clock/r7s72100-clock.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>

/ {
	compatible = "renesas,r7s72100";
	interrupt-parent = <&gic>;
	#address-cells = <1>;
	#size-cells = <1>;

	aliases {
		i2c0 = &i2c0;
		i2c1 = &i2c1;
		i2c2 = &i2c2;
		i2c3 = &i2c3;
		spi0 = &spi0;
		spi1 = &spi1;
		spi2 = &spi2;
		spi3 = &spi3;
		spi4 = &spi4;
	};

	clocks {
		ranges;
		#address-cells = <1>;
		#size-cells = <1>;

		/* External clocks */
		extal_clk: extal {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			/* If clk present, value must be set by board */
			clock-frequency = <0>;
		};

		usb_x1_clk: usb_x1 {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			/* If clk present, value must be set by board */
			clock-frequency = <0>;
		};

		/* Fixed factor clocks */
		b_clk: b {
			#clock-cells = <0>;
			compatible = "fixed-factor-clock";
			clocks = <&cpg_clocks R7S72100_CLK_PLL>;
			clock-mult = <1>;
			clock-div = <3>;
		};
		p1_clk: p1 {
			#clock-cells = <0>;
			compatible = "fixed-factor-clock";
			clocks = <&cpg_clocks R7S72100_CLK_PLL>;
			clock-mult = <1>;
			clock-div = <6>;
		};
		p0_clk: p0 {
			#clock-cells = <0>;
			compatible = "fixed-factor-clock";
			clocks = <&cpg_clocks R7S72100_CLK_PLL>;
			clock-mult = <1>;
			clock-div = <12>;
		};

		/* Special CPG clocks */
		cpg_clocks: cpg_clocks@fcfe0000 {
			#clock-cells = <1>;
			compatible = "renesas,r7s72100-cpg-clocks",
				     "renesas,rz-cpg-clocks";
			reg = <0xfcfe0000 0x18>;
			clocks = <&extal_clk>, <&usb_x1_clk>;
			clock-output-names = "pll", "i", "g";
			#power-domain-cells = <0>;
		};

		/* MSTP clocks */
		mstp3_clks: mstp3_clks@fcfe0420 {
			#clock-cells = <1>;
			compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
			reg = <0xfcfe0420 4>;
			clocks = <&p0_clk>;
			clock-indices = <R7S72100_CLK_MTU2>;
			clock-output-names = "mtu2";
		};

		mstp4_clks: mstp4_clks@fcfe0424 {
			#clock-cells = <1>;
			compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
			reg = <0xfcfe0424 4>;
			clocks = <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>,
				 <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>;
			clock-indices = <
				R7S72100_CLK_SCIF0 R7S72100_CLK_SCIF1 R7S72100_CLK_SCIF2 R7S72100_CLK_SCIF3
				R7S72100_CLK_SCIF4 R7S72100_CLK_SCIF5 R7S72100_CLK_SCIF6 R7S72100_CLK_SCIF7
			>;
			clock-output-names = "scif0", "scif1", "scif2", "scif3", "scif4", "scif5", "scif6", "scif7";
		};

		mstp7_clks: mstp7_clks@fcfe0430 {
			#clock-cells = <1>;
			compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
			reg = <0xfcfe0430 4>;
			clocks = <&p0_clk>;
			clock-indices = <R7S72100_CLK_ETHER>;
			clock-output-names = "ether";
		};

		mstp9_clks: mstp9_clks@fcfe0438 {
			#clock-cells = <1>;
			compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
			reg = <0xfcfe0438 4>;
			clocks = <&p0_clk>, <&p0_clk>, <&p0_clk>, <&p0_clk>;
			clock-indices = <
				R7S72100_CLK_I2C0 R7S72100_CLK_I2C1 R7S72100_CLK_I2C2 R7S72100_CLK_I2C3
			>;
			clock-output-names = "i2c0", "i2c1", "i2c2", "i2c3";
		};

		mstp10_clks: mstp10_clks@fcfe043c {
			#clock-cells = <1>;
			compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
			reg = <0xfcfe043c 4>;
			clocks = <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>,
				 <&p1_clk>;
			clock-indices = <
				R7S72100_CLK_SPI0 R7S72100_CLK_SPI1 R7S72100_CLK_SPI2 R7S72100_CLK_SPI3
				R7S72100_CLK_SPI4
			>;
			clock-output-names = "spi0", "spi1", "spi2", "spi3", "spi4";
		};
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <0>;
			clock-frequency = <400000000>;
		};
	};

	scif0: serial@e8007000 {
		compatible = "renesas,scif-r7s72100", "renesas,scif";
		reg = <0xe8007000 64>;
		interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp4_clks R7S72100_CLK_SCIF0>;
		clock-names = "fck";
		power-domains = <&cpg_clocks>;
		status = "disabled";
	};

	scif1: serial@e8007800 {
		compatible = "renesas,scif-r7s72100", "renesas,scif";
		reg = <0xe8007800 64>;
		interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp4_clks R7S72100_CLK_SCIF1>;
		clock-names = "fck";
		power-domains = <&cpg_clocks>;
		status = "disabled";
	};

	scif2: serial@e8008000 {
		compatible = "renesas,scif-r7s72100", "renesas,scif";
		reg = <0xe8008000 64>;
		interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp4_clks R7S72100_CLK_SCIF2>;
		clock-names = "fck";
		power-domains = <&cpg_clocks>;
		status = "disabled";
	};

	scif3: serial@e8008800 {
		compatible = "renesas,scif-r7s72100", "renesas,scif";
		reg = <0xe8008800 64>;
		interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp4_clks R7S72100_CLK_SCIF3>;
		clock-names = "fck";
		power-domains = <&cpg_clocks>;
		status = "disabled";
	};

	scif4: serial@e8009000 {
		compatible = "renesas,scif-r7s72100", "renesas,scif";
		reg = <0xe8009000 64>;
		interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp4_clks R7S72100_CLK_SCIF4>;
		clock-names = "fck";
		power-domains = <&cpg_clocks>;
		status = "disabled";
	};

	scif5: serial@e8009800 {
		compatible = "renesas,scif-r7s72100", "renesas,scif";
		reg = <0xe8009800 64>;
		interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp4_clks R7S72100_CLK_SCIF5>;
		clock-names = "fck";
		power-domains = <&cpg_clocks>;
		status = "disabled";
	};

	scif6: serial@e800a000 {
		compatible = "renesas,scif-r7s72100", "renesas,scif";
		reg = <0xe800a000 64>;
		interrupts = <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp4_clks R7S72100_CLK_SCIF6>;
		clock-names = "fck";
		power-domains = <&cpg_clocks>;
		status = "disabled";
	};

	scif7: serial@e800a800 {
		compatible = "renesas,scif-r7s72100", "renesas,scif";
		reg = <0xe800a800 64>;
		interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp4_clks R7S72100_CLK_SCIF7>;
		clock-names = "fck";
		power-domains = <&cpg_clocks>;
		status = "disabled";
	};

	spi0: spi@e800c800 {
		compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
		reg = <0xe800c800 0x24>;
		interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "error", "rx", "tx";
		clocks = <&mstp10_clks R7S72100_CLK_SPI0>;
		power-domains = <&cpg_clocks>;
		num-cs = <1>;
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
	};

	spi1: spi@e800d000 {
		compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
		reg = <0xe800d000 0x24>;
		interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "error", "rx", "tx";
		clocks = <&mstp10_clks R7S72100_CLK_SPI1>;
		power-domains = <&cpg_clocks>;
		num-cs = <1>;
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
	};

	spi2: spi@e800d800 {
		compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
		reg = <0xe800d800 0x24>;
		interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "error", "rx", "tx";
		clocks = <&mstp10_clks R7S72100_CLK_SPI2>;
		power-domains = <&cpg_clocks>;
		num-cs = <1>;
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
	};

	spi3: spi@e800e000 {
		compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
		reg = <0xe800e000 0x24>;
		interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "error", "rx", "tx";
		clocks = <&mstp10_clks R7S72100_CLK_SPI3>;
		power-domains = <&cpg_clocks>;
		num-cs = <1>;
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
	};

	spi4: spi@e800e800 {
		compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
		reg = <0xe800e800 0x24>;
		interrupts = <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "error", "rx", "tx";
		clocks = <&mstp10_clks R7S72100_CLK_SPI4>;
		power-domains = <&cpg_clocks>;
		num-cs = <1>;
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
	};

	gic: interrupt-controller@e8201000 {
		compatible = "arm,pl390";
		#interrupt-cells = <3>;
		#address-cells = <0>;
		interrupt-controller;
		reg = <0xe8201000 0x1000>,
			<0xe8202000 0x1000>;
	};

	i2c0: i2c@fcfee000 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
		reg = <0xfcfee000 0x44>;
		interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>,
			     <GIC_SPI 159 IRQ_TYPE_EDGE_RISING>,
			     <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp9_clks R7S72100_CLK_I2C0>;
		clock-frequency = <100000>;
		power-domains = <&cpg_clocks>;
		status = "disabled";
	};

	i2c1: i2c@fcfee400 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
		reg = <0xfcfee400 0x44>;
		interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 166 IRQ_TYPE_EDGE_RISING>,
			     <GIC_SPI 167 IRQ_TYPE_EDGE_RISING>,
			     <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp9_clks R7S72100_CLK_I2C1>;
		clock-frequency = <100000>;
		power-domains = <&cpg_clocks>;
		status = "disabled";
	};

	i2c2: i2c@fcfee800 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
		reg = <0xfcfee800 0x44>;
		interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 174 IRQ_TYPE_EDGE_RISING>,
			     <GIC_SPI 175 IRQ_TYPE_EDGE_RISING>,
			     <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp9_clks R7S72100_CLK_I2C2>;
		clock-frequency = <100000>;
		power-domains = <&cpg_clocks>;
		status = "disabled";
	};

	i2c3: i2c@fcfeec00 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
		reg = <0xfcfeec00 0x44>;
		interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 182 IRQ_TYPE_EDGE_RISING>,
			     <GIC_SPI 183 IRQ_TYPE_EDGE_RISING>,
			     <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp9_clks R7S72100_CLK_I2C3>;
		clock-frequency = <100000>;
		power-domains = <&cpg_clocks>;
		status = "disabled";
	};

	mtu2: timer@fcff0000 {
		compatible = "renesas,mtu2-r7s72100", "renesas,mtu2";
		reg = <0xfcff0000 0x400>;
		interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "tgi0a";
		clocks = <&mstp3_clks R7S72100_CLK_MTU2>;
		clock-names = "fck";
		power-domains = <&cpg_clocks>;
		status = "disabled";
	};

	ether: ethernet@e8203000 {
		compatible = "renesas,ether-r7s72100";
		reg = <0xe8203000 0x800>,
		      <0xe8204800 0x200>;
		interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp7_clks R7S72100_CLK_ETHER>;
		power-domains = <&cpg_clocks>;
		phy-mode = "mii";
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
	};
};
Commit	Line	Data
e3da5b36 MD	1	/*
	2	* Device Tree Source for the r7s72100 SoC
	3	*
b6face40 WS	4	* Copyright (C) 2013-14 Renesas Solutions Corp.
b6face40 WS	5	* Copyright (C) 2014 Wolfram Sang, Sang Engineering <wsa@sang-engineering.com>
e3da5b36 MD	6	*
	7	* This file is licensed under the terms of the GNU General Public License
	8	* version 2. This program is licensed "as is" without any warranty of any
	9	* kind, whether express or implied.
	10	*/
	11
b6face40	12	#include <dt-bindings/clock/r7s72100-clock.h>
16af4e97	13	#include <dt-bindings/interrupt-controller/arm-gic.h>
4b18e83f GU	14	#include <dt-bindings/interrupt-controller/irq.h>
4b18e83f GU	15
e3da5b36 MD	16	/ {
	17	compatible = "renesas,r7s72100";
	18	interrupt-parent = <&gic>;
	19	#address-cells = <1>;
	20	#size-cells = <1>;
	21
4b18e83f	22	aliases {
c81a4d3d WS	23	i2c0 = &i2c0;
	24	i2c1 = &i2c1;
	25	i2c2 = &i2c2;
	26	i2c3 = &i2c3;
4b18e83f GU	27	spi0 = &spi0;
	28	spi1 = &spi1;
	29	spi2 = &spi2;
	30	spi3 = &spi3;
	31	spi4 = &spi4;
	32	};
	33
b6face40 WS	34	clocks {
	35	ranges;
	36	#address-cells = <1>;
	37	#size-cells = <1>;
	38
	39	/* External clocks */
21f18970	40	extal_clk: extal {
b6face40 WS	41	#clock-cells = <0>;
	42	compatible = "fixed-clock";
	43	/* If clk present, value must be set by board */
	44	clock-frequency = <0>;
b6face40 WS	45	};
b6face40 WS	46
21f18970	47	usb_x1_clk: usb_x1 {
b6face40 WS	48	#clock-cells = <0>;
	49	compatible = "fixed-clock";
	50	/* If clk present, value must be set by board */
	51	clock-frequency = <0>;
b6face40 WS	52	};
b6face40 WS	53
b6face40	54	/* Fixed factor clocks */
21f18970	55	b_clk: b {
b6face40 WS	56	#clock-cells = <0>;
	57	compatible = "fixed-factor-clock";
	58	clocks = <&cpg_clocks R7S72100_CLK_PLL>;
	59	clock-mult = <1>;
	60	clock-div = <3>;
b6face40	61	};
21f18970	62	p1_clk: p1 {
b6face40 WS	63	#clock-cells = <0>;
	64	compatible = "fixed-factor-clock";
	65	clocks = <&cpg_clocks R7S72100_CLK_PLL>;
	66	clock-mult = <1>;
	67	clock-div = <6>;
b6face40	68	};
21f18970	69	p0_clk: p0 {
b6face40 WS	70	#clock-cells = <0>;
	71	compatible = "fixed-factor-clock";
	72	clocks = <&cpg_clocks R7S72100_CLK_PLL>;
	73	clock-mult = <1>;
	74	clock-div = <12>;
b6face40 WS	75	};
b6face40 WS	76
005980c0 UH	77	/* Special CPG clocks */
	78	cpg_clocks: cpg_clocks@fcfe0000 {
	79	#clock-cells = <1>;
	80	compatible = "renesas,r7s72100-cpg-clocks",
	81	"renesas,rz-cpg-clocks";
	82	reg = <0xfcfe0000 0x18>;
	83	clocks = <&extal_clk>, <&usb_x1_clk>;
	84	clock-output-names = "pll", "i", "g";
cbe1f838	85	#power-domain-cells = <0>;
005980c0 UH	86	};
005980c0 UH	87
b6face40 WS	88	/* MSTP clocks */
	89	mstp3_clks: mstp3_clks@fcfe0420 {
	90	#clock-cells = <1>;
	91	compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
	92	reg = <0xfcfe0420 4>;
	93	clocks = <&p0_clk>;
	94	clock-indices = <R7S72100_CLK_MTU2>;
	95	clock-output-names = "mtu2";
	96	};
	97
	98	mstp4_clks: mstp4_clks@fcfe0424 {
	99	#clock-cells = <1>;
	100	compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
	101	reg = <0xfcfe0424 4>;
	102	clocks = <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>,
	103	<&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>;
	104	clock-indices = <
	105	R7S72100_CLK_SCIF0 R7S72100_CLK_SCIF1 R7S72100_CLK_SCIF2 R7S72100_CLK_SCIF3
	106	R7S72100_CLK_SCIF4 R7S72100_CLK_SCIF5 R7S72100_CLK_SCIF6 R7S72100_CLK_SCIF7
	107	>;
	108	clock-output-names = "scif0", "scif1", "scif2", "scif3", "scif4", "scif5", "scif6", "scif7";
	109	};
d165566b	110
969244f9 CB	111	mstp7_clks: mstp7_clks@fcfe0430 {
	112	#clock-cells = <1>;
	113	compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
	114	reg = <0xfcfe0430 4>;
	115	clocks = <&p0_clk>;
	116	clock-indices = <R7S72100_CLK_ETHER>;
	117	clock-output-names = "ether";
	118	};
	119
d165566b WS	120	mstp9_clks: mstp9_clks@fcfe0438 {
	121	#clock-cells = <1>;
	122	compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
	123	reg = <0xfcfe0438 4>;
	124	clocks = <&p0_clk>, <&p0_clk>, <&p0_clk>, <&p0_clk>;
	125	clock-indices = <
	126	R7S72100_CLK_I2C0 R7S72100_CLK_I2C1 R7S72100_CLK_I2C2 R7S72100_CLK_I2C3
	127	>;
	128	clock-output-names = "i2c0", "i2c1", "i2c2", "i2c3";
	129	};
52eed4f5 WS	130
	131	mstp10_clks: mstp10_clks@fcfe043c {
	132	#clock-cells = <1>;
	133	compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
	134	reg = <0xfcfe043c 4>;
	135	clocks = <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>,
	136	<&p1_clk>;
	137	clock-indices = <
	138	R7S72100_CLK_SPI0 R7S72100_CLK_SPI1 R7S72100_CLK_SPI2 R7S72100_CLK_SPI3
	139	R7S72100_CLK_SPI4
	140	>;
	141	clock-output-names = "spi0", "spi1", "spi2", "spi3", "spi4";
	142	};
b6face40 WS	143	};
b6face40 WS	144
e3da5b36 MD	145	cpus {
	146	#address-cells = <1>;
	147	#size-cells = <0>;
	148
	149	cpu@0 {
	150	device_type = "cpu";
	151	compatible = "arm,cortex-a9";
	152	reg = <0>;
005407fd	153	clock-frequency = <400000000>;
e3da5b36 MD	154	};
	155	};
	156
4c84c1b3 WS	157	scif0: serial@e8007000 {
	158	compatible = "renesas,scif-r7s72100", "renesas,scif";
	159	reg = <0xe8007000 64>;
16af4e97 SH	160	interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
	161	<GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
	162	<GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
	163	<GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
4c84c1b3	164	clocks = <&mstp4_clks R7S72100_CLK_SCIF0>;
92489120	165	clock-names = "fck";
cbe1f838	166	power-domains = <&cpg_clocks>;
4c84c1b3 WS	167	status = "disabled";
	168	};
	169
	170	scif1: serial@e8007800 {
	171	compatible = "renesas,scif-r7s72100", "renesas,scif";
	172	reg = <0xe8007800 64>;
16af4e97 SH	173	interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>,
	174	<GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>,
	175	<GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
	176	<GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
4c84c1b3	177	clocks = <&mstp4_clks R7S72100_CLK_SCIF1>;
92489120	178	clock-names = "fck";
cbe1f838	179	power-domains = <&cpg_clocks>;
4c84c1b3 WS	180	status = "disabled";
	181	};
	182
	183	scif2: serial@e8008000 {
	184	compatible = "renesas,scif-r7s72100", "renesas,scif";
	185	reg = <0xe8008000 64>;
16af4e97 SH	186	interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
	187	<GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
	188	<GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
	189	<GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
4c84c1b3	190	clocks = <&mstp4_clks R7S72100_CLK_SCIF2>;
92489120	191	clock-names = "fck";
cbe1f838	192	power-domains = <&cpg_clocks>;
4c84c1b3 WS	193	status = "disabled";
	194	};
	195
	196	scif3: serial@e8008800 {
	197	compatible = "renesas,scif-r7s72100", "renesas,scif";
	198	reg = <0xe8008800 64>;
16af4e97 SH	199	interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
	200	<GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
	201	<GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
	202	<GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
4c84c1b3	203	clocks = <&mstp4_clks R7S72100_CLK_SCIF3>;
92489120	204	clock-names = "fck";
cbe1f838	205	power-domains = <&cpg_clocks>;
4c84c1b3 WS	206	status = "disabled";
	207	};
	208
	209	scif4: serial@e8009000 {
	210	compatible = "renesas,scif-r7s72100", "renesas,scif";
	211	reg = <0xe8009000 64>;
16af4e97 SH	212	interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
	213	<GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
	214	<GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
	215	<GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
4c84c1b3	216	clocks = <&mstp4_clks R7S72100_CLK_SCIF4>;
92489120	217	clock-names = "fck";
cbe1f838	218	power-domains = <&cpg_clocks>;
4c84c1b3 WS	219	status = "disabled";
	220	};
	221
	222	scif5: serial@e8009800 {
	223	compatible = "renesas,scif-r7s72100", "renesas,scif";
	224	reg = <0xe8009800 64>;
16af4e97 SH	225	interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
	226	<GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
	227	<GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
	228	<GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
4c84c1b3	229	clocks = <&mstp4_clks R7S72100_CLK_SCIF5>;
92489120	230	clock-names = "fck";
cbe1f838	231	power-domains = <&cpg_clocks>;
4c84c1b3 WS	232	status = "disabled";
	233	};
	234
	235	scif6: serial@e800a000 {
	236	compatible = "renesas,scif-r7s72100", "renesas,scif";
	237	reg = <0xe800a000 64>;
16af4e97 SH	238	interrupts = <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
	239	<GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
	240	<GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
	241	<GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>;
4c84c1b3	242	clocks = <&mstp4_clks R7S72100_CLK_SCIF6>;
92489120	243	clock-names = "fck";
cbe1f838	244	power-domains = <&cpg_clocks>;
4c84c1b3 WS	245	status = "disabled";
	246	};
	247
	248	scif7: serial@e800a800 {
	249	compatible = "renesas,scif-r7s72100", "renesas,scif";
	250	reg = <0xe800a800 64>;
16af4e97 SH	251	interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
	252	<GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
	253	<GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
	254	<GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>;
4c84c1b3	255	clocks = <&mstp4_clks R7S72100_CLK_SCIF7>;
92489120	256	clock-names = "fck";
cbe1f838	257	power-domains = <&cpg_clocks>;
4c84c1b3 WS	258	status = "disabled";
	259	};
	260
4b18e83f GU	261	spi0: spi@e800c800 {
	262	compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
	263	reg = <0xe800c800 0x24>;
16af4e97 SH	264	interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
	265	<GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>,
	266	<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
4b18e83f	267	interrupt-names = "error", "rx", "tx";
52eed4f5	268	clocks = <&mstp10_clks R7S72100_CLK_SPI0>;
cbe1f838	269	power-domains = <&cpg_clocks>;
4b18e83f GU	270	num-cs = <1>;
	271	#address-cells = <1>;
	272	#size-cells = <0>;
	273	status = "disabled";
	274	};
	275
	276	spi1: spi@e800d000 {
	277	compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
	278	reg = <0xe800d000 0x24>;
16af4e97 SH	279	interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>,
	280	<GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
	281	<GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
4b18e83f	282	interrupt-names = "error", "rx", "tx";
52eed4f5	283	clocks = <&mstp10_clks R7S72100_CLK_SPI1>;
cbe1f838	284	power-domains = <&cpg_clocks>;
4b18e83f GU	285	num-cs = <1>;
	286	#address-cells = <1>;
	287	#size-cells = <0>;
	288	status = "disabled";
	289	};
	290
	291	spi2: spi@e800d800 {
	292	compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
	293	reg = <0xe800d800 0x24>;
16af4e97 SH	294	interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
	295	<GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
	296	<GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
4b18e83f	297	interrupt-names = "error", "rx", "tx";
52eed4f5	298	clocks = <&mstp10_clks R7S72100_CLK_SPI2>;
cbe1f838	299	power-domains = <&cpg_clocks>;
4b18e83f GU	300	num-cs = <1>;
	301	#address-cells = <1>;
	302	#size-cells = <0>;
	303	status = "disabled";
	304	};
	305
	306	spi3: spi@e800e000 {
	307	compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
	308	reg = <0xe800e000 0x24>;
16af4e97 SH	309	interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
	310	<GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
	311	<GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
4b18e83f	312	interrupt-names = "error", "rx", "tx";
52eed4f5	313	clocks = <&mstp10_clks R7S72100_CLK_SPI3>;
cbe1f838	314	power-domains = <&cpg_clocks>;
4b18e83f GU	315	num-cs = <1>;
	316	#address-cells = <1>;
	317	#size-cells = <0>;
	318	status = "disabled";
	319	};
	320
	321	spi4: spi@e800e800 {
	322	compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
	323	reg = <0xe800e800 0x24>;
16af4e97 SH	324	interrupts = <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
	325	<GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
	326	<GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>;
4b18e83f	327	interrupt-names = "error", "rx", "tx";
52eed4f5	328	clocks = <&mstp10_clks R7S72100_CLK_SPI4>;
cbe1f838	329	power-domains = <&cpg_clocks>;
4b18e83f GU	330	num-cs = <1>;
	331	#address-cells = <1>;
	332	#size-cells = <0>;
	333	status = "disabled";
	334	};
005980c0 UH	335
005980c0 UH	336	gic: interrupt-controller@e8201000 {
d9e1a0ef	337	compatible = "arm,pl390";
005980c0 UH	338	#interrupt-cells = <3>;
	339	#address-cells = <0>;
	340	interrupt-controller;
	341	reg = <0xe8201000 0x1000>,
	342	<0xe8202000 0x1000>;
	343	};
	344
	345	i2c0: i2c@fcfee000 {
	346	#address-cells = <1>;
	347	#size-cells = <0>;
	348	compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
	349	reg = <0xfcfee000 0x44>;
16af4e97 SH	350	interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
	351	<GIC_SPI 158 IRQ_TYPE_EDGE_RISING>,
	352	<GIC_SPI 159 IRQ_TYPE_EDGE_RISING>,
	353	<GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
	354	<GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
	355	<GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
	356	<GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
	357	<GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
005980c0 UH	358	clocks = <&mstp9_clks R7S72100_CLK_I2C0>;
005980c0 UH	359	clock-frequency = <100000>;
cbe1f838	360	power-domains = <&cpg_clocks>;
005980c0 UH	361	status = "disabled";
	362	};
	363
	364	i2c1: i2c@fcfee400 {
	365	#address-cells = <1>;
	366	#size-cells = <0>;
	367	compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
	368	reg = <0xfcfee400 0x44>;
16af4e97 SH	369	interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
	370	<GIC_SPI 166 IRQ_TYPE_EDGE_RISING>,
	371	<GIC_SPI 167 IRQ_TYPE_EDGE_RISING>,
	372	<GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
	373	<GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
	374	<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
	375	<GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
	376	<GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
005980c0 UH	377	clocks = <&mstp9_clks R7S72100_CLK_I2C1>;
005980c0 UH	378	clock-frequency = <100000>;
cbe1f838	379	power-domains = <&cpg_clocks>;
005980c0 UH	380	status = "disabled";
	381	};
	382
	383	i2c2: i2c@fcfee800 {
	384	#address-cells = <1>;
	385	#size-cells = <0>;
	386	compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
	387	reg = <0xfcfee800 0x44>;
16af4e97 SH	388	interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
	389	<GIC_SPI 174 IRQ_TYPE_EDGE_RISING>,
	390	<GIC_SPI 175 IRQ_TYPE_EDGE_RISING>,
	391	<GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
	392	<GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>,
	393	<GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,
	394	<GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>,
	395	<GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
005980c0 UH	396	clocks = <&mstp9_clks R7S72100_CLK_I2C2>;
005980c0 UH	397	clock-frequency = <100000>;
cbe1f838	398	power-domains = <&cpg_clocks>;
005980c0 UH	399	status = "disabled";
	400	};
	401
	402	i2c3: i2c@fcfeec00 {
	403	#address-cells = <1>;
	404	#size-cells = <0>;
	405	compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
	406	reg = <0xfcfeec00 0x44>;
16af4e97 SH	407	interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
	408	<GIC_SPI 182 IRQ_TYPE_EDGE_RISING>,
	409	<GIC_SPI 183 IRQ_TYPE_EDGE_RISING>,
	410	<GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
	411	<GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
	412	<GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
	413	<GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
	414	<GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
005980c0 UH	415	clocks = <&mstp9_clks R7S72100_CLK_I2C3>;
005980c0 UH	416	clock-frequency = <100000>;
cbe1f838	417	power-domains = <&cpg_clocks>;
005980c0 UH	418	status = "disabled";
	419	};
	420
	421	mtu2: timer@fcff0000 {
	422	compatible = "renesas,mtu2-r7s72100", "renesas,mtu2";
	423	reg = <0xfcff0000 0x400>;
16af4e97	424	interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
005980c0 UH	425	interrupt-names = "tgi0a";
	426	clocks = <&mstp3_clks R7S72100_CLK_MTU2>;
	427	clock-names = "fck";
cbe1f838	428	power-domains = <&cpg_clocks>;
005980c0 UH	429	status = "disabled";
005980c0 UH	430	};
e5482401 CB	431
	432	ether: ethernet@e8203000 {
	433	compatible = "renesas,ether-r7s72100";
	434	reg = <0xe8203000 0x800>,
	435	<0xe8204800 0x200>;
	436	interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;
	437	clocks = <&mstp7_clks R7S72100_CLK_ETHER>;
	438	power-domains = <&cpg_clocks>;
	439	phy-mode = "mii";
	440	#address-cells = <1>;
	441	#size-cells = <0>;
	442	status = "disabled";
	443	};
e3da5b36	444	};