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Merge remote-tracking branch 'spi/for-next'
[deliverable/linux.git] / arch / arm / boot / dts / r8a7794.dtsi
CommitLineData
0dce5454
UH		 1/*
2 * Device Tree Source for the r8a7794 SoC
3 *
4 * Copyright (C) 2014 Renesas Electronics Corporation
5 * Copyright (C) 2014 Ulrich Hecht
6 *
7 * This file is licensed under the terms of the GNU General Public License
8 * version 2. This program is licensed "as is" without any warranty of any
9 * kind, whether express or implied.
10 */
11
12#include <dt-bindings/clock/r8a7794-clock.h>
13#include <dt-bindings/interrupt-controller/arm-gic.h>
14#include <dt-bindings/interrupt-controller/irq.h>
0761ff2a 15#include <dt-bindings/power/r8a7794-sysc.h>
0dce5454
UH		 16
17/ {
18 compatible = "renesas,r8a7794";
19 interrupt-parent = <&gic>;
20 #address-cells = <2>;
21 #size-cells = <2>;
22
740b4a9f 23 aliases {
5428521b
SS		 24 i2c0 = &i2c0;
25 i2c1 = &i2c1;
26 i2c2 = &i2c2;
27 i2c3 = &i2c3;
28 i2c4 = &i2c4;
29 i2c5 = &i2c5;
aa9b992e
SH		 30 i2c6 = &i2c6;
31 i2c7 = &i2c7;
740b4a9f 32 spi0 = &qspi;
1afe77ca
SS		 33 vin0 = &vin0;
34 vin1 = &vin1;
740b4a9f
SS		 35 };
36
0dce5454
UH		 37 cpus {
38 #address-cells = <1>;
39 #size-cells = <0>;
40
41 cpu0: cpu@0 {
42 device_type = "cpu";
43 compatible = "arm,cortex-a7";
44 reg = <0>;
45 clock-frequency = <1000000000>;
0761ff2a 46 power-domains = <&sysc R8A7794_PD_CA7_CPU0>;
d12a384a 47 next-level-cache = <&L2_CA7>;
0dce5454
UH		 48 };
49
50 cpu1: cpu@1 {
51 device_type = "cpu";
52 compatible = "arm,cortex-a7";
53 reg = <1>;
54 clock-frequency = <1000000000>;
0761ff2a 55 power-domains = <&sysc R8A7794_PD_CA7_CPU1>;
d12a384a 56 next-level-cache = <&L2_CA7>;
0dce5454 57 };
0dce5454 58
34ea4b4a
GU		 59 L2_CA7: cache-controller@0 {
60 compatible = "cache";
61 reg = <0>;
62 power-domains = <&sysc R8A7794_PD_CA7_SCU>;
63 cache-unified;
64 cache-level = <2>;
65 };
d12a384a
GU		 66 };
67
0dce5454 68 gic: interrupt-controller@f1001000 {
c73ddf42 69 compatible = "arm,gic-400";
0dce5454
UH		 70 #interrupt-cells = <3>;
71 #address-cells = <0>;
72 interrupt-controller;
73 reg = <0 0xf1001000 0 0x1000>,
74 <0 0xf1002000 0 0x1000>,
75 <0 0xf1004000 0 0x2000>,
76 <0 0xf1006000 0 0x2000>;
8d47e6af 77 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
0dce5454
UH		 78 };
79
e8f5de3b
SS		 80 gpio0: gpio@e6050000 {
81 compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
82 reg = <0 0xe6050000 0 0x50>;
8d47e6af 83 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
e8f5de3b
SS		 84 #gpio-cells = <2>;
85 gpio-controller;
86 gpio-ranges = <&pfc 0 0 32>;
87 #interrupt-cells = <2>;
88 interrupt-controller;
89 clocks = <&mstp9_clks R8A7794_CLK_GPIO0>;
25611e4e 90 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
e8f5de3b
SS		 91 };
92
93 gpio1: gpio@e6051000 {
94 compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
95 reg = <0 0xe6051000 0 0x50>;
8d47e6af 96 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
e8f5de3b
SS		 97 #gpio-cells = <2>;
98 gpio-controller;
99 gpio-ranges = <&pfc 0 32 26>;
100 #interrupt-cells = <2>;
101 interrupt-controller;
102 clocks = <&mstp9_clks R8A7794_CLK_GPIO1>;
25611e4e 103 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
e8f5de3b
SS		 104 };
105
106 gpio2: gpio@e6052000 {
107 compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
108 reg = <0 0xe6052000 0 0x50>;
8d47e6af 109 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
e8f5de3b
SS		 110 #gpio-cells = <2>;
111 gpio-controller;
112 gpio-ranges = <&pfc 0 64 32>;
113 #interrupt-cells = <2>;
114 interrupt-controller;
115 clocks = <&mstp9_clks R8A7794_CLK_GPIO2>;
25611e4e 116 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
e8f5de3b
SS		 117 };
118
119 gpio3: gpio@e6053000 {
120 compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
121 reg = <0 0xe6053000 0 0x50>;
8d47e6af 122 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
e8f5de3b
SS		 123 #gpio-cells = <2>;
124 gpio-controller;
125 gpio-ranges = <&pfc 0 96 32>;
126 #interrupt-cells = <2>;
127 interrupt-controller;
128 clocks = <&mstp9_clks R8A7794_CLK_GPIO3>;
25611e4e 129 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
e8f5de3b
SS		 130 };
131
132 gpio4: gpio@e6054000 {
133 compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
134 reg = <0 0xe6054000 0 0x50>;
8d47e6af 135 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
e8f5de3b
SS		 136 #gpio-cells = <2>;
137 gpio-controller;
138 gpio-ranges = <&pfc 0 128 32>;
139 #interrupt-cells = <2>;
140 interrupt-controller;
141 clocks = <&mstp9_clks R8A7794_CLK_GPIO4>;
25611e4e 142 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
e8f5de3b
SS		 143 };
144
145 gpio5: gpio@e6055000 {
146 compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
147 reg = <0 0xe6055000 0 0x50>;
8d47e6af 148 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
e8f5de3b
SS		 149 #gpio-cells = <2>;
150 gpio-controller;
151 gpio-ranges = <&pfc 0 160 28>;
152 #interrupt-cells = <2>;
153 interrupt-controller;
154 clocks = <&mstp9_clks R8A7794_CLK_GPIO5>;
25611e4e 155 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
e8f5de3b
SS		 156 };
157
158 gpio6: gpio@e6055400 {
159 compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
160 reg = <0 0xe6055400 0 0x50>;
8d47e6af 161 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
e8f5de3b
SS		 162 #gpio-cells = <2>;
163 gpio-controller;
164 gpio-ranges = <&pfc 0 192 26>;
165 #interrupt-cells = <2>;
166 interrupt-controller;
167 clocks = <&mstp9_clks R8A7794_CLK_GPIO6>;
25611e4e 168 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
e8f5de3b
SS		 169 };
170
0dce5454
UH		 171 cmt0: timer@ffca0000 {
172 compatible = "renesas,cmt-48-gen2";
173 reg = <0 0xffca0000 0 0x1004>;
8d47e6af
SH		 174 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
175 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
0dce5454
UH		 176 clocks = <&mstp1_clks R8A7794_CLK_CMT0>;
177 clock-names = "fck";
25611e4e 178 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
0dce5454
UH		 179
180 renesas,channels-mask = <0x60>;
181
182 status = "disabled";
183 };
184
185 cmt1: timer@e6130000 {
186 compatible = "renesas,cmt-48-gen2";
187 reg = <0 0xe6130000 0 0x1004>;
8d47e6af
SH		 188 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
189 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
190 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
191 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
192 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
193 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
194 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
195 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
0dce5454
UH		 196 clocks = <&mstp3_clks R8A7794_CLK_CMT1>;
197 clock-names = "fck";
25611e4e 198 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
0dce5454
UH		 199
200 renesas,channels-mask = <0xff>;
201
202 status = "disabled";
203 };
204
da33648c
HN		 205 timer {
206 compatible = "arm,armv7-timer";
8d47e6af
SH		 207 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
208 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
209 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
210 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
da33648c
HN		 211 };
212
0dce5454
UH		 213 irqc0: interrupt-controller@e61c0000 {
214 compatible = "renesas,irqc-r8a7794", "renesas,irqc";
215 #interrupt-cells = <2>;
216 interrupt-controller;
217 reg = <0 0xe61c0000 0 0x200>;
8d47e6af
SH		 218 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
219 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
220 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
221 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
222 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
223 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
224 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
225 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
226 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
227 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1c5ca5db 228 clocks = <&mstp4_clks R8A7794_CLK_IRQC>;
25611e4e 229 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
0dce5454
UH		 230 };
231
fd1683c1
SS		 232 pfc: pin-controller@e6060000 {
233 compatible = "renesas,pfc-r8a7794";
234 reg = <0 0xe6060000 0 0x11c>;
fd1683c1
SS		 235 };
236
bd847485 237 dmac0: dma-controller@e6700000 {
0a3d058b 238 compatible = "renesas,dmac-r8a7794", "renesas,rcar-dmac";
bd847485 239 reg = <0 0xe6700000 0 0x20000>;
8d47e6af
SH		 240 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
241 GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
242 GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
243 GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
244 GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
245 GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
246 GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
247 GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
248 GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
249 GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
250 GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
251 GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
252 GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
253 GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
254 GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
255 GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
bd847485
LP		 256 interrupt-names = "error",
257 "ch0", "ch1", "ch2", "ch3",
258 "ch4", "ch5", "ch6", "ch7",
259 "ch8", "ch9", "ch10", "ch11",
260 "ch12", "ch13", "ch14";
261 clocks = <&mstp2_clks R8A7794_CLK_SYS_DMAC0>;
262 clock-names = "fck";
25611e4e 263 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
bd847485
LP		 264 #dma-cells = <1>;
265 dma-channels = <15>;
266 };
267
268 dmac1: dma-controller@e6720000 {
0a3d058b 269 compatible = "renesas,dmac-r8a7794", "renesas,rcar-dmac";
bd847485 270 reg = <0 0xe6720000 0 0x20000>;
8d47e6af
SH		 271 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
272 GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
273 GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
274 GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
275 GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
276 GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
277 GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
278 GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
279 GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
280 GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
281 GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
282 GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
283 GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
284 GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
285 GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
286 GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
bd847485
LP		 287 interrupt-names = "error",
288 "ch0", "ch1", "ch2", "ch3",
289 "ch4", "ch5", "ch6", "ch7",
290 "ch8", "ch9", "ch10", "ch11",
291 "ch12", "ch13", "ch14";
292 clocks = <&mstp2_clks R8A7794_CLK_SYS_DMAC1>;
293 clock-names = "fck";
25611e4e 294 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
bd847485
LP		 295 #dma-cells = <1>;
296 dma-channels = <15>;
297 };
298
298e4ee3
SS		 299 audma0: dma-controller@ec700000 {
300 compatible = "renesas,dmac-r8a7794", "renesas,rcar-dmac";
301 reg = <0 0xec700000 0 0x10000>;
302 interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH
303 GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
304 GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
305 GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
306 GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
307 GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
308 GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
309 GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
310 GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
311 GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
312 GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
313 GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
314 GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
315 GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
316 interrupt-names = "error",
317 "ch0", "ch1", "ch2", "ch3", "ch4", "ch5",
318 "ch6", "ch7", "ch8", "ch9", "ch10", "ch11",
319 "ch12";
320 clocks = <&mstp5_clks R8A7794_CLK_AUDIO_DMAC0>;
321 clock-names = "fck";
322 power-domains = <&cpg_clocks>;
323 #dma-cells = <1>;
324 dma-channels = <13>;
325 };
326
0dce5454 327 scifa0: serial@e6c40000 {
06930a1f
GU		 328 compatible = "renesas,scifa-r8a7794",
329 "renesas,rcar-gen2-scifa", "renesas,scifa";
0dce5454 330 reg = <0 0xe6c40000 0 64>;
8d47e6af 331 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
0dce5454 332 clocks = <&mstp2_clks R8A7794_CLK_SCIFA0>;
1b463bd5 333 clock-names = "fck";
b38605e9
NS		 334 dmas = <&dmac0 0x21>, <&dmac0 0x22>,
335 <&dmac1 0x21>, <&dmac1 0x22>;
336 dma-names = "tx", "rx", "tx", "rx";
25611e4e 337 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
0dce5454
UH		 338 status = "disabled";
339 };
340
341 scifa1: serial@e6c50000 {
06930a1f
GU		 342 compatible = "renesas,scifa-r8a7794",
343 "renesas,rcar-gen2-scifa", "renesas,scifa";
0dce5454 344 reg = <0 0xe6c50000 0 64>;
8d47e6af 345 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
0dce5454 346 clocks = <&mstp2_clks R8A7794_CLK_SCIFA1>;
1b463bd5 347 clock-names = "fck";
b38605e9
NS		 348 dmas = <&dmac0 0x25>, <&dmac0 0x26>,
349 <&dmac1 0x25>, <&dmac1 0x26>;
350 dma-names = "tx", "rx", "tx", "rx";
25611e4e 351 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
0dce5454
UH		 352 status = "disabled";
353 };
354
355 scifa2: serial@e6c60000 {
06930a1f
GU		 356 compatible = "renesas,scifa-r8a7794",
357 "renesas,rcar-gen2-scifa", "renesas,scifa";
0dce5454 358 reg = <0 0xe6c60000 0 64>;
8d47e6af 359 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
0dce5454 360 clocks = <&mstp2_clks R8A7794_CLK_SCIFA2>;
1b463bd5 361 clock-names = "fck";
b38605e9
NS		 362 dmas = <&dmac0 0x27>, <&dmac0 0x28>,
363 <&dmac1 0x27>, <&dmac1 0x28>;
364 dma-names = "tx", "rx", "tx", "rx";
25611e4e 365 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
0dce5454
UH		 366 status = "disabled";
367 };
368
369 scifa3: serial@e6c70000 {
06930a1f
GU		 370 compatible = "renesas,scifa-r8a7794",
371 "renesas,rcar-gen2-scifa", "renesas,scifa";
0dce5454 372 reg = <0 0xe6c70000 0 64>;
8d47e6af 373 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
0dce5454 374 clocks = <&mstp11_clks R8A7794_CLK_SCIFA3>;
1b463bd5 375 clock-names = "fck";
b38605e9
NS		 376 dmas = <&dmac0 0x1b>, <&dmac0 0x1c>,
377 <&dmac1 0x1b>, <&dmac1 0x1c>;
378 dma-names = "tx", "rx", "tx", "rx";
25611e4e 379 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
0dce5454
UH		 380 status = "disabled";
381 };
382
383 scifa4: serial@e6c78000 {
06930a1f
GU		 384 compatible = "renesas,scifa-r8a7794",
385 "renesas,rcar-gen2-scifa", "renesas,scifa";
0dce5454 386 reg = <0 0xe6c78000 0 64>;
8d47e6af 387 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
0dce5454 388 clocks = <&mstp11_clks R8A7794_CLK_SCIFA4>;
1b463bd5 389 clock-names = "fck";
b38605e9
NS		 390 dmas = <&dmac0 0x1f>, <&dmac0 0x20>,
391 <&dmac1 0x1f>, <&dmac1 0x20>;
392 dma-names = "tx", "rx", "tx", "rx";
25611e4e 393 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
0dce5454
UH		 394 status = "disabled";
395 };
396
397 scifa5: serial@e6c80000 {
06930a1f
GU		 398 compatible = "renesas,scifa-r8a7794",
399 "renesas,rcar-gen2-scifa", "renesas,scifa";
0dce5454 400 reg = <0 0xe6c80000 0 64>;
8d47e6af 401 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
0dce5454 402 clocks = <&mstp11_clks R8A7794_CLK_SCIFA5>;
1b463bd5 403 clock-names = "fck";
b38605e9
NS		 404 dmas = <&dmac0 0x23>, <&dmac0 0x24>,
405 <&dmac1 0x23>, <&dmac1 0x24>;
406 dma-names = "tx", "rx", "tx", "rx";
25611e4e 407 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
0dce5454
UH		 408 status = "disabled";
409 };
410
411 scifb0: serial@e6c20000 {
06930a1f
GU		 412 compatible = "renesas,scifb-r8a7794",
413 "renesas,rcar-gen2-scifb", "renesas,scifb";
0dce5454 414 reg = <0 0xe6c20000 0 64>;
8d47e6af 415 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
0dce5454 416 clocks = <&mstp2_clks R8A7794_CLK_SCIFB0>;
1b463bd5 417 clock-names = "fck";
b38605e9
NS		 418 dmas = <&dmac0 0x3d>, <&dmac0 0x3e>,
419 <&dmac1 0x3d>, <&dmac1 0x3e>;
420 dma-names = "tx", "rx", "tx", "rx";
25611e4e 421 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
0dce5454
UH		 422 status = "disabled";
423 };
424
425 scifb1: serial@e6c30000 {
06930a1f
GU		 426 compatible = "renesas,scifb-r8a7794",
427 "renesas,rcar-gen2-scifb", "renesas,scifb";
0dce5454 428 reg = <0 0xe6c30000 0 64>;
8d47e6af 429 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
0dce5454 430 clocks = <&mstp2_clks R8A7794_CLK_SCIFB1>;
1b463bd5 431 clock-names = "fck";
b38605e9
NS		 432 dmas = <&dmac0 0x19>, <&dmac0 0x1a>,
433 <&dmac1 0x19>, <&dmac1 0x1a>;
434 dma-names = "tx", "rx", "tx", "rx";
25611e4e 435 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
0dce5454
UH		 436 status = "disabled";
437 };
438
439 scifb2: serial@e6ce0000 {
06930a1f
GU		 440 compatible = "renesas,scifb-r8a7794",
441 "renesas,rcar-gen2-scifb", "renesas,scifb";
0dce5454 442 reg = <0 0xe6ce0000 0 64>;
8d47e6af 443 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
0dce5454 444 clocks = <&mstp2_clks R8A7794_CLK_SCIFB2>;
1b463bd5 445 clock-names = "fck";
b38605e9
NS		 446 dmas = <&dmac0 0x1d>, <&dmac0 0x1e>,
447 <&dmac1 0x1d>, <&dmac1 0x1e>;
448 dma-names = "tx", "rx", "tx", "rx";
25611e4e 449 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
0dce5454
UH		 450 status = "disabled";
451 };
452
453 scif0: serial@e6e60000 {
06930a1f
GU		 454 compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif",
455 "renesas,scif";
0dce5454 456 reg = <0 0xe6e60000 0 64>;
8d47e6af 457 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
a864446f
GU		 458 clocks = <&mstp7_clks R8A7794_CLK_SCIF0>, <&zs_clk>,
459 <&scif_clk>;
460 clock-names = "fck", "brg_int", "scif_clk";
b38605e9
NS		 461 dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
462 <&dmac1 0x29>, <&dmac1 0x2a>;
463 dma-names = "tx", "rx", "tx", "rx";
25611e4e 464 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
0dce5454
UH		 465 status = "disabled";
466 };
467
468 scif1: serial@e6e68000 {
06930a1f
GU		 469 compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif",
470 "renesas,scif";
0dce5454 471 reg = <0 0xe6e68000 0 64>;
8d47e6af 472 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
a864446f
GU		 473 clocks = <&mstp7_clks R8A7794_CLK_SCIF1>, <&zs_clk>,
474 <&scif_clk>;
475 clock-names = "fck", "brg_int", "scif_clk";
b38605e9
NS		 476 dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
477 <&dmac1 0x2d>, <&dmac1 0x2e>;
478 dma-names = "tx", "rx", "tx", "rx";
25611e4e 479 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
0dce5454
UH		 480 status = "disabled";
481 };
482
483 scif2: serial@e6e58000 {
06930a1f
GU		 484 compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif",
485 "renesas,scif";
0dce5454 486 reg = <0 0xe6e58000 0 64>;
8d47e6af 487 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
a864446f
GU		 488 clocks = <&mstp7_clks R8A7794_CLK_SCIF2>, <&zs_clk>,
489 <&scif_clk>;
490 clock-names = "fck", "brg_int", "scif_clk";
b38605e9
NS		 491 dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
492 <&dmac1 0x2b>, <&dmac1 0x2c>;
493 dma-names = "tx", "rx", "tx", "rx";
25611e4e 494 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
0dce5454
UH		 495 status = "disabled";
496 };
497
498 scif3: serial@e6ea8000 {
06930a1f
GU		 499 compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif",
500 "renesas,scif";
0dce5454 501 reg = <0 0xe6ea8000 0 64>;
8d47e6af 502 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
a864446f
GU		 503 clocks = <&mstp7_clks R8A7794_CLK_SCIF3>, <&zs_clk>,
504 <&scif_clk>;
505 clock-names = "fck", "brg_int", "scif_clk";
b38605e9
NS		 506 dmas = <&dmac0 0x2f>, <&dmac0 0x30>,
507 <&dmac1 0x2f>, <&dmac1 0x30>;
508 dma-names = "tx", "rx", "tx", "rx";
25611e4e 509 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
0dce5454
UH		 510 status = "disabled";
511 };
512
513 scif4: serial@e6ee0000 {
06930a1f
GU		 514 compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif",
515 "renesas,scif";
0dce5454 516 reg = <0 0xe6ee0000 0 64>;
8d47e6af 517 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
a864446f
GU		 518 clocks = <&mstp7_clks R8A7794_CLK_SCIF4>, <&zs_clk>,
519 <&scif_clk>;
520 clock-names = "fck", "brg_int", "scif_clk";
b38605e9
NS		 521 dmas = <&dmac0 0xfb>, <&dmac0 0xfc>,
522 <&dmac1 0xfb>, <&dmac1 0xfc>;
523 dma-names = "tx", "rx", "tx", "rx";
25611e4e 524 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
0dce5454
UH		 525 status = "disabled";
526 };
527
528 scif5: serial@e6ee8000 {
06930a1f
GU		 529 compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif",
530 "renesas,scif";
0dce5454 531 reg = <0 0xe6ee8000 0 64>;
8d47e6af 532 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
a864446f
GU		 533 clocks = <&mstp7_clks R8A7794_CLK_SCIF5>, <&zs_clk>,
534 <&scif_clk>;
535 clock-names = "fck", "brg_int", "scif_clk";
b38605e9
NS		 536 dmas = <&dmac0 0xfd>, <&dmac0 0xfe>,
537 <&dmac1 0xfd>, <&dmac1 0xfe>;
538 dma-names = "tx", "rx", "tx", "rx";
25611e4e 539 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
0dce5454
UH		 540 status = "disabled";
541 };
542
543 hscif0: serial@e62c0000 {
06930a1f
GU		 544 compatible = "renesas,hscif-r8a7794",
545 "renesas,rcar-gen2-hscif", "renesas,hscif";
0dce5454 546 reg = <0 0xe62c0000 0 96>;
8d47e6af 547 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
a864446f
GU		 548 clocks = <&mstp7_clks R8A7794_CLK_HSCIF0>, <&zs_clk>,
549 <&scif_clk>;
550 clock-names = "fck", "brg_int", "scif_clk";
b38605e9
NS		 551 dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
552 <&dmac1 0x39>, <&dmac1 0x3a>;
553 dma-names = "tx", "rx", "tx", "rx";
25611e4e 554 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
0dce5454
UH		 555 status = "disabled";
556 };
557
558 hscif1: serial@e62c8000 {
06930a1f
GU		 559 compatible = "renesas,hscif-r8a7794",
560 "renesas,rcar-gen2-hscif", "renesas,hscif";
0dce5454 561 reg = <0 0xe62c8000 0 96>;
8d47e6af 562 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
a864446f
GU		 563 clocks = <&mstp7_clks R8A7794_CLK_HSCIF1>, <&zs_clk>,
564 <&scif_clk>;
565 clock-names = "fck", "brg_int", "scif_clk";
b38605e9
NS		 566 dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
567 <&dmac1 0x4d>, <&dmac1 0x4e>;
568 dma-names = "tx", "rx", "tx", "rx";
25611e4e 569 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
0dce5454
UH		 570 status = "disabled";
571 };
572
573 hscif2: serial@e62d0000 {
06930a1f
GU		 574 compatible = "renesas,hscif-r8a7794",
575 "renesas,rcar-gen2-hscif", "renesas,hscif";
0dce5454 576 reg = <0 0xe62d0000 0 96>;
8d47e6af 577 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
a864446f
GU		 578 clocks = <&mstp7_clks R8A7794_CLK_HSCIF2>, <&zs_clk>,
579 <&scif_clk>;
580 clock-names = "fck", "brg_int", "scif_clk";
b38605e9
NS		 581 dmas = <&dmac0 0x3b>, <&dmac0 0x3c>,
582 <&dmac1 0x3b>, <&dmac1 0x3c>;
583 dma-names = "tx", "rx", "tx", "rx";
25611e4e 584 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
0dce5454
UH		 585 status = "disabled";
586 };
587
82818d34
LP		 588 ether: ethernet@ee700000 {
589 compatible = "renesas,ether-r8a7794";
590 reg = <0 0xee700000 0 0x400>;
8d47e6af 591 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
82818d34 592 clocks = <&mstp8_clks R8A7794_CLK_ETHER>;
25611e4e 593 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
82818d34
LP		 594 phy-mode = "rmii";
595 #address-cells = <1>;
596 #size-cells = <0>;
597 status = "disabled";
598 };
599
89aac8af
SS		 600 avb: ethernet@e6800000 {
601 compatible = "renesas,etheravb-r8a7794",
602 "renesas,etheravb-rcar-gen2";
603 reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
604 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
605 clocks = <&mstp8_clks R8A7794_CLK_ETHERAVB>;
25611e4e 606 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
89aac8af
SS		 607 #address-cells = <1>;
608 #size-cells = <0>;
609 status = "disabled";
610 };
611
5428521b
SS		 612 /* The memory map in the User's Manual maps the cores to bus numbers */
613 i2c0: i2c@e6508000 {
614 compatible = "renesas,i2c-r8a7794";
615 reg = <0 0xe6508000 0 0x40>;
8d47e6af 616 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
5428521b 617 clocks = <&mstp9_clks R8A7794_CLK_I2C0>;
25611e4e 618 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
5428521b
SS		 619 #address-cells = <1>;
620 #size-cells = <0>;
691cd0a6 621 i2c-scl-internal-delay-ns = <6>;
5428521b
SS		 622 status = "disabled";
623 };
624
625 i2c1: i2c@e6518000 {
626 compatible = "renesas,i2c-r8a7794";
627 reg = <0 0xe6518000 0 0x40>;
8d47e6af 628 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
5428521b 629 clocks = <&mstp9_clks R8A7794_CLK_I2C1>;
25611e4e 630 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
5428521b
SS		 631 #address-cells = <1>;
632 #size-cells = <0>;
691cd0a6 633 i2c-scl-internal-delay-ns = <6>;
5428521b
SS		 634 status = "disabled";
635 };
636
637 i2c2: i2c@e6530000 {
638 compatible = "renesas,i2c-r8a7794";
639 reg = <0 0xe6530000 0 0x40>;
8d47e6af 640 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
5428521b 641 clocks = <&mstp9_clks R8A7794_CLK_I2C2>;
25611e4e 642 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
5428521b
SS		 643 #address-cells = <1>;
644 #size-cells = <0>;
691cd0a6 645 i2c-scl-internal-delay-ns = <6>;
5428521b
SS		 646 status = "disabled";
647 };
648
649 i2c3: i2c@e6540000 {
650 compatible = "renesas,i2c-r8a7794";
651 reg = <0 0xe6540000 0 0x40>;
8d47e6af 652 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
5428521b 653 clocks = <&mstp9_clks R8A7794_CLK_I2C3>;
25611e4e 654 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
5428521b
SS		 655 #address-cells = <1>;
656 #size-cells = <0>;
691cd0a6 657 i2c-scl-internal-delay-ns = <6>;
5428521b
SS		 658 status = "disabled";
659 };
660
661 i2c4: i2c@e6520000 {
662 compatible = "renesas,i2c-r8a7794";
663 reg = <0 0xe6520000 0 0x40>;
8d47e6af 664 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
5428521b 665 clocks = <&mstp9_clks R8A7794_CLK_I2C4>;
25611e4e 666 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
5428521b
SS		 667 #address-cells = <1>;
668 #size-cells = <0>;
691cd0a6 669 i2c-scl-internal-delay-ns = <6>;
5428521b
SS		 670 status = "disabled";
671 };
672
673 i2c5: i2c@e6528000 {
674 compatible = "renesas,i2c-r8a7794";
675 reg = <0 0xe6528000 0 0x40>;
8d47e6af 676 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
5428521b 677 clocks = <&mstp9_clks R8A7794_CLK_I2C5>;
25611e4e 678 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
5428521b
SS		 679 #address-cells = <1>;
680 #size-cells = <0>;
691cd0a6 681 i2c-scl-internal-delay-ns = <6>;
5428521b
SS		 682 status = "disabled";
683 };
684
aa9b992e
SH		 685 i2c6: i2c@e6500000 {
686 compatible = "renesas,iic-r8a7794", "renesas,rmobile-iic";
687 reg = <0 0xe6500000 0 0x425>;
688 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
689 clocks = <&mstp3_clks R8A7794_CLK_IIC0>;
b38605e9
NS		 690 dmas = <&dmac0 0x61>, <&dmac0 0x62>,
691 <&dmac1 0x61>, <&dmac1 0x62>;
692 dma-names = "tx", "rx", "tx", "rx";
25611e4e 693 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
aa9b992e
SH		 694 #address-cells = <1>;
695 #size-cells = <0>;
696 status = "disabled";
697 };
698
699 i2c7: i2c@e6510000 {
700 compatible = "renesas,iic-r8a7794", "renesas,rmobile-iic";
701 reg = <0 0xe6510000 0 0x425>;
702 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
703 clocks = <&mstp3_clks R8A7794_CLK_IIC1>;
b38605e9
NS		 704 dmas = <&dmac0 0x65>, <&dmac0 0x66>,
705 <&dmac1 0x65>, <&dmac1 0x66>;
706 dma-names = "tx", "rx", "tx", "rx";
25611e4e 707 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
aa9b992e
SH		 708 #address-cells = <1>;
709 #size-cells = <0>;
710 status = "disabled";
711 };
712
6cdf6ba1
SS		 713 mmcif0: mmc@ee200000 {
714 compatible = "renesas,mmcif-r8a7794", "renesas,sh-mmcif";
715 reg = <0 0xee200000 0 0x80>;
8d47e6af 716 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
6cdf6ba1 717 clocks = <&mstp3_clks R8A7794_CLK_MMCIF0>;
b38605e9
NS		 718 dmas = <&dmac0 0xd1>, <&dmac0 0xd2>,
719 <&dmac1 0xd1>, <&dmac1 0xd2>;
720 dma-names = "tx", "rx", "tx", "rx";
25611e4e 721 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
6cdf6ba1
SS		 722 reg-io-width = <4>;
723 status = "disabled";
724 };
725
b8e8ea12
SS		 726 sdhi0: sd@ee100000 {
727 compatible = "renesas,sdhi-r8a7794";
83701e00 728 reg = <0 0xee100000 0 0x328>;
8d47e6af 729 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
b8e8ea12 730 clocks = <&mstp3_clks R8A7794_CLK_SDHI0>;
b38605e9
NS		 731 dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
732 <&dmac1 0xcd>, <&dmac1 0xce>;
733 dma-names = "tx", "rx", "tx", "rx";
25611e4e 734 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
b8e8ea12
SS		 735 status = "disabled";
736 };
737
738 sdhi1: sd@ee140000 {
739 compatible = "renesas,sdhi-r8a7794";
740 reg = <0 0xee140000 0 0x100>;
8d47e6af 741 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
b8e8ea12 742 clocks = <&mstp3_clks R8A7794_CLK_SDHI1>;
b38605e9
NS		 743 dmas = <&dmac0 0xc1>, <&dmac0 0xc2>,
744 <&dmac1 0xc1>, <&dmac1 0xc2>;
745 dma-names = "tx", "rx", "tx", "rx";
25611e4e 746 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
b8e8ea12
SS		 747 status = "disabled";
748 };
749
750 sdhi2: sd@ee160000 {
751 compatible = "renesas,sdhi-r8a7794";
752 reg = <0 0xee160000 0 0x100>;
8d47e6af 753 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
b8e8ea12 754 clocks = <&mstp3_clks R8A7794_CLK_SDHI2>;
b38605e9
NS		 755 dmas = <&dmac0 0xd3>, <&dmac0 0xd4>,
756 <&dmac1 0xd3>, <&dmac1 0xd4>;
757 dma-names = "tx", "rx", "tx", "rx";
25611e4e 758 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
b8e8ea12
SS		 759 status = "disabled";
760 };
761
740b4a9f
SS		 762 qspi: spi@e6b10000 {
763 compatible = "renesas,qspi-r8a7794", "renesas,qspi";
764 reg = <0 0xe6b10000 0 0x2c>;
8d47e6af 765 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
740b4a9f 766 clocks = <&mstp9_clks R8A7794_CLK_QSPI_MOD>;
b38605e9
NS		 767 dmas = <&dmac0 0x17>, <&dmac0 0x18>,
768 <&dmac1 0x17>, <&dmac1 0x18>;
769 dma-names = "tx", "rx", "tx", "rx";
25611e4e 770 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
740b4a9f
SS		 771 num-cs = <1>;
772 #address-cells = <1>;
773 #size-cells = <0>;
774 status = "disabled";
775 };
776
1afe77ca
SS		 777 vin0: video@e6ef0000 {
778 compatible = "renesas,vin-r8a7794";
779 reg = <0 0xe6ef0000 0 0x1000>;
8d47e6af 780 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
1afe77ca 781 clocks = <&mstp8_clks R8A7794_CLK_VIN0>;
25611e4e 782 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
1afe77ca
SS		 783 status = "disabled";
784 };
785
786 vin1: video@e6ef1000 {
787 compatible = "renesas,vin-r8a7794";
788 reg = <0 0xe6ef1000 0 0x1000>;
8d47e6af 789 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
1afe77ca 790 clocks = <&mstp8_clks R8A7794_CLK_VIN1>;
25611e4e 791 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
1afe77ca
SS		 792 status = "disabled";
793 };
794
a6a130b3 795 pci0: pci@ee090000 {
c99fbe64 796 compatible = "renesas,pci-r8a7794", "renesas,pci-rcar-gen2";
a6a130b3
SS		 797 device_type = "pci";
798 reg = <0 0xee090000 0 0xc00>,
799 <0 0xee080000 0 0x1100>;
8d47e6af 800 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
a6a130b3 801 clocks = <&mstp7_clks R8A7794_CLK_EHCI>;
25611e4e 802 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
a6a130b3
SS		 803 status = "disabled";
804
805 bus-range = <0 0>;
806 #address-cells = <3>;
807 #size-cells = <2>;
808 #interrupt-cells = <1>;
809 ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;
810 interrupt-map-mask = <0xff00 0 0 0x7>;
8d47e6af
SH		 811 interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
812 0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
813 0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
45cb0bd7
SS		 814
815 usb@0,1 {
816 reg = <0x800 0 0 0 0>;
817 device_type = "pci";
818 phys = <&usb0 0>;
819 phy-names = "usb";
820 };
821
822 usb@0,2 {
823 reg = <0x1000 0 0 0 0>;
824 device_type = "pci";
825 phys = <&usb0 0>;
826 phy-names = "usb";
827 };
a6a130b3
SS		 828 };
829
830 pci1: pci@ee0d0000 {
c99fbe64 831 compatible = "renesas,pci-r8a7794", "renesas,pci-rcar-gen2";
a6a130b3
SS		 832 device_type = "pci";
833 reg = <0 0xee0d0000 0 0xc00>,
834 <0 0xee0c0000 0 0x1100>;
8d47e6af 835 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
a6a130b3 836 clocks = <&mstp7_clks R8A7794_CLK_EHCI>;
25611e4e 837 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
a6a130b3
SS		 838 status = "disabled";
839
840 bus-range = <1 1>;
841 #address-cells = <3>;
842 #size-cells = <2>;
843 #interrupt-cells = <1>;
844 ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;
845 interrupt-map-mask = <0xff00 0 0 0x7>;
8d47e6af
SH		 846 interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
847 0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
848 0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
45cb0bd7
SS		 849
850 usb@0,1 {
851 reg = <0x800 0 0 0 0>;
852 device_type = "pci";
853 phys = <&usb2 0>;
854 phy-names = "usb";
855 };
856
857 usb@0,2 {
858 reg = <0x1000 0 0 0 0>;
859 device_type = "pci";
860 phys = <&usb2 0>;
861 phy-names = "usb";
862 };
a6a130b3
SS		 863 };
864
2f33b9f7 865 hsusb: usb@e6590000 {
1472ffa8 866 compatible = "renesas,usbhs-r8a7794", "renesas,rcar-gen2-usbhs";
2f33b9f7 867 reg = <0 0xe6590000 0 0x100>;
8d47e6af 868 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
2f33b9f7 869 clocks = <&mstp7_clks R8A7794_CLK_HSUSB>;
25611e4e 870 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
2f33b9f7
SS		 871 renesas,buswait = <4>;
872 phys = <&usb0 1>;
873 phy-names = "usb";
874 status = "disabled";
875 };
876
74ef4572
SS		 877 usbphy: usb-phy@e6590100 {
878 compatible = "renesas,usb-phy-r8a7794";
879 reg = <0 0xe6590100 0 0x100>;
880 #address-cells = <1>;
881 #size-cells = <0>;
882 clocks = <&mstp7_clks R8A7794_CLK_HSUSB>;
883 clock-names = "usbhs";
25611e4e 884 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
74ef4572
SS		 885 status = "disabled";
886
887 usb0: usb-channel@0 {
888 reg = <0>;
889 #phy-cells = <1>;
890 };
891 usb2: usb-channel@2 {
892 reg = <2>;
893 #phy-cells = <1>;
894 };
895 };
896
bb249cdc
SS		 897 vsp1@fe928000 {
898 compatible = "renesas,vsp1";
899 reg = <0 0xfe928000 0 0x8000>;
900 interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
901 clocks = <&mstp1_clks R8A7794_CLK_VSP1_S>;
902 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
903 };
904
905 vsp1@fe930000 {
906 compatible = "renesas,vsp1";
907 reg = <0 0xfe930000 0 0x8000>;
908 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
909 clocks = <&mstp1_clks R8A7794_CLK_VSP1_DU0>;
910 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
911 };
912
46c4f13d
LP		 913 du: display@feb00000 {
914 compatible = "renesas,du-r8a7794";
915 reg = <0 0xfeb00000 0 0x40000>;
916 reg-names = "du";
8d47e6af
SH		 917 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
918 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
46c4f13d
LP		 919 clocks = <&mstp7_clks R8A7794_CLK_DU0>,
920 <&mstp7_clks R8A7794_CLK_DU0>;
921 clock-names = "du.0", "du.1";
922 status = "disabled";
923
924 ports {
925 #address-cells = <1>;
926 #size-cells = <0>;
927
928 port@0 {
929 reg = <0>;
930 du_out_rgb0: endpoint {
931 };
932 };
933 port@1 {
934 reg = <1>;
935 du_out_rgb1: endpoint {
936 };
937 };
938 };
939 };
940
9f1c1a2c
SH		 941 can0: can@e6e80000 {
942 compatible = "renesas,can-r8a7794", "renesas,rcar-gen2-can";
943 reg = <0 0xe6e80000 0 0x1000>;
944 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
945 clocks = <&mstp9_clks R8A7794_CLK_RCAN0>,
946 <&cpg_clocks R8A7794_CLK_RCAN>, <&can_clk>;
947 clock-names = "clkp1", "clkp2", "can_clk";
25611e4e 948 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
9f1c1a2c
SH		 949 status = "disabled";
950 };
951
952 can1: can@e6e88000 {
953 compatible = "renesas,can-r8a7794", "renesas,rcar-gen2-can";
954 reg = <0 0xe6e88000 0 0x1000>;
955 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
956 clocks = <&mstp9_clks R8A7794_CLK_RCAN1>,
957 <&cpg_clocks R8A7794_CLK_RCAN>, <&can_clk>;
958 clock-names = "clkp1", "clkp2", "can_clk";
25611e4e 959 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
9f1c1a2c
SH		 960 status = "disabled";
961 };
962
0dce5454
UH		 963 clocks {
964 #address-cells = <2>;
965 #size-cells = <2>;
966 ranges;
967
968 /* External root clock */
337f6bef 969 extal_clk: extal {
0dce5454
UH		 970 compatible = "fixed-clock";
971 #clock-cells = <0>;
972 /* This value must be overriden by the board. */
973 clock-frequency = <0>;
0dce5454
UH		 974 };
975
e980f941
SH		 976 /* External USB clock - can be overridden by the board */
977 usb_extal_clk: usb_extal {
978 compatible = "fixed-clock";
979 #clock-cells = <0>;
980 clock-frequency = <48000000>;
981 };
982
983 /* External CAN clock */
984 can_clk: can {
985 compatible = "fixed-clock";
986 #clock-cells = <0>;
987 /* This value must be overridden by the board. */
988 clock-frequency = <0>;
e980f941
SH		 989 };
990
a864446f
GU		 991 /* External SCIF clock */
992 scif_clk: scif {
993 compatible = "fixed-clock";
994 #clock-cells = <0>;
995 /* This value must be overridden by the board. */
996 clock-frequency = <0>;
a864446f
GU		 997 };
998
0b1f0e37
SS		 999 /*
1000 * The external audio clocks are configured as 0 Hz fixed
1001 * frequency clocks by default. Boards that provide audio
1002 * clocks should override them.
1003 */
1004 audio_clka: audio_clka {
1005 compatible = "fixed-clock";
1006 #clock-cells = <0>;
1007 clock-frequency = <0>;
1008 };
1009 audio_clkb: audio_clkb {
1010 compatible = "fixed-clock";
1011 #clock-cells = <0>;
1012 clock-frequency = <0>;
1013 };
1014 audio_clkc: audio_clkc {
1015 compatible = "fixed-clock";
1016 #clock-cells = <0>;
1017 clock-frequency = <0>;
1018 };
1019
0dce5454
UH		 1020 /* Special CPG clocks */
1021 cpg_clocks: cpg_clocks@e6150000 {
1022 compatible = "renesas,r8a7794-cpg-clocks",
1023 "renesas,rcar-gen2-cpg-clocks";
1024 reg = <0 0xe6150000 0 0x1000>;
e980f941 1025 clocks = <&extal_clk &usb_extal_clk>;
0dce5454
UH		 1026 #clock-cells = <1>;
1027 clock-output-names = "main", "pll0", "pll1", "pll3",
e980f941
SH		 1028 "lb", "qspi", "sdh", "sd0", "z",
1029 "rcan";
60c0745a 1030 #power-domain-cells = <0>;
0dce5454 1031 };
8e181633 1032 /* Variable factor clocks */
337f6bef 1033 sd2_clk: sd2@e6150078 {
8e181633
SU		 1034 compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock";
1035 reg = <0 0xe6150078 0 4>;
1036 clocks = <&pll1_div2_clk>;
1037 #clock-cells = <0>;
8e181633 1038 };
337f6bef 1039 sd3_clk: sd3@e615026c {
8e181633 1040 compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock";
5e7e1554 1041 reg = <0 0xe615026c 0 4>;
8e181633
SU		 1042 clocks = <&pll1_div2_clk>;
1043 #clock-cells = <0>;
8e181633 1044 };
337f6bef 1045 mmc0_clk: mmc0@e6150240 {
deac150c
SU		 1046 compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock";
1047 reg = <0 0xe6150240 0 4>;
1048 clocks = <&pll1_div2_clk>;
1049 #clock-cells = <0>;
deac150c 1050 };
0dce5454
UH		 1051
1052 /* Fixed factor clocks */
337f6bef 1053 pll1_div2_clk: pll1_div2 {
0dce5454
UH		 1054 compatible = "fixed-factor-clock";
1055 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
1056 #clock-cells = <0>;
1057 clock-div = <2>;
1058 clock-mult = <1>;
0dce5454 1059 };
337f6bef 1060 zg_clk: zg {
0dce5454
UH		 1061 compatible = "fixed-factor-clock";
1062 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
1063 #clock-cells = <0>;
1064 clock-div = <6>;
1065 clock-mult = <1>;
0dce5454 1066 };
337f6bef 1067 zx_clk: zx {
0dce5454
UH		 1068 compatible = "fixed-factor-clock";
1069 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
1070 #clock-cells = <0>;
1071 clock-div = <3>;
1072 clock-mult = <1>;
0dce5454 1073 };
337f6bef 1074 zs_clk: zs {
0dce5454
UH		 1075 compatible = "fixed-factor-clock";
1076 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
1077 #clock-cells = <0>;
1078 clock-div = <6>;
1079 clock-mult = <1>;
0dce5454 1080 };
337f6bef 1081 hp_clk: hp {
0dce5454
UH		 1082 compatible = "fixed-factor-clock";
1083 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
1084 #clock-cells = <0>;
1085 clock-div = <12>;
1086 clock-mult = <1>;
0dce5454 1087 };
337f6bef 1088 i_clk: i {
0dce5454
UH		 1089 compatible = "fixed-factor-clock";
1090 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
1091 #clock-cells = <0>;
1092 clock-div = <2>;
1093 clock-mult = <1>;
0dce5454 1094 };
337f6bef 1095 b_clk: b {
0dce5454
UH		 1096 compatible = "fixed-factor-clock";
1097 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
1098 #clock-cells = <0>;
1099 clock-div = <12>;
1100 clock-mult = <1>;
0dce5454 1101 };
337f6bef 1102 p_clk: p {
0dce5454
UH		 1103 compatible = "fixed-factor-clock";
1104 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
1105 #clock-cells = <0>;
1106 clock-div = <24>;
1107 clock-mult = <1>;
0dce5454 1108 };
337f6bef 1109 cl_clk: cl {
0dce5454
UH		 1110 compatible = "fixed-factor-clock";
1111 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
1112 #clock-cells = <0>;
1113 clock-div = <48>;
1114 clock-mult = <1>;
0dce5454 1115 };
337f6bef 1116 m2_clk: m2 {
0dce5454
UH		 1117 compatible = "fixed-factor-clock";
1118 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
1119 #clock-cells = <0>;
1120 clock-div = <8>;
1121 clock-mult = <1>;
0dce5454 1122 };
337f6bef 1123 rclk_clk: rclk {
0dce5454
UH		 1124 compatible = "fixed-factor-clock";
1125 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
1126 #clock-cells = <0>;
1127 clock-div = <(48 * 1024)>;
1128 clock-mult = <1>;
0dce5454 1129 };
337f6bef 1130 oscclk_clk: oscclk {
0dce5454
UH		 1131 compatible = "fixed-factor-clock";
1132 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
1133 #clock-cells = <0>;
1134 clock-div = <(12 * 1024)>;
1135 clock-mult = <1>;
0dce5454 1136 };
337f6bef 1137 zb3_clk: zb3 {
0dce5454
UH		 1138 compatible = "fixed-factor-clock";
1139 clocks = <&cpg_clocks R8A7794_CLK_PLL3>;
1140 #clock-cells = <0>;
1141 clock-div = <4>;
1142 clock-mult = <1>;
0dce5454 1143 };
337f6bef 1144 zb3d2_clk: zb3d2 {
0dce5454
UH		 1145 compatible = "fixed-factor-clock";
1146 clocks = <&cpg_clocks R8A7794_CLK_PLL3>;
1147 #clock-cells = <0>;
1148 clock-div = <8>;
1149 clock-mult = <1>;
0dce5454 1150 };
337f6bef 1151 ddr_clk: ddr {
0dce5454
UH		 1152 compatible = "fixed-factor-clock";
1153 clocks = <&cpg_clocks R8A7794_CLK_PLL3>;
1154 #clock-cells = <0>;
1155 clock-div = <8>;
1156 clock-mult = <1>;
0dce5454 1157 };
337f6bef 1158 mp_clk: mp {
0dce5454
UH		 1159 compatible = "fixed-factor-clock";
1160 clocks = <&pll1_div2_clk>;
1161 #clock-cells = <0>;
1162 clock-div = <15>;
1163 clock-mult = <1>;
0dce5454 1164 };
337f6bef 1165 cp_clk: cp {
0dce5454
UH		 1166 compatible = "fixed-factor-clock";
1167 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
1168 #clock-cells = <0>;
1169 clock-div = <48>;
1170 clock-mult = <1>;
0dce5454
UH		 1171 };
1172
337f6bef 1173 acp_clk: acp {
0dce5454
UH		 1174 compatible = "fixed-factor-clock";
1175 clocks = <&extal_clk>;
1176 #clock-cells = <0>;
1177 clock-div = <2>;
1178 clock-mult = <1>;
0dce5454
UH		 1179 };
1180
1181 /* Gate clocks */
1182 mstp0_clks: mstp0_clks@e6150130 {
1183 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1184 reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>;
1185 clocks = <&mp_clk>;
1186 #clock-cells = <1>;
1045d065 1187 clock-indices = <R8A7794_CLK_MSIOF0>;
0dce5454
UH		 1188 clock-output-names = "msiof0";
1189 };
1190 mstp1_clks: mstp1_clks@e6150134 {
1191 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1192 reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
dc3cf93d
YH		 1193 clocks = <&zs_clk>, <&zs_clk>, <&p_clk>, <&zg_clk>, <&zs_clk>,
1194 <&zs_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>, <&cp_clk>,
1195 <&zs_clk>, <&zs_clk>;
0dce5454 1196 #clock-cells = <1>;
1045d065 1197 clock-indices = <
dc3cf93d
YH		 1198 R8A7794_CLK_VCP0 R8A7794_CLK_VPC0 R8A7794_CLK_TMU1
1199 R8A7794_CLK_3DG R8A7794_CLK_2DDMAC R8A7794_CLK_FDP1_0
1200 R8A7794_CLK_TMU3 R8A7794_CLK_TMU2 R8A7794_CLK_CMT0
1201 R8A7794_CLK_TMU0 R8A7794_CLK_VSP1_DU0 R8A7794_CLK_VSP1_S
0dce5454
UH		 1202 >;
1203 clock-output-names =
dc3cf93d
YH		 1204 "vcp0", "vpc0", "tmu1", "3dg", "2ddmac", "fdp1-0",
1205 "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du0", "vsps";
0dce5454
UH		 1206 };
1207 mstp2_clks: mstp2_clks@e6150138 {
1208 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1209 reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
1210 clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
be16cd38
HY		 1211 <&mp_clk>, <&mp_clk>, <&mp_clk>,
1212 <&zs_clk>, <&zs_clk>;
0dce5454 1213 #clock-cells = <1>;
1045d065 1214 clock-indices = <
0dce5454
UH		 1215 R8A7794_CLK_SCIFA2 R8A7794_CLK_SCIFA1 R8A7794_CLK_SCIFA0
1216 R8A7794_CLK_MSIOF2 R8A7794_CLK_SCIFB0 R8A7794_CLK_SCIFB1
1217 R8A7794_CLK_MSIOF1 R8A7794_CLK_SCIFB2
be16cd38 1218 R8A7794_CLK_SYS_DMAC1 R8A7794_CLK_SYS_DMAC0
0dce5454
UH		 1219 >;
1220 clock-output-names =
1221 "scifa2", "scifa1", "scifa0", "msiof2", "scifb0",
be16cd38
HY		 1222 "scifb1", "msiof1", "scifb2",
1223 "sys-dmac1", "sys-dmac0";
0dce5454
UH		 1224 };
1225 mstp3_clks: mstp3_clks@e615013c {
1226 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1227 reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
5e7e1554 1228 clocks = <&sd3_clk>, <&sd2_clk>, <&cpg_clocks R8A7794_CLK_SD0>,
a856b195
SH		 1229 <&mmc0_clk>, <&hp_clk>, <&hp_clk>, <&rclk_clk>,
1230 <&hp_clk>, <&hp_clk>;
0dce5454 1231 #clock-cells = <1>;
1045d065 1232 clock-indices = <
8e181633 1233 R8A7794_CLK_SDHI2 R8A7794_CLK_SDHI1 R8A7794_CLK_SDHI0
a856b195
SH		 1234 R8A7794_CLK_MMCIF0 R8A7794_CLK_IIC0
1235 R8A7794_CLK_IIC1 R8A7794_CLK_CMT1
deac150c 1236 R8A7794_CLK_USBDMAC0 R8A7794_CLK_USBDMAC1
0dce5454
UH		 1237 >;
1238 clock-output-names =
8e181633 1239 "sdhi2", "sdhi1", "sdhi0",
a856b195
SH		 1240 "mmcif0", "i2c6", "i2c7",
1241 "cmt1", "usbdmac0", "usbdmac1";
0dce5454 1242 };
1c5ca5db
GU		 1243 mstp4_clks: mstp4_clks@e6150140 {
1244 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1245 reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>;
1246 clocks = <&cp_clk>;
1247 #clock-cells = <1>;
1248 clock-indices = <R8A7794_CLK_IRQC>;
1249 clock-output-names = "irqc";
1250 };
2a29f9d6
SS		 1251 mstp5_clks: mstp5_clks@e6150144 {
1252 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1253 reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
059baea1 1254 clocks = <&hp_clk>, <&p_clk>;
2a29f9d6
SS		 1255 #clock-cells = <1>;
1256 clock-indices = <R8A7794_CLK_AUDIO_DMAC0
1257 R8A7794_CLK_PWM>;
1258 clock-output-names = "audmac0", "pwm";
1259 };
0dce5454
UH		 1260 mstp7_clks: mstp7_clks@e615014c {
1261 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1262 reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
c7bab9f9
SU		 1263 clocks = <&mp_clk>, <&mp_clk>,
1264 <&zs_clk>, <&p_clk>, <&p_clk>, <&zs_clk>,
9859cd3b
LP		 1265 <&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
1266 <&zx_clk>;
0dce5454 1267 #clock-cells = <1>;
1045d065 1268 clock-indices = <
c7bab9f9 1269 R8A7794_CLK_EHCI R8A7794_CLK_HSUSB
0dce5454
UH		 1270 R8A7794_CLK_HSCIF2 R8A7794_CLK_SCIF5
1271 R8A7794_CLK_SCIF4 R8A7794_CLK_HSCIF1 R8A7794_CLK_HSCIF0
1272 R8A7794_CLK_SCIF3 R8A7794_CLK_SCIF2 R8A7794_CLK_SCIF1
9859cd3b 1273 R8A7794_CLK_SCIF0 R8A7794_CLK_DU0
0dce5454
UH		 1274 >;
1275 clock-output-names =
c7bab9f9 1276 "ehci", "hsusb",
0dce5454 1277 "hscif2", "scif5", "scif4", "hscif1", "hscif0",
9859cd3b 1278 "scif3", "scif2", "scif1", "scif0", "du0";
0dce5454
UH		 1279 };
1280 mstp8_clks: mstp8_clks@e6150990 {
1281 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1282 reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
255a4042 1283 clocks = <&zg_clk>, <&zg_clk>, <&hp_clk>, <&p_clk>;
0dce5454 1284 #clock-cells = <1>;
1045d065 1285 clock-indices = <
255a4042
SS		 1286 R8A7794_CLK_VIN1 R8A7794_CLK_VIN0
1287 R8A7794_CLK_ETHERAVB R8A7794_CLK_ETHER
0dce5454
UH		 1288 >;
1289 clock-output-names =
255a4042 1290 "vin1", "vin0", "etheravb", "ether";
0dce5454 1291 };
3281480b
HN		 1292 mstp9_clks: mstp9_clks@e6150994 {
1293 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1294 reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
3f37e018 1295 clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
e980f941
SH		 1296 <&cp_clk>, <&cp_clk>, <&cp_clk>, <&p_clk>,
1297 <&p_clk>, <&cpg_clocks R8A7794_CLK_QSPI>,
1298 <&hp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>,
1299 <&hp_clk>, <&hp_clk>;
3281480b 1300 #clock-cells = <1>;
3f37e018
SS		 1301 clock-indices = <R8A7794_CLK_GPIO6 R8A7794_CLK_GPIO5
1302 R8A7794_CLK_GPIO4 R8A7794_CLK_GPIO3
1303 R8A7794_CLK_GPIO2 R8A7794_CLK_GPIO1
e980f941
SH		 1304 R8A7794_CLK_GPIO0 R8A7794_CLK_RCAN1
1305 R8A7794_CLK_RCAN0 R8A7794_CLK_QSPI_MOD
3f37e018
SS		 1306 R8A7794_CLK_I2C5 R8A7794_CLK_I2C4
1307 R8A7794_CLK_I2C3 R8A7794_CLK_I2C2
1308 R8A7794_CLK_I2C1 R8A7794_CLK_I2C0>;
c5d82c99 1309 clock-output-names =
3f37e018 1310 "gpio6", "gpio5", "gpio4", "gpio3", "gpio2",
e980f941 1311 "gpio1", "gpio0", "rcan1", "rcan0", "qspi_mod",
3f37e018 1312 "i2c5", "i2c4", "i2c3", "i2c2", "i2c1", "i2c0";
3281480b 1313 };
975fb77f
SS		 1314 mstp10_clks: mstp10_clks@e6150998 {
1315 compatible = "renesas,r8a7794-mstp-clocks",
1316 "renesas,cpg-mstp-clocks";
1317 reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>;
1318 clocks = <&p_clk>,
1319 <&mstp10_clks R8A7794_CLK_SSI_ALL>,
1320 <&mstp10_clks R8A7794_CLK_SSI_ALL>,
1321 <&mstp10_clks R8A7794_CLK_SSI_ALL>,
1322 <&mstp10_clks R8A7794_CLK_SSI_ALL>,
1323 <&mstp10_clks R8A7794_CLK_SSI_ALL>,
1324 <&mstp10_clks R8A7794_CLK_SSI_ALL>,
1325 <&mstp10_clks R8A7794_CLK_SSI_ALL>,
1326 <&mstp10_clks R8A7794_CLK_SSI_ALL>,
1327 <&mstp10_clks R8A7794_CLK_SSI_ALL>,
1328 <&mstp10_clks R8A7794_CLK_SSI_ALL>,
1329 <&p_clk>,
1330 <&mstp10_clks R8A7794_CLK_SCU_ALL>,
1331 <&mstp10_clks R8A7794_CLK_SCU_ALL>,
1332 <&mstp10_clks R8A7794_CLK_SCU_ALL>,
1333 <&mstp10_clks R8A7794_CLK_SCU_ALL>,
1334 <&mstp10_clks R8A7794_CLK_SCU_ALL>,
1335 <&mstp10_clks R8A7794_CLK_SCU_ALL>,
1336 <&mstp10_clks R8A7794_CLK_SCU_ALL>,
1337 <&mstp10_clks R8A7794_CLK_SCU_ALL>,
1338 <&mstp10_clks R8A7794_CLK_SCU_ALL>,
1339 <&mstp10_clks R8A7794_CLK_SCU_ALL>;
1340 #clock-cells = <1>;
1341 clock-indices = <R8A7794_CLK_SSI_ALL
1342 R8A7794_CLK_SSI9 R8A7794_CLK_SSI8
1343 R8A7794_CLK_SSI7 R8A7794_CLK_SSI6
1344 R8A7794_CLK_SSI5 R8A7794_CLK_SSI4
1345 R8A7794_CLK_SSI3 R8A7794_CLK_SSI2
1346 R8A7794_CLK_SSI1 R8A7794_CLK_SSI0
1347 R8A7794_CLK_SCU_ALL
1348 R8A7794_CLK_SCU_DVC1
1349 R8A7794_CLK_SCU_DVC0
1350 R8A7794_CLK_SCU_CTU1_MIX1
1351 R8A7794_CLK_SCU_CTU0_MIX0
1352 R8A7794_CLK_SCU_SRC6
1353 R8A7794_CLK_SCU_SRC5
1354 R8A7794_CLK_SCU_SRC4
1355 R8A7794_CLK_SCU_SRC3
1356 R8A7794_CLK_SCU_SRC2
1357 R8A7794_CLK_SCU_SRC1>;
1358 clock-output-names = "ssi-all", "ssi9", "ssi8", "ssi7",
1359 "ssi6", "ssi5", "ssi4", "ssi3",
1360 "ssi2", "ssi1", "ssi0",
1361 "scu-all", "scu-dvc1", "scu-dvc0",
1362 "scu-ctu1-mix1", "scu-ctu0-mix0",
1363 "scu-src6", "scu-src5", "scu-src4",
1364 "scu-src3", "scu-src2", "scu-src1";
1365 };
0dce5454
UH		 1366 mstp11_clks: mstp11_clks@e615099c {
1367 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1368 reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>;
1369 clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>;
1370 #clock-cells = <1>;
1045d065 1371 clock-indices = <
0dce5454
UH		 1372 R8A7794_CLK_SCIFA3 R8A7794_CLK_SCIFA4 R8A7794_CLK_SCIFA5
1373 >;
1374 clock-output-names = "scifa3", "scifa4", "scifa5";
1375 };
1376 };
1cb2794f 1377
0761ff2a
GU		 1378 sysc: system-controller@e6180000 {
1379 compatible = "renesas,r8a7794-sysc";
1380 reg = <0 0xe6180000 0 0x0200>;
1381 #power-domain-cells = <1>;
1382 };
1383
1cb2794f 1384 ipmmu_sy0: mmu@e6280000 {
0da4cfd1 1385 compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa";
1cb2794f 1386 reg = <0 0xe6280000 0 0x1000>;
8d47e6af
SH		 1387 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
1388 <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
1cb2794f
LP		 1389 #iommu-cells = <1>;
1390 status = "disabled";
1391 };
1392
1393 ipmmu_sy1: mmu@e6290000 {
0da4cfd1 1394 compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa";
1cb2794f 1395 reg = <0 0xe6290000 0 0x1000>;
8d47e6af 1396 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
1cb2794f
LP		 1397 #iommu-cells = <1>;
1398 status = "disabled";
1399 };
1400
1401 ipmmu_ds: mmu@e6740000 {
0da4cfd1 1402 compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa";
1cb2794f 1403 reg = <0 0xe6740000 0 0x1000>;
8d47e6af
SH		 1404 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
1405 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
1cb2794f 1406 #iommu-cells = <1>;
832d3e4c 1407 status = "disabled";
1cb2794f
LP		 1408 };
1409
1410 ipmmu_mp: mmu@ec680000 {
0da4cfd1 1411 compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa";
1cb2794f 1412 reg = <0 0xec680000 0 0x1000>;
8d47e6af 1413 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
1cb2794f
LP		 1414 #iommu-cells = <1>;
1415 status = "disabled";
1416 };
1417
1418 ipmmu_mx: mmu@fe951000 {
0da4cfd1 1419 compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa";
1cb2794f 1420 reg = <0 0xfe951000 0 0x1000>;
8d47e6af
SH		 1421 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
1422 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
1cb2794f 1423 #iommu-cells = <1>;
832d3e4c 1424 status = "disabled";
1cb2794f
LP		 1425 };
1426
1427 ipmmu_gp: mmu@e62a0000 {
0da4cfd1 1428 compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa";
1cb2794f 1429 reg = <0 0xe62a0000 0 0x1000>;
8d47e6af
SH		 1430 interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
1431 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
1cb2794f
LP		 1432 #iommu-cells = <1>;
1433 status = "disabled";
1434 };
320d6c5a
SS		 1435
1436 rcar_sound: sound@ec500000 {
1437 /*
1438 * #sound-dai-cells is required
1439 *
1440 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
1441 * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
1442 */
1443 compatible = "renesas,rcar_sound-r8a7794",
1444 "renesas,rcar_sound-gen2";
1445 reg = <0 0xec500000 0 0x1000>, /* SCU */
1446 <0 0xec5a0000 0 0x100>, /* ADG */
1447 <0 0xec540000 0 0x1000>, /* SSIU */
1448 <0 0xec541000 0 0x280>, /* SSI */
1449 <0 0xec740000 0 0x200>; /* Audio DMAC peri peri */
1450 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
1451
1452 clocks = <&mstp10_clks R8A7794_CLK_SSI_ALL>,
1453 <&mstp10_clks R8A7794_CLK_SSI9>,
1454 <&mstp10_clks R8A7794_CLK_SSI8>,
1455 <&mstp10_clks R8A7794_CLK_SSI7>,
1456 <&mstp10_clks R8A7794_CLK_SSI6>,
1457 <&mstp10_clks R8A7794_CLK_SSI5>,
1458 <&mstp10_clks R8A7794_CLK_SSI4>,
1459 <&mstp10_clks R8A7794_CLK_SSI3>,
1460 <&mstp10_clks R8A7794_CLK_SSI2>,
1461 <&mstp10_clks R8A7794_CLK_SSI1>,
1462 <&mstp10_clks R8A7794_CLK_SSI0>,
1463 <&mstp10_clks R8A7794_CLK_SCU_SRC6>,
1464 <&mstp10_clks R8A7794_CLK_SCU_SRC5>,
1465 <&mstp10_clks R8A7794_CLK_SCU_SRC4>,
1466 <&mstp10_clks R8A7794_CLK_SCU_SRC3>,
1467 <&mstp10_clks R8A7794_CLK_SCU_SRC2>,
1468 <&mstp10_clks R8A7794_CLK_SCU_SRC1>,
1469 <&mstp10_clks R8A7794_CLK_SCU_CTU0_MIX0>,
1470 <&mstp10_clks R8A7794_CLK_SCU_CTU1_MIX1>,
1471 <&mstp10_clks R8A7794_CLK_SCU_CTU0_MIX0>,
1472 <&mstp10_clks R8A7794_CLK_SCU_CTU1_MIX1>,
1473 <&mstp10_clks R8A7794_CLK_SCU_DVC0>,
1474 <&mstp10_clks R8A7794_CLK_SCU_DVC1>,
1475 <&audio_clka>, <&audio_clkb>, <&audio_clkc>,
1476 <&m2_clk>;
1477 clock-names = "ssi-all",
1478 "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5",
1479 "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0",
1480 "src.6", "src.5", "src.4", "src.3", "src.2",
1481 "src.1",
1482 "ctu.0", "ctu.1",
1483 "mix.0", "mix.1",
1484 "dvc.0", "dvc.1",
1485 "clk_a", "clk_b", "clk_c", "clk_i";
1486 power-domains = <&cpg_clocks>;
1487
1488 status = "disabled";
1489
1490 rcar_sound,dvc {
1491 dvc0: dvc@0 {
1492 dmas = <&audma0 0xbc>;
1493 dma-names = "tx";
1494 };
1495 dvc1: dvc@1 {
1496 dmas = <&audma0 0xbe>;
1497 dma-names = "tx";
1498 };
1499 };
1500
1501 rcar_sound,mix {
1502 mix0: mix@0 { };
1503 mix1: mix@1 { };
1504 };
1505
1506 rcar_sound,ctu {
1507 ctu00: ctu@0 { };
1508 ctu01: ctu@1 { };
1509 ctu02: ctu@2 { };
1510 ctu03: ctu@3 { };
1511 ctu10: ctu@4 { };
1512 ctu11: ctu@5 { };
1513 ctu12: ctu@6 { };
1514 ctu13: ctu@7 { };
1515 };
1516
1517 rcar_sound,src {
1518 src@0 {
1519 status = "disabled";
1520 };
1521 src1: src@1 {
1522 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1523 dmas = <&audma0 0x87>, <&audma0 0x9c>;
1524 dma-names = "rx", "tx";
1525 };
1526 src2: src@2 {
1527 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1528 dmas = <&audma0 0x89>, <&audma0 0x9e>;
1529 dma-names = "rx", "tx";
1530 };
1531 src3: src@3 {
1532 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1533 dmas = <&audma0 0x8b>, <&audma0 0xa0>;
1534 dma-names = "rx", "tx";
1535 };
1536 src4: src@4 {
1537 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1538 dmas = <&audma0 0x8d>, <&audma0 0xb0>;
1539 dma-names = "rx", "tx";
1540 };
1541 src5: src@5 {
1542 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1543 dmas = <&audma0 0x8f>, <&audma0 0xb2>;
1544 dma-names = "rx", "tx";
1545 };
1546 src6: src@6 {
1547 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1548 dmas = <&audma0 0x91>, <&audma0 0xb4>;
1549 dma-names = "rx", "tx";
1550 };
1551 };
1552
1553 rcar_sound,ssi {
1554 ssi0: ssi@0 {
1555 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
1556 dmas = <&audma0 0x01>, <&audma0 0x02>,
1557 <&audma0 0x15>, <&audma0 0x16>;
1558 dma-names = "rx", "tx", "rxu", "txu";
1559 };
1560 ssi1: ssi@1 {
1561 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
1562 dmas = <&audma0 0x03>, <&audma0 0x04>,
1563 <&audma0 0x49>, <&audma0 0x4a>;
1564 dma-names = "rx", "tx", "rxu", "txu";
1565 };
1566 ssi2: ssi@2 {
1567 interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
1568 dmas = <&audma0 0x05>, <&audma0 0x06>,
1569 <&audma0 0x63>, <&audma0 0x64>;
1570 dma-names = "rx", "tx", "rxu", "txu";
1571 };
1572 ssi3: ssi@3 {
1573 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1574 dmas = <&audma0 0x07>, <&audma0 0x08>,
1575 <&audma0 0x6f>, <&audma0 0x70>;
1576 dma-names = "rx", "tx", "rxu", "txu";
1577 };
1578 ssi4: ssi@4 {
1579 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
1580 dmas = <&audma0 0x09>, <&audma0 0x0a>,
1581 <&audma0 0x71>, <&audma0 0x72>;
1582 dma-names = "rx", "tx", "rxu", "txu";
1583 };
1584 ssi5: ssi@5 {
1585 interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
1586 dmas = <&audma0 0x0b>, <&audma0 0x0c>,
1587 <&audma0 0x73>, <&audma0 0x74>;
1588 dma-names = "rx", "tx", "rxu", "txu";
1589 };
1590 ssi6: ssi@6 {
1591 interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
1592 dmas = <&audma0 0x0d>, <&audma0 0x0e>,
1593 <&audma0 0x75>, <&audma0 0x76>;
1594 dma-names = "rx", "tx", "rxu", "txu";
1595 };
1596 ssi7: ssi@7 {
1597 interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
1598 dmas = <&audma0 0x0f>, <&audma0 0x10>,
1599 <&audma0 0x79>, <&audma0 0x7a>;
1600 dma-names = "rx", "tx", "rxu", "txu";
1601 };
1602 ssi8: ssi@8 {
1603 interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
1604 dmas = <&audma0 0x11>, <&audma0 0x12>,
1605 <&audma0 0x7b>, <&audma0 0x7c>;
1606 dma-names = "rx", "tx", "rxu", "txu";
1607 };
1608 ssi9: ssi@9 {
1609 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
1610 dmas = <&audma0 0x13>, <&audma0 0x14>,
1611 <&audma0 0x7d>, <&audma0 0x7e>;
1612 dma-names = "rx", "tx", "rxu", "txu";
1613 };
1614 };
1615 };
0dce5454 1616};
Linux kernel - Deliverables
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