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faea098e XZ |
1 | /* |
2 | * This file is dual-licensed: you can use it either under the terms | |
3 | * of the GPL or the X11 license, at your option. Note that this dual | |
4 | * licensing only applies to this file, and not this project as a | |
5 | * whole. | |
6 | * | |
7 | * a) This file is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License as | |
9 | * published by the Free Software Foundation; either version 2 of the | |
10 | * License, or (at your option) any later version. | |
11 | * | |
12 | * This file is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * Or, alternatively, | |
18 | * | |
19 | * b) Permission is hereby granted, free of charge, to any person | |
20 | * obtaining a copy of this software and associated documentation | |
21 | * files (the "Software"), to deal in the Software without | |
22 | * restriction, including without limitation the rights to use, | |
23 | * copy, modify, merge, publish, distribute, sublicense, and/or | |
24 | * sell copies of the Software, and to permit persons to whom the | |
25 | * Software is furnished to do so, subject to the following | |
26 | * conditions: | |
27 | * | |
28 | * The above copyright notice and this permission notice shall be | |
29 | * included in all copies or substantial portions of the Software. | |
30 | * | |
31 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
32 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES | |
33 | * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
34 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT | |
35 | * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, | |
36 | * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
37 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
38 | * OTHER DEALINGS IN THE SOFTWARE. | |
39 | */ | |
40 | ||
41 | #include <dt-bindings/gpio/gpio.h> | |
42 | #include <dt-bindings/interrupt-controller/irq.h> | |
43 | #include <dt-bindings/interrupt-controller/arm-gic.h> | |
44 | #include <dt-bindings/pinctrl/rockchip.h> | |
45 | #include <dt-bindings/clock/rk3036-cru.h> | |
b60ab70b | 46 | #include <dt-bindings/soc/rockchip,boot-mode.h> |
faea098e XZ |
47 | |
48 | / { | |
3e7f5984 JMC |
49 | #address-cells = <1>; |
50 | #size-cells = <1>; | |
51 | ||
faea098e XZ |
52 | compatible = "rockchip,rk3036"; |
53 | ||
54 | interrupt-parent = <&gic>; | |
55 | ||
56 | aliases { | |
57 | i2c0 = &i2c0; | |
58 | i2c1 = &i2c1; | |
59 | i2c2 = &i2c2; | |
60 | mshc0 = &emmc; | |
187d7967 CW |
61 | mshc1 = &sdmmc; |
62 | mshc2 = &sdio; | |
faea098e XZ |
63 | serial0 = &uart0; |
64 | serial1 = &uart1; | |
65 | serial2 = &uart2; | |
f629fcfa | 66 | spi = &spi; |
faea098e XZ |
67 | }; |
68 | ||
faea098e XZ |
69 | cpus { |
70 | #address-cells = <1>; | |
71 | #size-cells = <0>; | |
72 | enable-method = "rockchip,rk3036-smp"; | |
73 | ||
74 | cpu0: cpu@f00 { | |
75 | device_type = "cpu"; | |
76 | compatible = "arm,cortex-a7"; | |
77 | reg = <0xf00>; | |
78 | resets = <&cru SRST_CORE0>; | |
79 | operating-points = < | |
80 | /* KHz uV */ | |
81 | 816000 1000000 | |
82 | >; | |
83 | clock-latency = <40000>; | |
84 | clocks = <&cru ARMCLK>; | |
85 | }; | |
86 | ||
87 | cpu1: cpu@f01 { | |
88 | device_type = "cpu"; | |
89 | compatible = "arm,cortex-a7"; | |
90 | reg = <0xf01>; | |
91 | resets = <&cru SRST_CORE1>; | |
92 | }; | |
93 | }; | |
94 | ||
95 | amba { | |
2ef7d5f3 | 96 | compatible = "simple-bus"; |
faea098e XZ |
97 | #address-cells = <1>; |
98 | #size-cells = <1>; | |
99 | ranges; | |
100 | ||
101 | pdma: pdma@20078000 { | |
102 | compatible = "arm,pl330", "arm,primecell"; | |
103 | reg = <0x20078000 0x4000>; | |
104 | interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, | |
105 | <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; | |
106 | #dma-cells = <1>; | |
29f12bba | 107 | arm,pl330-broken-no-flushp; |
faea098e XZ |
108 | clocks = <&cru ACLK_DMAC2>; |
109 | clock-names = "apb_pclk"; | |
110 | }; | |
111 | }; | |
112 | ||
113 | arm-pmu { | |
114 | compatible = "arm,cortex-a7-pmu"; | |
115 | interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, | |
116 | <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; | |
117 | interrupt-affinity = <&cpu0>, <&cpu1>; | |
118 | }; | |
119 | ||
d9abae3c CW |
120 | display-subsystem { |
121 | compatible = "rockchip,display-subsystem"; | |
122 | ports = <&vop_out>; | |
123 | }; | |
124 | ||
faea098e XZ |
125 | timer { |
126 | compatible = "arm,armv7-timer"; | |
127 | arm,cpu-registers-not-fw-configured; | |
128 | interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>, | |
129 | <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>, | |
130 | <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>, | |
131 | <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; | |
132 | clock-frequency = <24000000>; | |
133 | }; | |
134 | ||
135 | xin24m: oscillator { | |
136 | compatible = "fixed-clock"; | |
137 | clock-frequency = <24000000>; | |
138 | clock-output-names = "xin24m"; | |
139 | #clock-cells = <0>; | |
140 | }; | |
141 | ||
142 | bus_intmem@10080000 { | |
143 | compatible = "mmio-sram"; | |
144 | reg = <0x10080000 0x2000>; | |
145 | #address-cells = <1>; | |
146 | #size-cells = <1>; | |
147 | ranges = <0 0x10080000 0x2000>; | |
148 | ||
149 | smp-sram@0 { | |
150 | compatible = "rockchip,rk3066-smp-sram"; | |
151 | reg = <0x00 0x10>; | |
152 | }; | |
153 | }; | |
154 | ||
d9abae3c CW |
155 | vop: vop@10118000 { |
156 | compatible = "rockchip,rk3036-vop"; | |
157 | reg = <0x10118000 0x19c>; | |
158 | interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; | |
159 | clocks = <&cru ACLK_LCDC>, <&cru SCLK_LCDC>, <&cru HCLK_LCDC>; | |
160 | clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; | |
161 | resets = <&cru SRST_LCDC1_A>, <&cru SRST_LCDC1_H>, <&cru SRST_LCDC1_D>; | |
162 | reset-names = "axi", "ahb", "dclk"; | |
163 | iommus = <&vop_mmu>; | |
164 | status = "disabled"; | |
165 | ||
166 | vop_out: port { | |
167 | #address-cells = <1>; | |
168 | #size-cells = <0>; | |
b7217cf1 CW |
169 | vop_out_hdmi: endpoint@0 { |
170 | reg = <0>; | |
171 | remote-endpoint = <&hdmi_in_vop>; | |
172 | }; | |
d9abae3c CW |
173 | }; |
174 | }; | |
175 | ||
176 | vop_mmu: iommu@10118300 { | |
177 | compatible = "rockchip,iommu"; | |
178 | reg = <0x10118300 0x100>; | |
179 | interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; | |
180 | interrupt-names = "vop_mmu"; | |
181 | #iommu-cells = <0>; | |
182 | status = "disabled"; | |
183 | }; | |
184 | ||
faea098e XZ |
185 | gic: interrupt-controller@10139000 { |
186 | compatible = "arm,gic-400"; | |
187 | interrupt-controller; | |
188 | #interrupt-cells = <3>; | |
189 | #address-cells = <0>; | |
190 | ||
191 | reg = <0x10139000 0x1000>, | |
192 | <0x1013a000 0x1000>, | |
193 | <0x1013c000 0x2000>, | |
194 | <0x1013e000 0x2000>; | |
195 | interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; | |
196 | }; | |
197 | ||
198 | usb_otg: usb@10180000 { | |
0082180c | 199 | compatible = "rockchip,rk3036-usb", "rockchip,rk3066-usb", |
faea098e XZ |
200 | "snps,dwc2"; |
201 | reg = <0x10180000 0x40000>; | |
202 | interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; | |
203 | clocks = <&cru HCLK_OTG0>; | |
204 | clock-names = "otg"; | |
205 | dr_mode = "otg"; | |
206 | g-np-tx-fifo-size = <16>; | |
207 | g-rx-fifo-size = <275>; | |
208 | g-tx-fifo-size = <256 128 128 64 64 32>; | |
209 | g-use-dma; | |
210 | status = "disabled"; | |
211 | }; | |
212 | ||
213 | usb_host: usb@101c0000 { | |
0082180c | 214 | compatible = "rockchip,rk3036-usb", "rockchip,rk3066-usb", |
faea098e XZ |
215 | "snps,dwc2"; |
216 | reg = <0x101c0000 0x40000>; | |
217 | interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; | |
218 | clocks = <&cru HCLK_OTG1>; | |
219 | clock-names = "otg"; | |
220 | dr_mode = "host"; | |
221 | status = "disabled"; | |
222 | }; | |
223 | ||
af671e7b XZ |
224 | emac: ethernet@10200000 { |
225 | compatible = "rockchip,rk3036-emac", "snps,arc-emac"; | |
226 | reg = <0x10200000 0x4000>; | |
227 | interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; | |
228 | #address-cells = <1>; | |
229 | #size-cells = <0>; | |
230 | rockchip,grf = <&grf>; | |
231 | clocks = <&cru HCLK_MAC>, <&cru SCLK_MACREF>, <&cru SCLK_MAC>; | |
232 | clock-names = "hclk", "macref", "macclk"; | |
233 | /* | |
234 | * Fix the emac parent clock is DPLL instead of APLL. | |
235 | * since that will cause some unstable things if the cpufreq | |
236 | * is working. (e.g: the accurate 50MHz what mac_ref need) | |
237 | */ | |
238 | assigned-clocks = <&cru SCLK_MACPLL>; | |
239 | assigned-clock-parents = <&cru PLL_DPLL>; | |
240 | max-speed = <100>; | |
241 | phy-mode = "rmii"; | |
242 | status = "disabled"; | |
243 | }; | |
244 | ||
187d7967 CW |
245 | sdmmc: dwmmc@10214000 { |
246 | compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc"; | |
247 | reg = <0x10214000 0x4000>; | |
248 | clock-frequency = <37500000>; | |
249 | clock-freq-min-max = <400000 37500000>; | |
250 | clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>; | |
251 | clock-names = "biu", "ciu"; | |
252 | fifo-depth = <0x100>; | |
253 | interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; | |
254 | status = "disabled"; | |
255 | }; | |
256 | ||
257 | sdio: dwmmc@10218000 { | |
258 | compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc"; | |
259 | reg = <0x10218000 0x4000>; | |
260 | clock-freq-min-max = <400000 37500000>; | |
261 | clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, | |
262 | <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; | |
263 | clock-names = "biu", "ciu", "ciu_drv", "ciu_sample"; | |
264 | fifo-depth = <0x100>; | |
265 | interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; | |
266 | status = "disabled"; | |
267 | }; | |
268 | ||
faea098e | 269 | emmc: dwmmc@1021c000 { |
0082180c | 270 | compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc"; |
faea098e XZ |
271 | reg = <0x1021c000 0x4000>; |
272 | interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; | |
faea098e XZ |
273 | bus-width = <8>; |
274 | cap-mmc-highspeed; | |
275 | clock-frequency = <37500000>; | |
276 | clock-freq-min-max = <400000 37500000>; | |
277 | clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, | |
278 | <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; | |
279 | clock-names = "biu", "ciu", "ciu_drv", "ciu_sample"; | |
280 | default-sample-phase = <158>; | |
281 | disable-wp; | |
282 | dmas = <&pdma 12>; | |
283 | dma-names = "rx-tx"; | |
284 | fifo-depth = <0x100>; | |
285 | mmc-ddr-1_8v; | |
286 | non-removable; | |
287 | num-slots = <1>; | |
288 | pinctrl-names = "default"; | |
289 | pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; | |
290 | status = "disabled"; | |
291 | }; | |
292 | ||
293 | i2s: i2s@10220000 { | |
294 | compatible = "rockchip,rk3036-i2s", "rockchip,rk3066-i2s"; | |
295 | reg = <0x10220000 0x4000>; | |
296 | interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; | |
297 | #address-cells = <1>; | |
298 | #size-cells = <0>; | |
3860aa1c HS |
299 | clock-names = "i2s_clk", "i2s_hclk"; |
300 | clocks = <&cru SCLK_I2S>, <&cru HCLK_I2S>; | |
faea098e XZ |
301 | dmas = <&pdma 0>, <&pdma 1>; |
302 | dma-names = "tx", "rx"; | |
303 | pinctrl-names = "default"; | |
304 | pinctrl-0 = <&i2s_bus>; | |
305 | status = "disabled"; | |
306 | }; | |
307 | ||
308 | cru: clock-controller@20000000 { | |
309 | compatible = "rockchip,rk3036-cru"; | |
310 | reg = <0x20000000 0x1000>; | |
311 | rockchip,grf = <&grf>; | |
312 | #clock-cells = <1>; | |
313 | #reset-cells = <1>; | |
314 | assigned-clocks = <&cru PLL_GPLL>; | |
315 | assigned-clock-rates = <594000000>; | |
316 | }; | |
317 | ||
318 | grf: syscon@20008000 { | |
b60ab70b | 319 | compatible = "rockchip,rk3036-grf", "syscon", "simple-mfd"; |
faea098e | 320 | reg = <0x20008000 0x1000>; |
b60ab70b AY |
321 | |
322 | reboot-mode { | |
323 | compatible = "syscon-reboot-mode"; | |
324 | offset = <0x1d8>; | |
325 | mode-normal = <BOOT_NORMAL>; | |
326 | mode-recovery = <BOOT_RECOVERY>; | |
327 | mode-bootloader = <BOOT_FASTBOOT>; | |
328 | mode-loader = <BOOT_BL_DOWNLOAD>; | |
329 | }; | |
faea098e XZ |
330 | }; |
331 | ||
332 | acodec: acodec-ana@20030000 { | |
333 | compatible = "rk3036-codec"; | |
334 | reg = <0x20030000 0x4000>; | |
335 | rockchip,grf = <&grf>; | |
336 | clock-names = "acodec_pclk"; | |
337 | clocks = <&cru PCLK_ACODEC>; | |
338 | status = "disabled"; | |
339 | }; | |
340 | ||
b7217cf1 CW |
341 | hdmi: hdmi@20034000 { |
342 | compatible = "rockchip,rk3036-inno-hdmi"; | |
343 | reg = <0x20034000 0x4000>; | |
344 | interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; | |
345 | clocks = <&cru PCLK_HDMI>; | |
346 | clock-names = "pclk"; | |
347 | rockchip,grf = <&grf>; | |
348 | pinctrl-names = "default"; | |
349 | pinctrl-0 = <&hdmi_ctl>; | |
350 | status = "disabled"; | |
351 | ||
352 | hdmi_in: port { | |
353 | #address-cells = <1>; | |
354 | #size-cells = <0>; | |
355 | hdmi_in_vop: endpoint@0 { | |
356 | reg = <0>; | |
357 | remote-endpoint = <&vop_out_hdmi>; | |
358 | }; | |
359 | }; | |
360 | }; | |
361 | ||
faea098e XZ |
362 | timer: timer@20044000 { |
363 | compatible = "rockchip,rk3036-timer", "rockchip,rk3288-timer"; | |
364 | reg = <0x20044000 0x20>; | |
365 | interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; | |
366 | clocks = <&xin24m>, <&cru PCLK_TIMER>; | |
367 | clock-names = "timer", "pclk"; | |
368 | }; | |
369 | ||
370 | pwm0: pwm@20050000 { | |
371 | compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm"; | |
372 | reg = <0x20050000 0x10>; | |
373 | #pwm-cells = <3>; | |
374 | clocks = <&cru PCLK_PWM>; | |
375 | clock-names = "pwm"; | |
376 | pinctrl-names = "default"; | |
377 | pinctrl-0 = <&pwm0_pin>; | |
378 | status = "disabled"; | |
379 | }; | |
380 | ||
381 | pwm1: pwm@20050010 { | |
382 | compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm"; | |
383 | reg = <0x20050010 0x10>; | |
384 | #pwm-cells = <3>; | |
385 | clocks = <&cru PCLK_PWM>; | |
386 | clock-names = "pwm"; | |
387 | pinctrl-names = "default"; | |
388 | pinctrl-0 = <&pwm1_pin>; | |
389 | status = "disabled"; | |
390 | }; | |
391 | ||
392 | pwm2: pwm@20050020 { | |
393 | compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm"; | |
394 | reg = <0x20050020 0x10>; | |
395 | #pwm-cells = <3>; | |
396 | clocks = <&cru PCLK_PWM>; | |
397 | clock-names = "pwm"; | |
398 | pinctrl-names = "default"; | |
399 | pinctrl-0 = <&pwm2_pin>; | |
400 | status = "disabled"; | |
401 | }; | |
402 | ||
403 | pwm3: pwm@20050030 { | |
404 | compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm"; | |
405 | reg = <0x20050030 0x10>; | |
406 | #pwm-cells = <2>; | |
407 | clocks = <&cru PCLK_PWM>; | |
408 | clock-names = "pwm"; | |
409 | pinctrl-names = "default"; | |
410 | pinctrl-0 = <&pwm3_pin>; | |
411 | status = "disabled"; | |
412 | }; | |
413 | ||
414 | i2c1: i2c@20056000 { | |
0082180c | 415 | compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c"; |
faea098e XZ |
416 | reg = <0x20056000 0x1000>; |
417 | interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; | |
418 | #address-cells = <1>; | |
419 | #size-cells = <0>; | |
420 | clock-names = "i2c"; | |
421 | clocks = <&cru PCLK_I2C1>; | |
422 | pinctrl-names = "default"; | |
423 | pinctrl-0 = <&i2c1_xfer>; | |
424 | status = "disabled"; | |
425 | }; | |
426 | ||
427 | i2c2: i2c@2005a000 { | |
0082180c | 428 | compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c"; |
faea098e XZ |
429 | reg = <0x2005a000 0x1000>; |
430 | interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; | |
431 | #address-cells = <1>; | |
432 | #size-cells = <0>; | |
433 | clock-names = "i2c"; | |
434 | clocks = <&cru PCLK_I2C2>; | |
435 | pinctrl-names = "default"; | |
436 | pinctrl-0 = <&i2c2_xfer>; | |
437 | status = "disabled"; | |
438 | }; | |
439 | ||
440 | uart0: serial@20060000 { | |
441 | compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart"; | |
442 | reg = <0x20060000 0x100>; | |
443 | interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; | |
444 | reg-shift = <2>; | |
445 | reg-io-width = <4>; | |
446 | clock-frequency = <24000000>; | |
447 | clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; | |
448 | clock-names = "baudclk", "apb_pclk"; | |
449 | pinctrl-names = "default"; | |
450 | pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; | |
451 | status = "disabled"; | |
452 | }; | |
453 | ||
454 | uart1: serial@20064000 { | |
455 | compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart"; | |
456 | reg = <0x20064000 0x100>; | |
457 | interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; | |
458 | reg-shift = <2>; | |
459 | reg-io-width = <4>; | |
460 | clock-frequency = <24000000>; | |
461 | clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; | |
462 | clock-names = "baudclk", "apb_pclk"; | |
463 | pinctrl-names = "default"; | |
464 | pinctrl-0 = <&uart1_xfer>; | |
465 | status = "disabled"; | |
466 | }; | |
467 | ||
468 | uart2: serial@20068000 { | |
469 | compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart"; | |
470 | reg = <0x20068000 0x100>; | |
471 | interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; | |
472 | reg-shift = <2>; | |
473 | reg-io-width = <4>; | |
474 | clock-frequency = <24000000>; | |
475 | clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; | |
476 | clock-names = "baudclk", "apb_pclk"; | |
477 | pinctrl-names = "default"; | |
478 | pinctrl-0 = <&uart2_xfer>; | |
479 | status = "disabled"; | |
480 | }; | |
481 | ||
482 | i2c0: i2c@20072000 { | |
0082180c | 483 | compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c"; |
faea098e XZ |
484 | reg = <0x20072000 0x1000>; |
485 | interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; | |
486 | #address-cells = <1>; | |
487 | #size-cells = <0>; | |
488 | clock-names = "i2c"; | |
489 | clocks = <&cru PCLK_I2C0>; | |
490 | pinctrl-names = "default"; | |
491 | pinctrl-0 = <&i2c0_xfer>; | |
492 | status = "disabled"; | |
493 | }; | |
494 | ||
f629fcfa CW |
495 | spi: spi@20074000 { |
496 | compatible = "rockchip,rockchip-spi"; | |
497 | reg = <0x20074000 0x1000>; | |
498 | interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; | |
499 | clocks =<&cru PCLK_SPI>, <&cru SCLK_SPI>; | |
500 | clock-names = "apb-pclk","spi_pclk"; | |
501 | dmas = <&pdma 8>, <&pdma 9>; | |
502 | dma-names = "tx", "rx"; | |
503 | pinctrl-names = "default"; | |
504 | pinctrl-0 = <&spi_txd &spi_rxd &spi_clk &spi_cs0>; | |
505 | #address-cells = <1>; | |
506 | #size-cells = <0>; | |
507 | status = "disabled"; | |
508 | }; | |
509 | ||
faea098e XZ |
510 | pinctrl: pinctrl { |
511 | compatible = "rockchip,rk3036-pinctrl"; | |
512 | rockchip,grf = <&grf>; | |
513 | #address-cells = <1>; | |
514 | #size-cells = <1>; | |
515 | ranges; | |
516 | ||
517 | gpio0: gpio0@2007c000 { | |
518 | compatible = "rockchip,gpio-bank"; | |
519 | reg = <0x2007c000 0x100>; | |
520 | interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; | |
521 | clocks = <&cru PCLK_GPIO0>; | |
522 | ||
523 | gpio-controller; | |
524 | #gpio-cells = <2>; | |
525 | ||
526 | interrupt-controller; | |
527 | #interrupt-cells = <2>; | |
528 | }; | |
529 | ||
530 | gpio1: gpio1@20080000 { | |
531 | compatible = "rockchip,gpio-bank"; | |
532 | reg = <0x20080000 0x100>; | |
533 | interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; | |
534 | clocks = <&cru PCLK_GPIO1>; | |
535 | ||
536 | gpio-controller; | |
537 | #gpio-cells = <2>; | |
538 | ||
539 | interrupt-controller; | |
540 | #interrupt-cells = <2>; | |
541 | }; | |
542 | ||
543 | gpio2: gpio2@20084000 { | |
544 | compatible = "rockchip,gpio-bank"; | |
545 | reg = <0x20084000 0x100>; | |
546 | interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; | |
547 | clocks = <&cru PCLK_GPIO2>; | |
548 | ||
549 | gpio-controller; | |
550 | #gpio-cells = <2>; | |
551 | ||
552 | interrupt-controller; | |
553 | #interrupt-cells = <2>; | |
554 | }; | |
555 | ||
68556dd7 XZ |
556 | pcfg_pull_default: pcfg_pull_default { |
557 | bias-pull-pin-default; | |
faea098e XZ |
558 | }; |
559 | ||
560 | pcfg_pull_none: pcfg-pull-none { | |
561 | bias-disable; | |
562 | }; | |
563 | ||
564 | pwm0 { | |
565 | pwm0_pin: pwm0-pin { | |
566 | rockchip,pins = <0 0 RK_FUNC_2 &pcfg_pull_none>; | |
567 | }; | |
568 | }; | |
569 | ||
570 | pwm1 { | |
571 | pwm1_pin: pwm1-pin { | |
572 | rockchip,pins = <0 1 RK_FUNC_2 &pcfg_pull_none>; | |
573 | }; | |
574 | }; | |
575 | ||
576 | pwm2 { | |
577 | pwm2_pin: pwm2-pin { | |
578 | rockchip,pins = <0 1 2 &pcfg_pull_none>; | |
579 | }; | |
580 | }; | |
581 | ||
582 | pwm3 { | |
583 | pwm3_pin: pwm3-pin { | |
584 | rockchip,pins = <0 27 1 &pcfg_pull_none>; | |
585 | }; | |
586 | }; | |
587 | ||
187d7967 CW |
588 | sdmmc { |
589 | sdmmc_clk: sdmmc-clk { | |
590 | rockchip,pins = <1 16 RK_FUNC_1 &pcfg_pull_none>; | |
591 | }; | |
592 | ||
593 | sdmmc_cmd: sdmmc-cmd { | |
594 | rockchip,pins = <1 15 RK_FUNC_1 &pcfg_pull_default>; | |
595 | }; | |
596 | ||
597 | sdmmc_cd: sdmcc-cd { | |
598 | rockchip,pins = <1 17 RK_FUNC_1 &pcfg_pull_default>; | |
599 | }; | |
600 | ||
601 | sdmmc_bus1: sdmmc-bus1 { | |
602 | rockchip,pins = <1 18 RK_FUNC_1 &pcfg_pull_default>; | |
603 | }; | |
604 | ||
605 | sdmmc_bus4: sdmmc-bus4 { | |
606 | rockchip,pins = <1 18 RK_FUNC_1 &pcfg_pull_default>, | |
607 | <1 19 RK_FUNC_1 &pcfg_pull_default>, | |
608 | <1 20 RK_FUNC_1 &pcfg_pull_default>, | |
609 | <1 21 RK_FUNC_1 &pcfg_pull_default>; | |
610 | }; | |
611 | }; | |
612 | ||
613 | sdio { | |
614 | sdio_bus1: sdio-bus1 { | |
615 | rockchip,pins = <0 11 RK_FUNC_1 &pcfg_pull_default>; | |
616 | }; | |
617 | ||
618 | sdio_bus4: sdio-bus4 { | |
619 | rockchip,pins = <0 11 RK_FUNC_1 &pcfg_pull_default>, | |
620 | <0 12 RK_FUNC_1 &pcfg_pull_default>, | |
621 | <0 13 RK_FUNC_1 &pcfg_pull_default>, | |
622 | <0 14 RK_FUNC_1 &pcfg_pull_default>; | |
623 | }; | |
624 | ||
625 | sdio_cmd: sdio-cmd { | |
626 | rockchip,pins = <0 8 RK_FUNC_1 &pcfg_pull_default>; | |
627 | }; | |
628 | ||
629 | sdio_clk: sdio-clk { | |
630 | rockchip,pins = <0 9 RK_FUNC_1 &pcfg_pull_none>; | |
631 | }; | |
632 | }; | |
633 | ||
faea098e XZ |
634 | emmc { |
635 | /* | |
636 | * We run eMMC at max speed; bump up drive strength. | |
637 | * We also have external pulls, so disable the internal ones. | |
638 | */ | |
639 | emmc_clk: emmc-clk { | |
640 | rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>; | |
641 | }; | |
642 | ||
643 | emmc_cmd: emmc-cmd { | |
68556dd7 | 644 | rockchip,pins = <2 1 RK_FUNC_2 &pcfg_pull_default>; |
faea098e XZ |
645 | }; |
646 | ||
647 | emmc_bus8: emmc-bus8 { | |
68556dd7 XZ |
648 | rockchip,pins = <1 24 RK_FUNC_2 &pcfg_pull_default>, |
649 | <1 25 RK_FUNC_2 &pcfg_pull_default>, | |
650 | <1 26 RK_FUNC_2 &pcfg_pull_default>, | |
651 | <1 27 RK_FUNC_2 &pcfg_pull_default>, | |
652 | <1 28 RK_FUNC_2 &pcfg_pull_default>, | |
653 | <1 29 RK_FUNC_2 &pcfg_pull_default>, | |
654 | <1 30 RK_FUNC_2 &pcfg_pull_default>, | |
655 | <1 31 RK_FUNC_2 &pcfg_pull_default>; | |
faea098e XZ |
656 | }; |
657 | }; | |
658 | ||
af671e7b XZ |
659 | emac { |
660 | emac_xfer: emac-xfer { | |
661 | rockchip,pins = <2 10 RK_FUNC_1 &pcfg_pull_default>, /* crs_dvalid */ | |
662 | <2 13 RK_FUNC_1 &pcfg_pull_default>, /* tx_en */ | |
663 | <2 14 RK_FUNC_1 &pcfg_pull_default>, /* mac_clk */ | |
664 | <2 15 RK_FUNC_1 &pcfg_pull_default>, /* rx_err */ | |
665 | <2 16 RK_FUNC_1 &pcfg_pull_default>, /* rxd1 */ | |
666 | <2 17 RK_FUNC_1 &pcfg_pull_default>, /* rxd0 */ | |
667 | <2 18 RK_FUNC_1 &pcfg_pull_default>, /* txd1 */ | |
668 | <2 19 RK_FUNC_1 &pcfg_pull_default>; /* txd0 */ | |
669 | }; | |
670 | ||
671 | emac_mdio: emac-mdio { | |
672 | rockchip,pins = <2 12 RK_FUNC_1 &pcfg_pull_default>, /* mac_md */ | |
673 | <2 25 RK_FUNC_1 &pcfg_pull_default>; /* mac_mdclk */ | |
674 | }; | |
675 | }; | |
676 | ||
faea098e XZ |
677 | i2c0 { |
678 | i2c0_xfer: i2c0-xfer { | |
679 | rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>, | |
680 | <0 1 RK_FUNC_1 &pcfg_pull_none>; | |
681 | }; | |
682 | }; | |
683 | ||
684 | i2c1 { | |
685 | i2c1_xfer: i2c1-xfer { | |
686 | rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_none>, | |
687 | <0 3 RK_FUNC_1 &pcfg_pull_none>; | |
688 | }; | |
689 | }; | |
690 | ||
691 | i2c2 { | |
692 | i2c2_xfer: i2c2-xfer { | |
693 | rockchip,pins = <2 20 RK_FUNC_1 &pcfg_pull_none>, | |
694 | <2 21 RK_FUNC_1 &pcfg_pull_none>; | |
695 | }; | |
696 | }; | |
697 | ||
698 | i2s { | |
699 | i2s_bus: i2s-bus { | |
f4755332 CW |
700 | rockchip,pins = <1 0 RK_FUNC_1 &pcfg_pull_default>, |
701 | <1 1 RK_FUNC_1 &pcfg_pull_default>, | |
702 | <1 2 RK_FUNC_1 &pcfg_pull_default>, | |
703 | <1 3 RK_FUNC_1 &pcfg_pull_default>, | |
704 | <1 4 RK_FUNC_1 &pcfg_pull_default>, | |
705 | <1 5 RK_FUNC_1 &pcfg_pull_default>; | |
faea098e XZ |
706 | }; |
707 | }; | |
708 | ||
b7217cf1 CW |
709 | hdmi { |
710 | hdmi_ctl: hdmi-ctl { | |
711 | rockchip,pins = <1 8 RK_FUNC_1 &pcfg_pull_none>, | |
712 | <1 9 RK_FUNC_1 &pcfg_pull_none>, | |
713 | <1 10 RK_FUNC_1 &pcfg_pull_none>, | |
714 | <1 11 RK_FUNC_1 &pcfg_pull_none>; | |
715 | }; | |
716 | }; | |
717 | ||
faea098e XZ |
718 | uart0 { |
719 | uart0_xfer: uart0-xfer { | |
68556dd7 | 720 | rockchip,pins = <0 16 RK_FUNC_1 &pcfg_pull_default>, |
faea098e XZ |
721 | <0 17 RK_FUNC_1 &pcfg_pull_none>; |
722 | }; | |
723 | ||
724 | uart0_cts: uart0-cts { | |
68556dd7 | 725 | rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_default>; |
faea098e XZ |
726 | }; |
727 | ||
728 | uart0_rts: uart0-rts { | |
729 | rockchip,pins = <0 19 RK_FUNC_1 &pcfg_pull_none>; | |
730 | }; | |
731 | }; | |
732 | ||
733 | uart1 { | |
734 | uart1_xfer: uart1-xfer { | |
68556dd7 | 735 | rockchip,pins = <2 22 RK_FUNC_1 &pcfg_pull_default>, |
faea098e XZ |
736 | <2 23 RK_FUNC_1 &pcfg_pull_none>; |
737 | }; | |
738 | /* no rts / cts for uart1 */ | |
739 | }; | |
740 | ||
741 | uart2 { | |
742 | uart2_xfer: uart2-xfer { | |
68556dd7 | 743 | rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_default>, |
faea098e XZ |
744 | <1 19 RK_FUNC_2 &pcfg_pull_none>; |
745 | }; | |
746 | /* no rts / cts for uart2 */ | |
747 | }; | |
f629fcfa CW |
748 | |
749 | spi { | |
750 | spi_txd:spi-txd { | |
751 | rockchip,pins = <1 29 RK_FUNC_3 &pcfg_pull_default>; | |
752 | }; | |
753 | ||
754 | spi_rxd:spi-rxd { | |
755 | rockchip,pins = <1 28 RK_FUNC_3 &pcfg_pull_default>; | |
756 | }; | |
757 | ||
758 | spi_clk:spi-clk { | |
759 | rockchip,pins = <2 0 RK_FUNC_2 &pcfg_pull_default>; | |
760 | }; | |
761 | ||
762 | spi_cs0:spi-cs0 { | |
763 | rockchip,pins = <1 30 RK_FUNC_3 &pcfg_pull_default>; | |
764 | ||
765 | }; | |
766 | ||
767 | spi_cs1:spi-cs1 { | |
768 | rockchip,pins = <1 31 RK_FUNC_3 &pcfg_pull_default>; | |
769 | ||
770 | }; | |
771 | }; | |
faea098e XZ |
772 | }; |
773 | }; |