[deliverable/linux.git] / arch / arm / boot / dts / sun8i-h3.dtsi

/*
 * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 *  a) This file is free software; you can redistribute it and/or
 *     modify it under the terms of the GNU General Public License as
 *     published by the Free Software Foundation; either version 2 of the
 *     License, or (at your option) any later version.
 *
 *     This file is distributed in the hope that it will be useful,
 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *     GNU General Public License for more details.
 *
 * Or, alternatively,
 *
 *  b) Permission is hereby granted, free of charge, to any person
 *     obtaining a copy of this software and associated documentation
 *     files (the "Software"), to deal in the Software without
 *     restriction, including without limitation the rights to use,
 *     copy, modify, merge, publish, distribute, sublicense, and/or
 *     sell copies of the Software, and to permit persons to whom the
 *     Software is furnished to do so, subject to the following
 *     conditions:
 *
 *     The above copyright notice and this permission notice shall be
 *     included in all copies or substantial portions of the Software.
 *
 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 *     OTHER DEALINGS IN THE SOFTWARE.
 */

#include "skeleton.dtsi"

#include <dt-bindings/clock/sun8i-h3-ccu.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pinctrl/sun4i-a10.h>
#include <dt-bindings/reset/sun8i-h3-ccu.h>

/ {
	interrupt-parent = <&gic>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			compatible = "arm,cortex-a7";
			device_type = "cpu";
			reg = <0>;
		};

		cpu@1 {
			compatible = "arm,cortex-a7";
			device_type = "cpu";
			reg = <1>;
		};

		cpu@2 {
			compatible = "arm,cortex-a7";
			device_type = "cpu";
			reg = <2>;
		};

		cpu@3 {
			compatible = "arm,cortex-a7";
			device_type = "cpu";
			reg = <3>;
		};
	};

	timer {
		compatible = "arm,armv7-timer";
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
	};

	clocks {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		osc24M: osc24M_clk {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <24000000>;
			clock-output-names = "osc24M";
		};

		osc32k: osc32k_clk {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <32768>;
			clock-output-names = "osc32k";
		};

		apb0: apb0_clk {
			compatible = "fixed-factor-clock";
			#clock-cells = <0>;
			clock-div = <1>;
			clock-mult = <1>;
			clocks = <&osc24M>;
			clock-output-names = "apb0";
		};

		apb0_gates: clk@01f01428 {
			compatible = "allwinner,sun8i-h3-apb0-gates-clk",
				     "allwinner,sun4i-a10-gates-clk";
			reg = <0x01f01428 0x4>;
			#clock-cells = <1>;
			clocks = <&apb0>;
			clock-indices = <0>, <1>;
			clock-output-names = "apb0_pio", "apb0_ir";
		};

		ir_clk: ir_clk@01f01454 {
			compatible = "allwinner,sun4i-a10-mod0-clk";
			reg = <0x01f01454 0x4>;
			#clock-cells = <0>;
			clocks = <&osc32k>, <&osc24M>;
			clock-output-names = "ir";
		};
	};

	soc {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		dma: dma-controller@01c02000 {
			compatible = "allwinner,sun8i-h3-dma";
			reg = <0x01c02000 0x1000>;
			interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ccu CLK_BUS_DMA>;
			resets = <&ccu RST_BUS_DMA>;
			#dma-cells = <1>;
		};

		mmc0: mmc@01c0f000 {
			compatible = "allwinner,sun7i-a20-mmc";
			reg = <0x01c0f000 0x1000>;
			clocks = <&ccu CLK_BUS_MMC0>,
				 <&ccu CLK_MMC0>,
				 <&ccu CLK_MMC0_OUTPUT>,
				 <&ccu CLK_MMC0_SAMPLE>;
			clock-names = "ahb",
				      "mmc",
				      "output",
				      "sample";
			resets = <&ccu RST_BUS_MMC0>;
			reset-names = "ahb";
			interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		mmc1: mmc@01c10000 {
			compatible = "allwinner,sun7i-a20-mmc";
			reg = <0x01c10000 0x1000>;
			clocks = <&ccu CLK_BUS_MMC1>,
				 <&ccu CLK_MMC1>,
				 <&ccu CLK_MMC1_OUTPUT>,
				 <&ccu CLK_MMC1_SAMPLE>;
			clock-names = "ahb",
				      "mmc",
				      "output",
				      "sample";
			resets = <&ccu RST_BUS_MMC1>;
			reset-names = "ahb";
			interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		mmc2: mmc@01c11000 {
			compatible = "allwinner,sun7i-a20-mmc";
			reg = <0x01c11000 0x1000>;
			clocks = <&ccu CLK_BUS_MMC2>,
				 <&ccu CLK_MMC2>,
				 <&ccu CLK_MMC2_OUTPUT>,
				 <&ccu CLK_MMC2_SAMPLE>;
			clock-names = "ahb",
				      "mmc",
				      "output",
				      "sample";
			resets = <&ccu RST_BUS_MMC2>;
			reset-names = "ahb";
			interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		usbphy: phy@01c19400 {
			compatible = "allwinner,sun8i-h3-usb-phy";
			reg = <0x01c19400 0x2c>,
			      <0x01c1a800 0x4>,
			      <0x01c1b800 0x4>,
			      <0x01c1c800 0x4>,
			      <0x01c1d800 0x4>;
			reg-names = "phy_ctrl",
				    "pmu0",
				    "pmu1",
				    "pmu2",
				    "pmu3";
			clocks = <&ccu CLK_USB_PHY0>,
				 <&ccu CLK_USB_PHY1>,
				 <&ccu CLK_USB_PHY2>,
				 <&ccu CLK_USB_PHY3>;
			clock-names = "usb0_phy",
				      "usb1_phy",
				      "usb2_phy",
				      "usb3_phy";
			resets = <&ccu RST_USB_PHY0>,
				 <&ccu RST_USB_PHY1>,
				 <&ccu RST_USB_PHY2>,
				 <&ccu RST_USB_PHY3>;
			reset-names = "usb0_reset",
				      "usb1_reset",
				      "usb2_reset",
				      "usb3_reset";
			status = "disabled";
			#phy-cells = <1>;
		};

		ehci1: usb@01c1b000 {
			compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
			reg = <0x01c1b000 0x100>;
			interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ccu CLK_BUS_EHCI1>, <&ccu CLK_BUS_OHCI1>;
			resets = <&ccu RST_BUS_EHCI1>, <&ccu RST_BUS_OHCI1>;
			phys = <&usbphy 1>;
			phy-names = "usb";
			status = "disabled";
		};

		ohci1: usb@01c1b400 {
			compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
			reg = <0x01c1b400 0x100>;
			interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ccu CLK_BUS_EHCI1>, <&ccu CLK_BUS_OHCI1>,
				 <&ccu CLK_USB_OHCI1>;
			resets = <&ccu RST_BUS_EHCI1>, <&ccu RST_BUS_OHCI1>;
			phys = <&usbphy 1>;
			phy-names = "usb";
			status = "disabled";
		};

		ehci2: usb@01c1c000 {
			compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
			reg = <0x01c1c000 0x100>;
			interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ccu CLK_BUS_EHCI2>, <&ccu CLK_BUS_OHCI2>;
			resets = <&ccu RST_BUS_EHCI2>, <&ccu RST_BUS_OHCI2>;
			phys = <&usbphy 2>;
			phy-names = "usb";
			status = "disabled";
		};

		ohci2: usb@01c1c400 {
			compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
			reg = <0x01c1c400 0x100>;
			interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ccu CLK_BUS_EHCI2>, <&ccu CLK_BUS_OHCI2>,
				 <&ccu CLK_USB_OHCI2>;
			resets = <&ccu RST_BUS_EHCI2>, <&ccu RST_BUS_OHCI2>;
			phys = <&usbphy 2>;
			phy-names = "usb";
			status = "disabled";
		};

		ehci3: usb@01c1d000 {
			compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
			reg = <0x01c1d000 0x100>;
			interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ccu CLK_BUS_EHCI3>, <&ccu CLK_BUS_OHCI3>;
			resets = <&ccu RST_BUS_EHCI3>, <&ccu RST_BUS_OHCI3>;
			phys = <&usbphy 3>;
			phy-names = "usb";
			status = "disabled";
		};

		ohci3: usb@01c1d400 {
			compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
			reg = <0x01c1d400 0x100>;
			interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ccu CLK_BUS_EHCI3>, <&ccu CLK_BUS_OHCI3>,
				 <&ccu CLK_USB_OHCI3>;
			resets = <&ccu RST_BUS_EHCI3>, <&ccu RST_BUS_OHCI3>;
			phys = <&usbphy 3>;
			phy-names = "usb";
			status = "disabled";
		};

		ccu: clock@01c20000 {
			compatible = "allwinner,sun8i-h3-ccu";
			reg = <0x01c20000 0x400>;
			clocks = <&osc24M>, <&osc32k>;
			clock-names = "hosc", "losc";
			#clock-cells = <1>;
			#reset-cells = <1>;
		};

		pio: pinctrl@01c20800 {
			compatible = "allwinner,sun8i-h3-pinctrl";
			reg = <0x01c20800 0x400>;
			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ccu CLK_BUS_PIO>;
			gpio-controller;
			#gpio-cells = <3>;
			interrupt-controller;
			#interrupt-cells = <3>;

			mmc0_pins_a: mmc0@0 {
				allwinner,pins = "PF0", "PF1", "PF2", "PF3",
						 "PF4", "PF5";
				allwinner,function = "mmc0";
				allwinner,drive = <SUN4I_PINCTRL_30_MA>;
				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
			};

			mmc0_cd_pin: mmc0_cd_pin@0 {
				allwinner,pins = "PF6";
				allwinner,function = "gpio_in";
				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
				allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
			};

			mmc1_pins_a: mmc1@0 {
				allwinner,pins = "PG0", "PG1", "PG2", "PG3",
						 "PG4", "PG5";
				allwinner,function = "mmc1";
				allwinner,drive = <SUN4I_PINCTRL_30_MA>;
				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
			};

			mmc2_8bit_pins: mmc2_8bit {
				allwinner,pins = "PC5", "PC6", "PC8",
						 "PC9", "PC10", "PC11",
						 "PC12", "PC13", "PC14",
						 "PC15", "PC16";
				allwinner,function = "mmc2";
				allwinner,drive = <SUN4I_PINCTRL_30_MA>;
				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
			};

			uart0_pins_a: uart0@0 {
				allwinner,pins = "PA4", "PA5";
				allwinner,function = "uart0";
				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
			};

			uart1_pins_a: uart1@0 {
				allwinner,pins = "PG6", "PG7", "PG8", "PG9";
				allwinner,function = "uart1";
				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
			};
		};

		timer@01c20c00 {
			compatible = "allwinner,sun4i-a10-timer";
			reg = <0x01c20c00 0xa0>;
			interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&osc24M>;
		};

		wdt0: watchdog@01c20ca0 {
			compatible = "allwinner,sun6i-a31-wdt";
			reg = <0x01c20ca0 0x20>;
			interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
		};

		pwm: pwm@01c21400 {
			compatible = "allwinner,sun8i-h3-pwm";
			reg = <0x01c21400 0x8>;
			clocks = <&osc24M>;
			#pwm-cells = <3>;
			status = "disabled";
		};

		uart0: serial@01c28000 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c28000 0x400>;
			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&ccu CLK_BUS_UART0>;
			resets = <&ccu RST_BUS_UART0>;
			dmas = <&dma 6>, <&dma 6>;
			dma-names = "rx", "tx";
			status = "disabled";
		};

		uart1: serial@01c28400 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c28400 0x400>;
			interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&ccu CLK_BUS_UART1>;
			resets = <&ccu RST_BUS_UART1>;
			dmas = <&dma 7>, <&dma 7>;
			dma-names = "rx", "tx";
			status = "disabled";
		};

		uart2: serial@01c28800 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c28800 0x400>;
			interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&ccu CLK_BUS_UART2>;
			resets = <&ccu RST_BUS_UART2>;
			dmas = <&dma 8>, <&dma 8>;
			dma-names = "rx", "tx";
			status = "disabled";
		};

		uart3: serial@01c28c00 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c28c00 0x400>;
			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&ccu CLK_BUS_UART3>;
			resets = <&ccu RST_BUS_UART3>;
			dmas = <&dma 9>, <&dma 9>;
			dma-names = "rx", "tx";
			status = "disabled";
		};

		gic: interrupt-controller@01c81000 {
			compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
			reg = <0x01c81000 0x1000>,
			      <0x01c82000 0x1000>,
			      <0x01c84000 0x2000>,
			      <0x01c86000 0x2000>;
			interrupt-controller;
			#interrupt-cells = <3>;
			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
		};

		rtc: rtc@01f00000 {
			compatible = "allwinner,sun6i-a31-rtc";
			reg = <0x01f00000 0x54>;
			interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
		};

		apb0_reset: reset@01f014b0 {
			reg = <0x01f014b0 0x4>;
			compatible = "allwinner,sun6i-a31-clock-reset";
			#reset-cells = <1>;
		};

		ir: ir@01f02000 {
			compatible = "allwinner,sun5i-a13-ir";
			clocks = <&apb0_gates 1>, <&ir_clk>;
			clock-names = "apb", "ir";
			resets = <&apb0_reset 1>;
			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
			reg = <0x01f02000 0x40>;
			status = "disabled";
		};

		r_pio: pinctrl@01f02c00 {
			compatible = "allwinner,sun8i-h3-r-pinctrl";
			reg = <0x01f02c00 0x400>;
			interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&apb0_gates 0>;
			resets = <&apb0_reset 0>;
			gpio-controller;
			#gpio-cells = <3>;
			interrupt-controller;
			#interrupt-cells = <3>;

			ir_pins_a: ir@0 {
				allwinner,pins = "PL11";
				allwinner,function = "s_cir_rx";
				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
			};
		};
	};
};
Commit	Line	Data
318d93bc JK	1	/*
	2	* Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
	3	*
	4	* This file is dual-licensed: you can use it either under the terms
	5	* of the GPL or the X11 license, at your option. Note that this dual
	6	* licensing only applies to this file, and not this project as a
	7	* whole.
	8	*
	9	* a) This file is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU General Public License as
	11	* published by the Free Software Foundation; either version 2 of the
	12	* License, or (at your option) any later version.
	13	*
	14	* This file is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* Or, alternatively,
	20	*
	21	* b) Permission is hereby granted, free of charge, to any person
	22	* obtaining a copy of this software and associated documentation
	23	* files (the "Software"), to deal in the Software without
	24	* restriction, including without limitation the rights to use,
	25	* copy, modify, merge, publish, distribute, sublicense, and/or
	26	* sell copies of the Software, and to permit persons to whom the
	27	* Software is furnished to do so, subject to the following
	28	* conditions:
	29	*
	30	* The above copyright notice and this permission notice shall be
	31	* included in all copies or substantial portions of the Software.
	32	*
	33	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	34	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
	35	* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	36	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
	37	* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
	38	* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	39	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	40	* OTHER DEALINGS IN THE SOFTWARE.
	41	*/
	42
	43	#include "skeleton.dtsi"
	44
f38f5199	45	#include <dt-bindings/clock/sun8i-h3-ccu.h>
318d93bc JK	46	#include <dt-bindings/interrupt-controller/arm-gic.h>
318d93bc JK	47	#include <dt-bindings/pinctrl/sun4i-a10.h>
f38f5199	48	#include <dt-bindings/reset/sun8i-h3-ccu.h>
318d93bc JK	49
	50	/ {
	51	interrupt-parent = <&gic>;
	52
	53	cpus {
	54	#address-cells = <1>;
	55	#size-cells = <0>;
	56
	57	cpu@0 {
	58	compatible = "arm,cortex-a7";
	59	device_type = "cpu";
	60	reg = <0>;
	61	};
	62
	63	cpu@1 {
	64	compatible = "arm,cortex-a7";
	65	device_type = "cpu";
	66	reg = <1>;
	67	};
	68
	69	cpu@2 {
	70	compatible = "arm,cortex-a7";
	71	device_type = "cpu";
	72	reg = <2>;
	73	};
	74
	75	cpu@3 {
	76	compatible = "arm,cortex-a7";
	77	device_type = "cpu";
	78	reg = <3>;
	79	};
	80	};
	81
	82	timer {
	83	compatible = "arm,armv7-timer";
	84	interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
	85	<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
	86	<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
	87	<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>;
	88	};
	89
	90	clocks {
	91	#address-cells = <1>;
	92	#size-cells = <1>;
	93	ranges;
	94
	95	osc24M: osc24M_clk {
	96	#clock-cells = <0>;
	97	compatible = "fixed-clock";
	98	clock-frequency = <24000000>;
	99	clock-output-names = "osc24M";
	100	};
	101
	102	osc32k: osc32k_clk {
	103	#clock-cells = <0>;
	104	compatible = "fixed-clock";
	105	clock-frequency = <32768>;
	106	clock-output-names = "osc32k";
	107	};
	108
09787294 KA	109	apb0: apb0_clk {
	110	compatible = "fixed-factor-clock";
	111	#clock-cells = <0>;
	112	clock-div = <1>;
	113	clock-mult = <1>;
	114	clocks = <&osc24M>;
	115	clock-output-names = "apb0";
	116	};
	117
	118	apb0_gates: clk@01f01428 {
	119	compatible = "allwinner,sun8i-h3-apb0-gates-clk",
	120	"allwinner,sun4i-a10-gates-clk";
	121	reg = <0x01f01428 0x4>;
	122	#clock-cells = <1>;
	123	clocks = <&apb0>;
	124	clock-indices = <0>, <1>;
	125	clock-output-names = "apb0_pio", "apb0_ir";
	126	};
fe0a8ea1 HG	127
	128	ir_clk: ir_clk@01f01454 {
	129	compatible = "allwinner,sun4i-a10-mod0-clk";
	130	reg = <0x01f01454 0x4>;
	131	#clock-cells = <0>;
	132	clocks = <&osc32k>, <&osc24M>;
	133	clock-output-names = "ir";
	134	};
318d93bc JK	135	};
	136
	137	soc {
	138	compatible = "simple-bus";
	139	#address-cells = <1>;
	140	#size-cells = <1>;
	141	ranges;
	142
	143	dma: dma-controller@01c02000 {
	144	compatible = "allwinner,sun8i-h3-dma";
	145	reg = <0x01c02000 0x1000>;
	146	interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
f38f5199 MR	147	clocks = <&ccu CLK_BUS_DMA>;
f38f5199 MR	148	resets = <&ccu RST_BUS_DMA>;
318d93bc JK	149	#dma-cells = <1>;
	150	};
	151
	152	mmc0: mmc@01c0f000 {
32ecb385	153	compatible = "allwinner,sun7i-a20-mmc";
318d93bc	154	reg = <0x01c0f000 0x1000>;
f38f5199 MR	155	clocks = <&ccu CLK_BUS_MMC0>,
	156	<&ccu CLK_MMC0>,
	157	<&ccu CLK_MMC0_OUTPUT>,
	158	<&ccu CLK_MMC0_SAMPLE>;
318d93bc JK	159	clock-names = "ahb",
	160	"mmc",
	161	"output",
	162	"sample";
f38f5199	163	resets = <&ccu RST_BUS_MMC0>;
318d93bc JK	164	reset-names = "ahb";
	165	interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
	166	status = "disabled";
	167	#address-cells = <1>;
	168	#size-cells = <0>;
	169	};
	170
	171	mmc1: mmc@01c10000 {
32ecb385	172	compatible = "allwinner,sun7i-a20-mmc";
318d93bc	173	reg = <0x01c10000 0x1000>;
f38f5199 MR	174	clocks = <&ccu CLK_BUS_MMC1>,
	175	<&ccu CLK_MMC1>,
	176	<&ccu CLK_MMC1_OUTPUT>,
	177	<&ccu CLK_MMC1_SAMPLE>;
318d93bc JK	178	clock-names = "ahb",
	179	"mmc",
	180	"output",
	181	"sample";
f38f5199	182	resets = <&ccu RST_BUS_MMC1>;
318d93bc JK	183	reset-names = "ahb";
	184	interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
	185	status = "disabled";
	186	#address-cells = <1>;
	187	#size-cells = <0>;
	188	};
	189
	190	mmc2: mmc@01c11000 {
32ecb385	191	compatible = "allwinner,sun7i-a20-mmc";
318d93bc	192	reg = <0x01c11000 0x1000>;
f38f5199 MR	193	clocks = <&ccu CLK_BUS_MMC2>,
	194	<&ccu CLK_MMC2>,
	195	<&ccu CLK_MMC2_OUTPUT>,
	196	<&ccu CLK_MMC2_SAMPLE>;
318d93bc JK	197	clock-names = "ahb",
	198	"mmc",
	199	"output",
	200	"sample";
f38f5199	201	resets = <&ccu RST_BUS_MMC2>;
318d93bc JK	202	reset-names = "ahb";
	203	interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
	204	status = "disabled";
	205	#address-cells = <1>;
	206	#size-cells = <0>;
	207	};
	208
4cf9654e RH	209	usbphy: phy@01c19400 {
	210	compatible = "allwinner,sun8i-h3-usb-phy";
	211	reg = <0x01c19400 0x2c>,
	212	<0x01c1a800 0x4>,
	213	<0x01c1b800 0x4>,
	214	<0x01c1c800 0x4>,
	215	<0x01c1d800 0x4>;
	216	reg-names = "phy_ctrl",
	217	"pmu0",
	218	"pmu1",
	219	"pmu2",
	220	"pmu3";
f38f5199 MR	221	clocks = <&ccu CLK_USB_PHY0>,
	222	<&ccu CLK_USB_PHY1>,
	223	<&ccu CLK_USB_PHY2>,
	224	<&ccu CLK_USB_PHY3>;
4cf9654e RH	225	clock-names = "usb0_phy",
	226	"usb1_phy",
	227	"usb2_phy",
	228	"usb3_phy";
f38f5199 MR	229	resets = <&ccu RST_USB_PHY0>,
	230	<&ccu RST_USB_PHY1>,
	231	<&ccu RST_USB_PHY2>,
	232	<&ccu RST_USB_PHY3>;
4cf9654e RH	233	reset-names = "usb0_reset",
	234	"usb1_reset",
	235	"usb2_reset",
	236	"usb3_reset";
	237	status = "disabled";
	238	#phy-cells = <1>;
	239	};
	240
	241	ehci1: usb@01c1b000 {
	242	compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
	243	reg = <0x01c1b000 0x100>;
	244	interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
f38f5199 MR	245	clocks = <&ccu CLK_BUS_EHCI1>, <&ccu CLK_BUS_OHCI1>;
f38f5199 MR	246	resets = <&ccu RST_BUS_EHCI1>, <&ccu RST_BUS_OHCI1>;
4cf9654e RH	247	phys = <&usbphy 1>;
	248	phy-names = "usb";
	249	status = "disabled";
	250	};
	251
	252	ohci1: usb@01c1b400 {
	253	compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
	254	reg = <0x01c1b400 0x100>;
	255	interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
f38f5199 MR	256	clocks = <&ccu CLK_BUS_EHCI1>, <&ccu CLK_BUS_OHCI1>,
	257	<&ccu CLK_USB_OHCI1>;
	258	resets = <&ccu RST_BUS_EHCI1>, <&ccu RST_BUS_OHCI1>;
4cf9654e RH	259	phys = <&usbphy 1>;
	260	phy-names = "usb";
	261	status = "disabled";
	262	};
	263
	264	ehci2: usb@01c1c000 {
	265	compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
	266	reg = <0x01c1c000 0x100>;
	267	interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
f38f5199 MR	268	clocks = <&ccu CLK_BUS_EHCI2>, <&ccu CLK_BUS_OHCI2>;
f38f5199 MR	269	resets = <&ccu RST_BUS_EHCI2>, <&ccu RST_BUS_OHCI2>;
4cf9654e RH	270	phys = <&usbphy 2>;
	271	phy-names = "usb";
	272	status = "disabled";
	273	};
	274
	275	ohci2: usb@01c1c400 {
	276	compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
	277	reg = <0x01c1c400 0x100>;
	278	interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
f38f5199 MR	279	clocks = <&ccu CLK_BUS_EHCI2>, <&ccu CLK_BUS_OHCI2>,
	280	<&ccu CLK_USB_OHCI2>;
	281	resets = <&ccu RST_BUS_EHCI2>, <&ccu RST_BUS_OHCI2>;
4cf9654e RH	282	phys = <&usbphy 2>;
	283	phy-names = "usb";
	284	status = "disabled";
	285	};
	286
	287	ehci3: usb@01c1d000 {
	288	compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
	289	reg = <0x01c1d000 0x100>;
	290	interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
f38f5199 MR	291	clocks = <&ccu CLK_BUS_EHCI3>, <&ccu CLK_BUS_OHCI3>;
f38f5199 MR	292	resets = <&ccu RST_BUS_EHCI3>, <&ccu RST_BUS_OHCI3>;
4cf9654e RH	293	phys = <&usbphy 3>;
	294	phy-names = "usb";
	295	status = "disabled";
	296	};
	297
	298	ohci3: usb@01c1d400 {
	299	compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
	300	reg = <0x01c1d400 0x100>;
	301	interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
f38f5199 MR	302	clocks = <&ccu CLK_BUS_EHCI3>, <&ccu CLK_BUS_OHCI3>,
	303	<&ccu CLK_USB_OHCI3>;
	304	resets = <&ccu RST_BUS_EHCI3>, <&ccu RST_BUS_OHCI3>;
4cf9654e RH	305	phys = <&usbphy 3>;
	306	phy-names = "usb";
	307	status = "disabled";
	308	};
	309
f38f5199 MR	310	ccu: clock@01c20000 {
	311	compatible = "allwinner,sun8i-h3-ccu";
	312	reg = <0x01c20000 0x400>;
	313	clocks = <&osc24M>, <&osc32k>;
	314	clock-names = "hosc", "losc";
	315	#clock-cells = <1>;
	316	#reset-cells = <1>;
	317	};
	318
318d93bc JK	319	pio: pinctrl@01c20800 {
	320	compatible = "allwinner,sun8i-h3-pinctrl";
	321	reg = <0x01c20800 0x400>;
	322	interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
	323	<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
f38f5199	324	clocks = <&ccu CLK_BUS_PIO>;
318d93bc JK	325	gpio-controller;
	326	#gpio-cells = <3>;
	327	interrupt-controller;
5bcaf95c	328	#interrupt-cells = <3>;
318d93bc	329
318d93bc JK	330	mmc0_pins_a: mmc0@0 {
	331	allwinner,pins = "PF0", "PF1", "PF2", "PF3",
	332	"PF4", "PF5";
	333	allwinner,function = "mmc0";
	334	allwinner,drive = <SUN4I_PINCTRL_30_MA>;
	335	allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
	336	};
	337
	338	mmc0_cd_pin: mmc0_cd_pin@0 {
	339	allwinner,pins = "PF6";
	340	allwinner,function = "gpio_in";
	341	allwinner,drive = <SUN4I_PINCTRL_10_MA>;
	342	allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
	343	};
	344
	345	mmc1_pins_a: mmc1@0 {
	346	allwinner,pins = "PG0", "PG1", "PG2", "PG3",
	347	"PG4", "PG5";
	348	allwinner,function = "mmc1";
	349	allwinner,drive = <SUN4I_PINCTRL_30_MA>;
	350	allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
	351	};
9461faf2 HG	352
	353	mmc2_8bit_pins: mmc2_8bit {
	354	allwinner,pins = "PC5", "PC6", "PC8",
	355	"PC9", "PC10", "PC11",
	356	"PC12", "PC13", "PC14",
	357	"PC15", "PC16";
	358	allwinner,function = "mmc2";
	359	allwinner,drive = <SUN4I_PINCTRL_30_MA>;
	360	allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
	361	};
2bcb2b1b CYT	362
	363	uart0_pins_a: uart0@0 {
	364	allwinner,pins = "PA4", "PA5";
	365	allwinner,function = "uart0";
	366	allwinner,drive = <SUN4I_PINCTRL_10_MA>;
	367	allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
	368	};
966c11a3 CYT	369
	370	uart1_pins_a: uart1@0 {
	371	allwinner,pins = "PG6", "PG7", "PG8", "PG9";
	372	allwinner,function = "uart1";
	373	allwinner,drive = <SUN4I_PINCTRL_10_MA>;
	374	allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
	375	};
318d93bc JK	376	};
318d93bc JK	377
318d93bc JK	378	timer@01c20c00 {
	379	compatible = "allwinner,sun4i-a10-timer";
	380	reg = <0x01c20c00 0xa0>;
	381	interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
	382	<GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
	383	clocks = <&osc24M>;
	384	};
	385
	386	wdt0: watchdog@01c20ca0 {
	387	compatible = "allwinner,sun6i-a31-wdt";
	388	reg = <0x01c20ca0 0x20>;
	389	interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
	390	};
	391
a37b7a5a MK	392	pwm: pwm@01c21400 {
	393	compatible = "allwinner,sun8i-h3-pwm";
	394	reg = <0x01c21400 0x8>;
	395	clocks = <&osc24M>;
	396	#pwm-cells = <3>;
	397	status = "disabled";
	398	};
	399
318d93bc JK	400	uart0: serial@01c28000 {
	401	compatible = "snps,dw-apb-uart";
	402	reg = <0x01c28000 0x400>;
	403	interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
	404	reg-shift = <2>;
	405	reg-io-width = <4>;
f38f5199 MR	406	clocks = <&ccu CLK_BUS_UART0>;
f38f5199 MR	407	resets = <&ccu RST_BUS_UART0>;
318d93bc JK	408	dmas = <&dma 6>, <&dma 6>;
	409	dma-names = "rx", "tx";
	410	status = "disabled";
	411	};
	412
	413	uart1: serial@01c28400 {
	414	compatible = "snps,dw-apb-uart";
	415	reg = <0x01c28400 0x400>;
	416	interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
	417	reg-shift = <2>;
	418	reg-io-width = <4>;
f38f5199 MR	419	clocks = <&ccu CLK_BUS_UART1>;
f38f5199 MR	420	resets = <&ccu RST_BUS_UART1>;
318d93bc JK	421	dmas = <&dma 7>, <&dma 7>;
	422	dma-names = "rx", "tx";
	423	status = "disabled";
	424	};
	425
	426	uart2: serial@01c28800 {
	427	compatible = "snps,dw-apb-uart";
	428	reg = <0x01c28800 0x400>;
	429	interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
	430	reg-shift = <2>;
	431	reg-io-width = <4>;
f38f5199 MR	432	clocks = <&ccu CLK_BUS_UART2>;
f38f5199 MR	433	resets = <&ccu RST_BUS_UART2>;
318d93bc JK	434	dmas = <&dma 8>, <&dma 8>;
	435	dma-names = "rx", "tx";
	436	status = "disabled";
	437	};
	438
	439	uart3: serial@01c28c00 {
	440	compatible = "snps,dw-apb-uart";
	441	reg = <0x01c28c00 0x400>;
	442	interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
	443	reg-shift = <2>;
	444	reg-io-width = <4>;
f38f5199 MR	445	clocks = <&ccu CLK_BUS_UART3>;
f38f5199 MR	446	resets = <&ccu RST_BUS_UART3>;
318d93bc JK	447	dmas = <&dma 9>, <&dma 9>;
	448	dma-names = "rx", "tx";
	449	status = "disabled";
	450	};
	451
	452	gic: interrupt-controller@01c81000 {
	453	compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
	454	reg = <0x01c81000 0x1000>,
	455	<0x01c82000 0x1000>,
	456	<0x01c84000 0x2000>,
	457	<0x01c86000 0x2000>;
	458	interrupt-controller;
	459	#interrupt-cells = <3>;
	460	interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_HIGH)>;
	461	};
	462
	463	rtc: rtc@01f00000 {
	464	compatible = "allwinner,sun6i-a31-rtc";
	465	reg = <0x01f00000 0x54>;
	466	interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
	467	<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
	468	};
09787294 KA	469
	470	apb0_reset: reset@01f014b0 {
	471	reg = <0x01f014b0 0x4>;
	472	compatible = "allwinner,sun6i-a31-clock-reset";
	473	#reset-cells = <1>;
	474	};
93385367	475
fe0a8ea1 HG	476	ir: ir@01f02000 {
	477	compatible = "allwinner,sun5i-a13-ir";
	478	clocks = <&apb0_gates 1>, <&ir_clk>;
	479	clock-names = "apb", "ir";
	480	resets = <&apb0_reset 1>;
	481	interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
	482	reg = <0x01f02000 0x40>;
	483	status = "disabled";
	484	};
	485
93385367 KA	486	r_pio: pinctrl@01f02c00 {
	487	compatible = "allwinner,sun8i-h3-r-pinctrl";
	488	reg = <0x01f02c00 0x400>;
	489	interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
	490	clocks = <&apb0_gates 0>;
	491	resets = <&apb0_reset 0>;
	492	gpio-controller;
	493	#gpio-cells = <3>;
	494	interrupt-controller;
	495	#interrupt-cells = <3>;
fe0a8ea1 HG	496
	497	ir_pins_a: ir@0 {
	498	allwinner,pins = "PL11";
	499	allwinner,function = "s_cir_rx";
	500	allwinner,drive = <SUN4I_PINCTRL_10_MA>;
	501	allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
	502	};
93385367	503	};
318d93bc JK	504	};
318d93bc JK	505	};