[deliverable/linux.git] / arch / arm / include / asm / cachetype.h

#ifndef __ASM_ARM_CACHETYPE_H
#define __ASM_ARM_CACHETYPE_H

#define CACHEID_VIVT			(1 << 0)
#define CACHEID_VIPT_NONALIASING	(1 << 1)
#define CACHEID_VIPT_ALIASING		(1 << 2)
#define CACHEID_VIPT			(CACHEID_VIPT_ALIASING|CACHEID_VIPT_NONALIASING)
#define CACHEID_ASID_TAGGED		(1 << 3)
#define CACHEID_VIPT_I_ALIASING		(1 << 4)
#define CACHEID_PIPT			(1 << 5)

extern unsigned int cacheid;

#define cache_is_vivt()			cacheid_is(CACHEID_VIVT)
#define cache_is_vipt()			cacheid_is(CACHEID_VIPT)
#define cache_is_vipt_nonaliasing()	cacheid_is(CACHEID_VIPT_NONALIASING)
#define cache_is_vipt_aliasing()	cacheid_is(CACHEID_VIPT_ALIASING)
#define icache_is_vivt_asid_tagged()	cacheid_is(CACHEID_ASID_TAGGED)
#define icache_is_vipt_aliasing()	cacheid_is(CACHEID_VIPT_I_ALIASING)
#define icache_is_pipt()		cacheid_is(CACHEID_PIPT)

/*
 * __LINUX_ARM_ARCH__ is the minimum supported CPU architecture
 * Mask out support which will never be present on newer CPUs.
 * - v6+ is never VIVT
 * - v7+ VIPT never aliases on D-side
 */
#if __LINUX_ARM_ARCH__ >= 7
#define __CACHEID_ARCH_MIN	(CACHEID_VIPT_NONALIASING |\
				 CACHEID_ASID_TAGGED |\
				 CACHEID_VIPT_I_ALIASING |\
				 CACHEID_PIPT)
#elif __LINUX_ARM_ARCH__ >= 6
#define	__CACHEID_ARCH_MIN	(~CACHEID_VIVT)
#else
#define __CACHEID_ARCH_MIN	(~0)
#endif

/*
 * Mask out support which isn't configured
 */
#if defined(CONFIG_CPU_CACHE_VIVT) && !defined(CONFIG_CPU_CACHE_VIPT)
#define __CACHEID_ALWAYS	(CACHEID_VIVT)
#define __CACHEID_NEVER		(~CACHEID_VIVT)
#elif !defined(CONFIG_CPU_CACHE_VIVT) && defined(CONFIG_CPU_CACHE_VIPT)
#define __CACHEID_ALWAYS	(0)
#define __CACHEID_NEVER		(CACHEID_VIVT)
#else
#define __CACHEID_ALWAYS	(0)
#define __CACHEID_NEVER		(0)
#endif

static inline unsigned int __attribute__((pure)) cacheid_is(unsigned int mask)
{
	return (__CACHEID_ALWAYS & mask) |
	       (~__CACHEID_NEVER & __CACHEID_ARCH_MIN & mask & cacheid);
}

#define CSSELR_ICACHE	1
#define CSSELR_DCACHE	0

#define CSSELR_L1	(0 << 1)
#define CSSELR_L2	(1 << 1)
#define CSSELR_L3	(2 << 1)
#define CSSELR_L4	(3 << 1)
#define CSSELR_L5	(4 << 1)
#define CSSELR_L6	(5 << 1)
#define CSSELR_L7	(6 << 1)

#ifndef CONFIG_CPU_V7M
static inline void set_csselr(unsigned int cache_selector)
{
	asm volatile("mcr p15, 2, %0, c0, c0, 0" : : "r" (cache_selector));
}

static inline unsigned int read_ccsidr(void)
{
	unsigned int val;

	asm volatile("mrc p15, 1, %0, c0, c0, 0" : "=r" (val));
	return val;
}
#else /* CONFIG_CPU_V7M */
#include <linux/io.h>
#include "asm/v7m.h"

static inline void set_csselr(unsigned int cache_selector)
{
	writel(cache_selector, BASEADDR_V7M_SCB + V7M_SCB_CTR);
}

static inline unsigned int read_ccsidr(void)
{
	return readl(BASEADDR_V7M_SCB + V7M_SCB_CCSIDR);
}
#endif

#endif
Commit	Line	Data
46097c7d RK	1	#ifndef __ASM_ARM_CACHETYPE_H
	2	#define __ASM_ARM_CACHETYPE_H
	3
c0e95878 RK	4	#define CACHEID_VIVT (1 << 0)
	5	#define CACHEID_VIPT_NONALIASING (1 << 1)
	6	#define CACHEID_VIPT_ALIASING (1 << 2)
	7	#define CACHEID_VIPT (CACHEID_VIPT_ALIASING\|CACHEID_VIPT_NONALIASING)
	8	#define CACHEID_ASID_TAGGED (1 << 3)
8925ec4c	9	#define CACHEID_VIPT_I_ALIASING (1 << 4)
7f94e9cc	10	#define CACHEID_PIPT (1 << 5)
46097c7d	11
c0e95878	12	extern unsigned int cacheid;
46097c7d	13
c0e95878 RK	14	#define cache_is_vivt() cacheid_is(CACHEID_VIVT)
	15	#define cache_is_vipt() cacheid_is(CACHEID_VIPT)
	16	#define cache_is_vipt_nonaliasing() cacheid_is(CACHEID_VIPT_NONALIASING)
	17	#define cache_is_vipt_aliasing() cacheid_is(CACHEID_VIPT_ALIASING)
	18	#define icache_is_vivt_asid_tagged() cacheid_is(CACHEID_ASID_TAGGED)
8925ec4c	19	#define icache_is_vipt_aliasing() cacheid_is(CACHEID_VIPT_I_ALIASING)
7f94e9cc	20	#define icache_is_pipt() cacheid_is(CACHEID_PIPT)
46097c7d	21
46097c7d	22	/*
c0e95878 RK	23	* __LINUX_ARM_ARCH__ is the minimum supported CPU architecture
	24	* Mask out support which will never be present on newer CPUs.
	25	* - v6+ is never VIVT
8925ec4c	26	* - v7+ VIPT never aliases on D-side
46097c7d	27	*/
c0e95878	28	#if __LINUX_ARM_ARCH__ >= 7
8925ec4c WD	29	#define __CACHEID_ARCH_MIN (CACHEID_VIPT_NONALIASING \|\
8925ec4c WD	30	CACHEID_ASID_TAGGED \|\
7f94e9cc WD	31	CACHEID_VIPT_I_ALIASING \|\
7f94e9cc WD	32	CACHEID_PIPT)
c0e95878 RK	33	#elif __LINUX_ARM_ARCH__ >= 6
	34	#define __CACHEID_ARCH_MIN (~CACHEID_VIVT)
	35	#else
	36	#define __CACHEID_ARCH_MIN (~0)
	37	#endif
46097c7d	38
46097c7d	39	/*
c0e95878	40	* Mask out support which isn't configured
46097c7d	41	*/
c0e95878 RK	42	#if defined(CONFIG_CPU_CACHE_VIVT) && !defined(CONFIG_CPU_CACHE_VIPT)
	43	#define __CACHEID_ALWAYS (CACHEID_VIVT)
	44	#define __CACHEID_NEVER (~CACHEID_VIVT)
	45	#elif !defined(CONFIG_CPU_CACHE_VIVT) && defined(CONFIG_CPU_CACHE_VIPT)
	46	#define __CACHEID_ALWAYS (0)
	47	#define __CACHEID_NEVER (CACHEID_VIVT)
46097c7d	48	#else
c0e95878 RK	49	#define __CACHEID_ALWAYS (0)
c0e95878 RK	50	#define __CACHEID_NEVER (0)
46097c7d RK	51	#endif
46097c7d RK	52
c0e95878 RK	53	static inline unsigned int __attribute__((pure)) cacheid_is(unsigned int mask)
	54	{
	55	return (__CACHEID_ALWAYS & mask) \|
	56	(~__CACHEID_NEVER & __CACHEID_ARCH_MIN & mask & cacheid);
	57	}
	58
26150aa9 JA	59	#define CSSELR_ICACHE 1
	60	#define CSSELR_DCACHE 0
	61
	62	#define CSSELR_L1 (0 << 1)
	63	#define CSSELR_L2 (1 << 1)
	64	#define CSSELR_L3 (2 << 1)
	65	#define CSSELR_L4 (3 << 1)
	66	#define CSSELR_L5 (4 << 1)
	67	#define CSSELR_L6 (5 << 1)
	68	#define CSSELR_L7 (6 << 1)
	69
f5a5c89e	70	#ifndef CONFIG_CPU_V7M
26150aa9 JA	71	static inline void set_csselr(unsigned int cache_selector)
	72	{
	73	asm volatile("mcr p15, 2, %0, c0, c0, 0" : : "r" (cache_selector));
	74	}
	75
	76	static inline unsigned int read_ccsidr(void)
	77	{
	78	unsigned int val;
	79
	80	asm volatile("mrc p15, 1, %0, c0, c0, 0" : "=r" (val));
	81	return val;
	82	}
f5a5c89e JA	83	#else /* CONFIG_CPU_V7M */
	84	#include <linux/io.h>
	85	#include "asm/v7m.h"
	86
	87	static inline void set_csselr(unsigned int cache_selector)
	88	{
	89	writel(cache_selector, BASEADDR_V7M_SCB + V7M_SCB_CTR);
	90	}
	91
	92	static inline unsigned int read_ccsidr(void)
	93	{
	94	return readl(BASEADDR_V7M_SCB + V7M_SCB_CCSIDR);
	95	}
	96	#endif
26150aa9	97
46097c7d	98	#endif