[deliverable/linux.git] / arch / arm / include / asm / cputype.h

#ifndef __ASM_ARM_CPUTYPE_H
#define __ASM_ARM_CPUTYPE_H

#include <linux/stringify.h>
#include <linux/kernel.h>

#define CPUID_ID	0
#define CPUID_CACHETYPE	1
#define CPUID_TCM	2
#define CPUID_TLBTYPE	3
#define CPUID_MPUIR	4
#define CPUID_MPIDR	5
#define CPUID_REVIDR	6

#ifdef CONFIG_CPU_V7M
#define CPUID_EXT_PFR0	0x40
#define CPUID_EXT_PFR1	0x44
#define CPUID_EXT_DFR0	0x48
#define CPUID_EXT_AFR0	0x4c
#define CPUID_EXT_MMFR0	0x50
#define CPUID_EXT_MMFR1	0x54
#define CPUID_EXT_MMFR2	0x58
#define CPUID_EXT_MMFR3	0x5c
#define CPUID_EXT_ISAR0	0x60
#define CPUID_EXT_ISAR1	0x64
#define CPUID_EXT_ISAR2	0x68
#define CPUID_EXT_ISAR3	0x6c
#define CPUID_EXT_ISAR4	0x70
#define CPUID_EXT_ISAR5	0x74
#else
#define CPUID_EXT_PFR0	"c1, 0"
#define CPUID_EXT_PFR1	"c1, 1"
#define CPUID_EXT_DFR0	"c1, 2"
#define CPUID_EXT_AFR0	"c1, 3"
#define CPUID_EXT_MMFR0	"c1, 4"
#define CPUID_EXT_MMFR1	"c1, 5"
#define CPUID_EXT_MMFR2	"c1, 6"
#define CPUID_EXT_MMFR3	"c1, 7"
#define CPUID_EXT_ISAR0	"c2, 0"
#define CPUID_EXT_ISAR1	"c2, 1"
#define CPUID_EXT_ISAR2	"c2, 2"
#define CPUID_EXT_ISAR3	"c2, 3"
#define CPUID_EXT_ISAR4	"c2, 4"
#define CPUID_EXT_ISAR5	"c2, 5"
#endif

#define MPIDR_SMP_BITMASK (0x3 << 30)
#define MPIDR_SMP_VALUE (0x2 << 30)

#define MPIDR_MT_BITMASK (0x1 << 24)

#define MPIDR_HWID_BITMASK 0xFFFFFF

#define MPIDR_INVALID (~MPIDR_HWID_BITMASK)

#define MPIDR_LEVEL_BITS 8
#define MPIDR_LEVEL_MASK ((1 << MPIDR_LEVEL_BITS) - 1)

#define MPIDR_AFFINITY_LEVEL(mpidr, level) \
	((mpidr >> (MPIDR_LEVEL_BITS * level)) & MPIDR_LEVEL_MASK)

#define ARM_CPU_IMP_ARM			0x41
#define ARM_CPU_IMP_DEC			0x44
#define ARM_CPU_IMP_INTEL		0x69

/* ARM implemented processors */
#define ARM_CPU_PART_ARM1136		0x4100b360
#define ARM_CPU_PART_ARM1156		0x4100b560
#define ARM_CPU_PART_ARM1176		0x4100b760
#define ARM_CPU_PART_ARM11MPCORE	0x4100b020
#define ARM_CPU_PART_CORTEX_A8		0x4100c080
#define ARM_CPU_PART_CORTEX_A9		0x4100c090
#define ARM_CPU_PART_CORTEX_A5		0x4100c050
#define ARM_CPU_PART_CORTEX_A7		0x4100c070
#define ARM_CPU_PART_CORTEX_A12		0x4100c0d0
#define ARM_CPU_PART_CORTEX_A17		0x4100c0e0
#define ARM_CPU_PART_CORTEX_A15		0x4100c0f0
#define ARM_CPU_PART_MASK		0xff00fff0

/* DEC implemented cores */
#define ARM_CPU_PART_SA1100		0x4400a110

/* Intel implemented cores */
#define ARM_CPU_PART_SA1110		0x6900b110
#define ARM_CPU_REV_SA1110_A0		0
#define ARM_CPU_REV_SA1110_B0		4
#define ARM_CPU_REV_SA1110_B1		5
#define ARM_CPU_REV_SA1110_B2		6
#define ARM_CPU_REV_SA1110_B4		8

#define ARM_CPU_XSCALE_ARCH_MASK	0xe000
#define ARM_CPU_XSCALE_ARCH_V1		0x2000
#define ARM_CPU_XSCALE_ARCH_V2		0x4000
#define ARM_CPU_XSCALE_ARCH_V3		0x6000

extern unsigned int processor_id;

#ifdef CONFIG_CPU_CP15
#define read_cpuid(reg)							\
	({								\
		unsigned int __val;					\
		asm("mrc	p15, 0, %0, c0, c0, " __stringify(reg)	\
		    : "=r" (__val)					\
		    :							\
		    : "cc");						\
		__val;							\
	})

/*
 * The memory clobber prevents gcc 4.5 from reordering the mrc before
 * any is_smp() tests, which can cause undefined instruction aborts on
 * ARM1136 r0 due to the missing extended CP15 registers.
 */
#define read_cpuid_ext(ext_reg)						\
	({								\
		unsigned int __val;					\
		asm("mrc	p15, 0, %0, c0, " ext_reg		\
		    : "=r" (__val)					\
		    :							\
		    : "memory");					\
		__val;							\
	})

#elif defined(CONFIG_CPU_V7M)

#include <asm/io.h>
#include <asm/v7m.h>

#define read_cpuid(reg)							\
	({								\
		WARN_ON_ONCE(1);					\
		0;							\
	})

static inline unsigned int __attribute_const__ read_cpuid_ext(unsigned offset)
{
	return readl(BASEADDR_V7M_SCB + offset);
}

#else /* ifdef CONFIG_CPU_CP15 / elif defined (CONFIG_CPU_V7M) */

/*
 * read_cpuid and read_cpuid_ext should only ever be called on machines that
 * have cp15 so warn on other usages.
 */
#define read_cpuid(reg)							\
	({								\
		WARN_ON_ONCE(1);					\
		0;							\
	})

#define read_cpuid_ext(reg) read_cpuid(reg)

#endif /* ifdef CONFIG_CPU_CP15 / else */

#ifdef CONFIG_CPU_CP15
/*
 * The CPU ID never changes at run time, so we might as well tell the
 * compiler that it's constant.  Use this function to read the CPU ID
 * rather than directly reading processor_id or read_cpuid() directly.
 */
static inline unsigned int __attribute_const__ read_cpuid_id(void)
{
	return read_cpuid(CPUID_ID);
}

static inline unsigned int __attribute_const__ read_cpuid_cachetype(void)
{
	return read_cpuid(CPUID_CACHETYPE);
}

#elif defined(CONFIG_CPU_V7M)

static inline unsigned int __attribute_const__ read_cpuid_id(void)
{
	return readl(BASEADDR_V7M_SCB + V7M_SCB_CPUID);
}

static inline unsigned int __attribute_const__ read_cpuid_cachetype(void)
{
	return readl(BASEADDR_V7M_SCB + V7M_SCB_CTR);
}

#else /* ifdef CONFIG_CPU_CP15 / elif defined(CONFIG_CPU_V7M) */

static inline unsigned int __attribute_const__ read_cpuid_id(void)
{
	return processor_id;
}

#endif /* ifdef CONFIG_CPU_CP15 / else */

static inline unsigned int __attribute_const__ read_cpuid_implementor(void)
{
	return (read_cpuid_id() & 0xFF000000) >> 24;
}

static inline unsigned int __attribute_const__ read_cpuid_revision(void)
{
	return read_cpuid_id() & 0x0000000f;
}

/*
 * The CPU part number is meaningless without referring to the CPU
 * implementer: implementers are free to define their own part numbers
 * which are permitted to clash with other implementer part numbers.
 */
static inline unsigned int __attribute_const__ read_cpuid_part(void)
{
	return read_cpuid_id() & ARM_CPU_PART_MASK;
}

static inline unsigned int __attribute_const__ __deprecated read_cpuid_part_number(void)
{
	return read_cpuid_id() & 0xFFF0;
}

static inline unsigned int __attribute_const__ xscale_cpu_arch_version(void)
{
	return read_cpuid_id() & ARM_CPU_XSCALE_ARCH_MASK;
}

static inline unsigned int __attribute_const__ read_cpuid_tcmstatus(void)
{
	return read_cpuid(CPUID_TCM);
}

static inline unsigned int __attribute_const__ read_cpuid_mpidr(void)
{
	return read_cpuid(CPUID_MPIDR);
}

/* StrongARM-11x0 CPUs */
#define cpu_is_sa1100() (read_cpuid_part() == ARM_CPU_PART_SA1100)
#define cpu_is_sa1110() (read_cpuid_part() == ARM_CPU_PART_SA1110)

/*
 * Intel's XScale3 core supports some v6 features (supersections, L2)
 * but advertises itself as v5 as it does not support the v6 ISA.  For
 * this reason, we need a way to explicitly test for this type of CPU.
 */
#ifndef CONFIG_CPU_XSC3
#define cpu_is_xsc3()	0
#else
static inline int cpu_is_xsc3(void)
{
	unsigned int id;
	id = read_cpuid_id() & 0xffffe000;
	/* It covers both Intel ID and Marvell ID */
	if ((id == 0x69056000) || (id == 0x56056000))
		return 1;

	return 0;
}
#endif

#if !defined(CONFIG_CPU_XSCALE) && !defined(CONFIG_CPU_XSC3) && \
    !defined(CONFIG_CPU_MOHAWK)
#define	cpu_is_xscale_family() 0
#else
static inline int cpu_is_xscale_family(void)
{
	unsigned int id;
	id = read_cpuid_id() & 0xffffe000;

	switch (id) {
	case 0x69052000: /* Intel XScale 1 */
	case 0x69054000: /* Intel XScale 2 */
	case 0x69056000: /* Intel XScale 3 */
	case 0x56056000: /* Marvell XScale 3 */
	case 0x56158000: /* Marvell Mohawk */
		return 1;
	}

	return 0;
}
#endif

/*
 * Marvell's PJ4 and PJ4B cores are based on V7 version,
 * but require a specical sequence for enabling coprocessors.
 * For this reason, we need a way to distinguish them.
 */
#if defined(CONFIG_CPU_PJ4) || defined(CONFIG_CPU_PJ4B)
static inline int cpu_is_pj4(void)
{
	unsigned int id;

	id = read_cpuid_id();
	if ((id & 0xff0fff00) == 0x560f5800)
		return 1;

	return 0;
}
#else
#define cpu_is_pj4()	0
#endif

static inline int __attribute_const__ cpuid_feature_extract_field(u32 features,
								  int field)
{
	int feature = (features >> field) & 15;

	/* feature registers are signed values */
	if (feature > 7)
		feature -= 16;

	return feature;
}

#define cpuid_feature_extract(reg, field) \
	cpuid_feature_extract_field(read_cpuid_ext(reg), field)

#endif
Commit	Line	Data
0ba8b9b2 RK	1	#ifndef __ASM_ARM_CPUTYPE_H
	2	#define __ASM_ARM_CPUTYPE_H
	3
	4	#include <linux/stringify.h>
e9569c15	5	#include <linux/kernel.h>
0ba8b9b2 RK	6
	7	#define CPUID_ID 0
	8	#define CPUID_CACHETYPE 1
	9	#define CPUID_TCM 2
	10	#define CPUID_TLBTYPE 3
aca7e592	11	#define CPUID_MPUIR 4
c9018aab	12	#define CPUID_MPIDR 5
92871b94	13	#define CPUID_REVIDR 6
0ba8b9b2	14
6fae9cda UKK	15	#ifdef CONFIG_CPU_V7M
	16	#define CPUID_EXT_PFR0 0x40
	17	#define CPUID_EXT_PFR1 0x44
	18	#define CPUID_EXT_DFR0 0x48
	19	#define CPUID_EXT_AFR0 0x4c
	20	#define CPUID_EXT_MMFR0 0x50
	21	#define CPUID_EXT_MMFR1 0x54
	22	#define CPUID_EXT_MMFR2 0x58
	23	#define CPUID_EXT_MMFR3 0x5c
	24	#define CPUID_EXT_ISAR0 0x60
	25	#define CPUID_EXT_ISAR1 0x64
	26	#define CPUID_EXT_ISAR2 0x68
	27	#define CPUID_EXT_ISAR3 0x6c
	28	#define CPUID_EXT_ISAR4 0x70
	29	#define CPUID_EXT_ISAR5 0x74
	30	#else
faa7bc51 CM	31	#define CPUID_EXT_PFR0 "c1, 0"
	32	#define CPUID_EXT_PFR1 "c1, 1"
	33	#define CPUID_EXT_DFR0 "c1, 2"
	34	#define CPUID_EXT_AFR0 "c1, 3"
	35	#define CPUID_EXT_MMFR0 "c1, 4"
	36	#define CPUID_EXT_MMFR1 "c1, 5"
	37	#define CPUID_EXT_MMFR2 "c1, 6"
	38	#define CPUID_EXT_MMFR3 "c1, 7"
	39	#define CPUID_EXT_ISAR0 "c2, 0"
	40	#define CPUID_EXT_ISAR1 "c2, 1"
	41	#define CPUID_EXT_ISAR2 "c2, 2"
	42	#define CPUID_EXT_ISAR3 "c2, 3"
	43	#define CPUID_EXT_ISAR4 "c2, 4"
	44	#define CPUID_EXT_ISAR5 "c2, 5"
6fae9cda	45	#endif
faa7bc51	46
dca463da LP	47	#define MPIDR_SMP_BITMASK (0x3 << 30)
	48	#define MPIDR_SMP_VALUE (0x2 << 30)
	49
	50	#define MPIDR_MT_BITMASK (0x1 << 24)
	51
	52	#define MPIDR_HWID_BITMASK 0xFFFFFF
	53
18d7f152 LP	54	#define MPIDR_INVALID (~MPIDR_HWID_BITMASK)
18d7f152 LP	55
dca463da LP	56	#define MPIDR_LEVEL_BITS 8
	57	#define MPIDR_LEVEL_MASK ((1 << MPIDR_LEVEL_BITS) - 1)
	58
	59	#define MPIDR_AFFINITY_LEVEL(mpidr, level) \
	60	((mpidr >> (MPIDR_LEVEL_BITS * level)) & MPIDR_LEVEL_MASK)
	61
73a09d21	62	#define ARM_CPU_IMP_ARM 0x41
83809b90	63	#define ARM_CPU_IMP_DEC 0x44
73a09d21 RK	64	#define ARM_CPU_IMP_INTEL 0x69
73a09d21 RK	65
af040ffc RK	66	/* ARM implemented processors */
	67	#define ARM_CPU_PART_ARM1136 0x4100b360
	68	#define ARM_CPU_PART_ARM1156 0x4100b560
	69	#define ARM_CPU_PART_ARM1176 0x4100b760
	70	#define ARM_CPU_PART_ARM11MPCORE 0x4100b020
	71	#define ARM_CPU_PART_CORTEX_A8 0x4100c080
	72	#define ARM_CPU_PART_CORTEX_A9 0x4100c090
	73	#define ARM_CPU_PART_CORTEX_A5 0x4100c050
	74	#define ARM_CPU_PART_CORTEX_A7 0x4100c070
	75	#define ARM_CPU_PART_CORTEX_A12 0x4100c0d0
	76	#define ARM_CPU_PART_CORTEX_A17 0x4100c0e0
	77	#define ARM_CPU_PART_CORTEX_A15 0x4100c0f0
eba1c718	78	#define ARM_CPU_PART_MASK 0xff00fff0
73a09d21	79
83809b90 RK	80	/* DEC implemented cores */
	81	#define ARM_CPU_PART_SA1100 0x4400a110
	82
	83	/* Intel implemented cores */
	84	#define ARM_CPU_PART_SA1110 0x6900b110
	85	#define ARM_CPU_REV_SA1110_A0 0
	86	#define ARM_CPU_REV_SA1110_B0 4
	87	#define ARM_CPU_REV_SA1110_B1 5
	88	#define ARM_CPU_REV_SA1110_B2 6
	89	#define ARM_CPU_REV_SA1110_B4 8
	90
73a09d21 RK	91	#define ARM_CPU_XSCALE_ARCH_MASK 0xe000
	92	#define ARM_CPU_XSCALE_ARCH_V1 0x2000
	93	#define ARM_CPU_XSCALE_ARCH_V2 0x4000
	94	#define ARM_CPU_XSCALE_ARCH_V3 0x6000
	95
2bbd7e9b RK	96	extern unsigned int processor_id;
2bbd7e9b RK	97
0ba8b9b2 RK	98	#ifdef CONFIG_CPU_CP15
	99	#define read_cpuid(reg) \
	100	({ \
	101	unsigned int __val; \
	102	asm("mrc p15, 0, %0, c0, c0, " __stringify(reg) \
	103	: "=r" (__val) \
	104	: \
	105	: "cc"); \
	106	__val; \
	107	})
6ebd4d03	108
067e710b PW	109	/*
	110	* The memory clobber prevents gcc 4.5 from reordering the mrc before
	111	* any is_smp() tests, which can cause undefined instruction aborts on
	112	* ARM1136 r0 due to the missing extended CP15 registers.
	113	*/
faa7bc51 CM	114	#define read_cpuid_ext(ext_reg) \
	115	({ \
	116	unsigned int __val; \
	117	asm("mrc p15, 0, %0, c0, " ext_reg \
	118	: "=r" (__val) \
	119	: \
067e710b	120	: "memory"); \
faa7bc51 CM	121	__val; \
faa7bc51 CM	122	})
0ba8b9b2	123
6fae9cda UKK	124	#elif defined(CONFIG_CPU_V7M)
	125
	126	#include <asm/io.h>
	127	#include <asm/v7m.h>
	128
	129	#define read_cpuid(reg) \
	130	({ \
	131	WARN_ON_ONCE(1); \
	132	0; \
	133	})
	134
	135	static inline unsigned int __attribute_const__ read_cpuid_ext(unsigned offset)
	136	{
	137	return readl(BASEADDR_V7M_SCB + offset);
	138	}
	139
	140	#else /* ifdef CONFIG_CPU_CP15 / elif defined (CONFIG_CPU_V7M) */
59530adc	141
6ebd4d03 UKK	142	/*
	143	* read_cpuid and read_cpuid_ext should only ever be called on machines that
	144	* have cp15 so warn on other usages.
	145	*/
	146	#define read_cpuid(reg) \
	147	({ \
	148	WARN_ON_ONCE(1); \
	149	0; \
	150	})
59530adc	151
6ebd4d03	152	#define read_cpuid_ext(reg) read_cpuid(reg)
59530adc	153
6ebd4d03 UKK	154	#endif /* ifdef CONFIG_CPU_CP15 / else */
	155
	156	#ifdef CONFIG_CPU_CP15
0ba8b9b2 RK	157	/*
	158	* The CPU ID never changes at run time, so we might as well tell the
	159	* compiler that it's constant. Use this function to read the CPU ID
	160	* rather than directly reading processor_id or read_cpuid() directly.
	161	*/
	162	static inline unsigned int __attribute_const__ read_cpuid_id(void)
	163	{
	164	return read_cpuid(CPUID_ID);
	165	}
	166
f5a5c89e JA	167	static inline unsigned int __attribute_const__ read_cpuid_cachetype(void)
	168	{
	169	return read_cpuid(CPUID_CACHETYPE);
	170	}
	171
55bdd694 CM	172	#elif defined(CONFIG_CPU_V7M)
55bdd694 CM	173
55bdd694 CM	174	static inline unsigned int __attribute_const__ read_cpuid_id(void)
	175	{
	176	return readl(BASEADDR_V7M_SCB + V7M_SCB_CPUID);
	177	}
	178
f5a5c89e JA	179	static inline unsigned int __attribute_const__ read_cpuid_cachetype(void)
	180	{
	181	return readl(BASEADDR_V7M_SCB + V7M_SCB_CTR);
	182	}
	183
55bdd694	184	#else /* ifdef CONFIG_CPU_CP15 / elif defined(CONFIG_CPU_V7M) */
6ebd4d03 UKK	185
	186	static inline unsigned int __attribute_const__ read_cpuid_id(void)
	187	{
	188	return processor_id;
	189	}
	190
	191	#endif /* ifdef CONFIG_CPU_CP15 / else */
	192
59530adc CD	193	static inline unsigned int __attribute_const__ read_cpuid_implementor(void)
	194	{
	195	return (read_cpuid_id() & 0xFF000000) >> 24;
	196	}
	197
83809b90 RK	198	static inline unsigned int __attribute_const__ read_cpuid_revision(void)
	199	{
	200	return read_cpuid_id() & 0x0000000f;
	201	}
	202
af040ffc RK	203	/*
	204	* The CPU part number is meaningless without referring to the CPU
	205	* implementer: implementers are free to define their own part numbers
	206	* which are permitted to clash with other implementer part numbers.
	207	*/
	208	static inline unsigned int __attribute_const__ read_cpuid_part(void)
	209	{
eba1c718	210	return read_cpuid_id() & ARM_CPU_PART_MASK;
af040ffc RK	211	}
	212
	213	static inline unsigned int __attribute_const__ __deprecated read_cpuid_part_number(void)
59530adc CD	214	{
	215	return read_cpuid_id() & 0xFFF0;
	216	}
	217
	218	static inline unsigned int __attribute_const__ xscale_cpu_arch_version(void)
	219	{
af040ffc	220	return read_cpuid_id() & ARM_CPU_XSCALE_ARCH_MASK;
59530adc CD	221	}
59530adc CD	222
bc581770 LW	223	static inline unsigned int __attribute_const__ read_cpuid_tcmstatus(void)
	224	{
	225	return read_cpuid(CPUID_TCM);
	226	}
	227
c9018aab VG	228	static inline unsigned int __attribute_const__ read_cpuid_mpidr(void)
	229	{
	230	return read_cpuid(CPUID_MPIDR);
	231	}
	232
83809b90 RK	233	/* StrongARM-11x0 CPUs */
	234	#define cpu_is_sa1100() (read_cpuid_part() == ARM_CPU_PART_SA1100)
	235	#define cpu_is_sa1110() (read_cpuid_part() == ARM_CPU_PART_SA1110)
	236
0ba8b9b2 RK	237	/*
	238	* Intel's XScale3 core supports some v6 features (supersections, L2)
	239	* but advertises itself as v5 as it does not support the v6 ISA. For
	240	* this reason, we need a way to explicitly test for this type of CPU.
	241	*/
	242	#ifndef CONFIG_CPU_XSC3
	243	#define cpu_is_xsc3() 0
	244	#else
	245	static inline int cpu_is_xsc3(void)
	246	{
337c1db6 HZ	247	unsigned int id;
	248	id = read_cpuid_id() & 0xffffe000;
	249	/* It covers both Intel ID and Marvell ID */
	250	if ((id == 0x69056000) \|\| (id == 0x56056000))
0ba8b9b2 RK	251	return 1;
	252
	253	return 0;
	254	}
	255	#endif
	256
d33c43ac AB	257	#if !defined(CONFIG_CPU_XSCALE) && !defined(CONFIG_CPU_XSC3) && \
	258	!defined(CONFIG_CPU_MOHAWK)
	259	#define cpu_is_xscale_family() 0
0ba8b9b2	260	#else
d33c43ac AB	261	static inline int cpu_is_xscale_family(void)
	262	{
	263	unsigned int id;
	264	id = read_cpuid_id() & 0xffffe000;
	265
	266	switch (id) {
	267	case 0x69052000: /* Intel XScale 1 */
	268	case 0x69054000: /* Intel XScale 2 */
	269	case 0x69056000: /* Intel XScale 3 */
	270	case 0x56056000: /* Marvell XScale 3 */
	271	case 0x56158000: /* Marvell Mohawk */
	272	return 1;
	273	}
	274
	275	return 0;
	276	}
0ba8b9b2 RK	277	#endif
0ba8b9b2 RK	278
fdb487f5	279	/*
cd171170 SH	280	* Marvell's PJ4 and PJ4B cores are based on V7 version,
	281	* but require a specical sequence for enabling coprocessors.
	282	* For this reason, we need a way to distinguish them.
fdb487f5	283	*/
cd171170	284	#if defined(CONFIG_CPU_PJ4) \|\| defined(CONFIG_CPU_PJ4B)
fdb487f5 CXL	285	static inline int cpu_is_pj4(void)
	286	{
	287	unsigned int id;
	288
	289	id = read_cpuid_id();
cd171170	290	if ((id & 0xff0fff00) == 0x560f5800)
fdb487f5 CXL	291	return 1;
	292
	293	return 0;
	294	}
cd171170 SH	295	#else
cd171170 SH	296	#define cpu_is_pj4() 0
fdb487f5	297	#endif
b8c9592b AB	298
	299	static inline int __attribute_const__ cpuid_feature_extract_field(u32 features,
	300	int field)
	301	{
	302	int feature = (features >> field) & 15;
	303
	304	/* feature registers are signed values */
ac36a881	305	if (feature > 7)
b8c9592b AB	306	feature -= 16;
	307
	308	return feature;
	309	}
	310
	311	#define cpuid_feature_extract(reg, field) \
	312	cpuid_feature_extract_field(read_cpuid_ext(reg), field)
	313
0ba8b9b2	314	#endif