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342cd0ab CD |
1 | /* |
2 | * Copyright (C) 2012 - Virtual Open Systems and Columbia University | |
3 | * Author: Christoffer Dall <c.dall@virtualopensystems.com> | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License, version 2, as | |
7 | * published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program; if not, write to the Free Software | |
16 | * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. | |
17 | */ | |
18 | ||
19 | #ifndef __ARM_KVM_MMU_H__ | |
20 | #define __ARM_KVM_MMU_H__ | |
21 | ||
5a677ce0 MZ |
22 | #include <asm/memory.h> |
23 | #include <asm/page.h> | |
c62ee2b2 | 24 | |
06e8c3b0 MZ |
25 | /* |
26 | * We directly use the kernel VA for the HYP, as we can directly share | |
27 | * the mapping (HTTBR "covers" TTBR1). | |
28 | */ | |
5a677ce0 | 29 | #define HYP_PAGE_OFFSET_MASK UL(~0) |
06e8c3b0 MZ |
30 | #define HYP_PAGE_OFFSET PAGE_OFFSET |
31 | #define KERN_TO_HYP(kva) (kva) | |
32 | ||
5a677ce0 MZ |
33 | /* |
34 | * Our virtual mapping for the boot-time MMU-enable code. Must be | |
35 | * shared across all the page-tables. Conveniently, we use the vectors | |
36 | * page, where no kernel data will ever be shared with HYP. | |
37 | */ | |
38 | #define TRAMPOLINE_VA UL(CONFIG_VECTORS_BASE) | |
39 | ||
38f791a4 CD |
40 | /* |
41 | * KVM_MMU_CACHE_MIN_PAGES is the number of stage2 page table translation levels. | |
42 | */ | |
43 | #define KVM_MMU_CACHE_MIN_PAGES 2 | |
44 | ||
5a677ce0 MZ |
45 | #ifndef __ASSEMBLY__ |
46 | ||
363ef89f | 47 | #include <linux/highmem.h> |
5a677ce0 MZ |
48 | #include <asm/cacheflush.h> |
49 | #include <asm/pgalloc.h> | |
b1ae9a30 | 50 | #include <asm/stage2_pgtable.h> |
5a677ce0 | 51 | |
342cd0ab CD |
52 | int create_hyp_mappings(void *from, void *to); |
53 | int create_hyp_io_mappings(void *from, void *to, phys_addr_t); | |
d157f4a5 | 54 | void free_boot_hyp_pgd(void); |
4f728276 | 55 | void free_hyp_pgds(void); |
342cd0ab | 56 | |
957db105 | 57 | void stage2_unmap_vm(struct kvm *kvm); |
d5d8184d CD |
58 | int kvm_alloc_stage2_pgd(struct kvm *kvm); |
59 | void kvm_free_stage2_pgd(struct kvm *kvm); | |
60 | int kvm_phys_addr_ioremap(struct kvm *kvm, phys_addr_t guest_ipa, | |
c40f2f8f | 61 | phys_addr_t pa, unsigned long size, bool writable); |
d5d8184d CD |
62 | |
63 | int kvm_handle_guest_abort(struct kvm_vcpu *vcpu, struct kvm_run *run); | |
64 | ||
65 | void kvm_mmu_free_memory_caches(struct kvm_vcpu *vcpu); | |
66 | ||
342cd0ab | 67 | phys_addr_t kvm_mmu_get_httbr(void); |
5a677ce0 MZ |
68 | phys_addr_t kvm_mmu_get_boot_httbr(void); |
69 | phys_addr_t kvm_get_idmap_vector(void); | |
342cd0ab CD |
70 | int kvm_mmu_init(void); |
71 | void kvm_clear_hyp_idmap(void); | |
94f8e641 | 72 | |
ad361f09 CD |
73 | static inline void kvm_set_pmd(pmd_t *pmd, pmd_t new_pmd) |
74 | { | |
75 | *pmd = new_pmd; | |
76 | flush_pmd_entry(pmd); | |
77 | } | |
78 | ||
c62ee2b2 MZ |
79 | static inline void kvm_set_pte(pte_t *pte, pte_t new_pte) |
80 | { | |
0963e5d0 | 81 | *pte = new_pte; |
c62ee2b2 MZ |
82 | /* |
83 | * flush_pmd_entry just takes a void pointer and cleans the necessary | |
84 | * cache entries, so we can reuse the function for ptes. | |
85 | */ | |
86 | flush_pmd_entry(pte); | |
87 | } | |
88 | ||
c62ee2b2 MZ |
89 | static inline void kvm_clean_pgd(pgd_t *pgd) |
90 | { | |
91 | clean_dcache_area(pgd, PTRS_PER_S2_PGD * sizeof(pgd_t)); | |
92 | } | |
93 | ||
38f791a4 CD |
94 | static inline void kvm_clean_pmd(pmd_t *pmd) |
95 | { | |
96 | clean_dcache_area(pmd, PTRS_PER_PMD * sizeof(pmd_t)); | |
97 | } | |
98 | ||
c62ee2b2 MZ |
99 | static inline void kvm_clean_pmd_entry(pmd_t *pmd) |
100 | { | |
101 | clean_pmd_entry(pmd); | |
102 | } | |
103 | ||
104 | static inline void kvm_clean_pte(pte_t *pte) | |
105 | { | |
106 | clean_pte_table(pte); | |
107 | } | |
108 | ||
06485053 | 109 | static inline pte_t kvm_s2pte_mkwrite(pte_t pte) |
c62ee2b2 | 110 | { |
06485053 CM |
111 | pte_val(pte) |= L_PTE_S2_RDWR; |
112 | return pte; | |
c62ee2b2 MZ |
113 | } |
114 | ||
06485053 | 115 | static inline pmd_t kvm_s2pmd_mkwrite(pmd_t pmd) |
ad361f09 | 116 | { |
06485053 CM |
117 | pmd_val(pmd) |= L_PMD_S2_RDWR; |
118 | return pmd; | |
ad361f09 CD |
119 | } |
120 | ||
c6473555 MS |
121 | static inline void kvm_set_s2pte_readonly(pte_t *pte) |
122 | { | |
123 | pte_val(*pte) = (pte_val(*pte) & ~L_PTE_S2_RDWR) | L_PTE_S2_RDONLY; | |
124 | } | |
125 | ||
126 | static inline bool kvm_s2pte_readonly(pte_t *pte) | |
127 | { | |
128 | return (pte_val(*pte) & L_PTE_S2_RDWR) == L_PTE_S2_RDONLY; | |
129 | } | |
130 | ||
131 | static inline void kvm_set_s2pmd_readonly(pmd_t *pmd) | |
132 | { | |
133 | pmd_val(*pmd) = (pmd_val(*pmd) & ~L_PMD_S2_RDWR) | L_PMD_S2_RDONLY; | |
134 | } | |
135 | ||
136 | static inline bool kvm_s2pmd_readonly(pmd_t *pmd) | |
137 | { | |
138 | return (pmd_val(*pmd) & L_PMD_S2_RDWR) == L_PMD_S2_RDONLY; | |
139 | } | |
140 | ||
4f853a71 CD |
141 | static inline bool kvm_page_empty(void *ptr) |
142 | { | |
143 | struct page *ptr_page = virt_to_page(ptr); | |
144 | return page_count(ptr_page) == 1; | |
145 | } | |
146 | ||
38f791a4 CD |
147 | #define kvm_pte_table_empty(kvm, ptep) kvm_page_empty(ptep) |
148 | #define kvm_pmd_table_empty(kvm, pmdp) kvm_page_empty(pmdp) | |
b1d030a7 SP |
149 | #define kvm_pud_table_empty(kvm, pudp) false |
150 | ||
151 | #define hyp_pte_table_empty(ptep) kvm_page_empty(ptep) | |
152 | #define hyp_pmd_table_empty(pmdp) kvm_page_empty(pmdp) | |
153 | #define hyp_pud_table_empty(pudp) false | |
38f791a4 | 154 | |
c62ee2b2 MZ |
155 | struct kvm; |
156 | ||
15979300 MZ |
157 | #define kvm_flush_dcache_to_poc(a,l) __cpuc_flush_dcache_area((a), (l)) |
158 | ||
159 | static inline bool vcpu_has_cache_enabled(struct kvm_vcpu *vcpu) | |
160 | { | |
fb32a52a | 161 | return (vcpu_cp15(vcpu, c1_SCTLR) & 0b101) == 0b101; |
15979300 MZ |
162 | } |
163 | ||
ba049e93 DW |
164 | static inline void __coherent_cache_guest_page(struct kvm_vcpu *vcpu, |
165 | kvm_pfn_t pfn, | |
0d3e4d4f MZ |
166 | unsigned long size, |
167 | bool ipa_uncached) | |
c62ee2b2 MZ |
168 | { |
169 | /* | |
170 | * If we are going to insert an instruction page and the icache is | |
171 | * either VIPT or PIPT, there is a potential problem where the host | |
172 | * (or another VM) may have used the same page as this guest, and we | |
173 | * read incorrect data from the icache. If we're using a PIPT cache, | |
174 | * we can invalidate just that page, but if we are using a VIPT cache | |
175 | * we need to invalidate the entire icache - damn shame - as written | |
176 | * in the ARM ARM (DDI 0406C.b - Page B3-1393). | |
177 | * | |
178 | * VIVT caches are tagged using both the ASID and the VMID and doesn't | |
179 | * need any kind of flushing (DDI 0406C.b - Page B3-1392). | |
0d3e4d4f MZ |
180 | * |
181 | * We need to do this through a kernel mapping (using the | |
182 | * user-space mapping has proved to be the wrong | |
183 | * solution). For that, we need to kmap one page at a time, | |
184 | * and iterate over the range. | |
c62ee2b2 | 185 | */ |
0d3e4d4f MZ |
186 | |
187 | bool need_flush = !vcpu_has_cache_enabled(vcpu) || ipa_uncached; | |
188 | ||
a050dfb2 | 189 | VM_BUG_ON(size & ~PAGE_MASK); |
0d3e4d4f MZ |
190 | |
191 | if (!need_flush && !icache_is_pipt()) | |
192 | goto vipt_cache; | |
193 | ||
194 | while (size) { | |
195 | void *va = kmap_atomic_pfn(pfn); | |
196 | ||
197 | if (need_flush) | |
198 | kvm_flush_dcache_to_poc(va, PAGE_SIZE); | |
199 | ||
200 | if (icache_is_pipt()) | |
201 | __cpuc_coherent_user_range((unsigned long)va, | |
202 | (unsigned long)va + PAGE_SIZE); | |
203 | ||
204 | size -= PAGE_SIZE; | |
205 | pfn++; | |
206 | ||
207 | kunmap_atomic(va); | |
208 | } | |
209 | ||
210 | vipt_cache: | |
211 | if (!icache_is_pipt() && !icache_is_vivt_asid_tagged()) { | |
c62ee2b2 MZ |
212 | /* any kind of VIPT cache */ |
213 | __flush_icache_all(); | |
214 | } | |
215 | } | |
216 | ||
363ef89f MZ |
217 | static inline void __kvm_flush_dcache_pte(pte_t pte) |
218 | { | |
219 | void *va = kmap_atomic(pte_page(pte)); | |
220 | ||
221 | kvm_flush_dcache_to_poc(va, PAGE_SIZE); | |
222 | ||
223 | kunmap_atomic(va); | |
224 | } | |
225 | ||
226 | static inline void __kvm_flush_dcache_pmd(pmd_t pmd) | |
227 | { | |
228 | unsigned long size = PMD_SIZE; | |
ba049e93 | 229 | kvm_pfn_t pfn = pmd_pfn(pmd); |
363ef89f MZ |
230 | |
231 | while (size) { | |
232 | void *va = kmap_atomic_pfn(pfn); | |
233 | ||
234 | kvm_flush_dcache_to_poc(va, PAGE_SIZE); | |
235 | ||
236 | pfn++; | |
237 | size -= PAGE_SIZE; | |
238 | ||
239 | kunmap_atomic(va); | |
240 | } | |
241 | } | |
242 | ||
243 | static inline void __kvm_flush_dcache_pud(pud_t pud) | |
244 | { | |
245 | } | |
246 | ||
4fda342c | 247 | #define kvm_virt_to_phys(x) virt_to_idmap((unsigned long)(x)) |
5a677ce0 | 248 | |
3c1e7165 MZ |
249 | void kvm_set_way_flush(struct kvm_vcpu *vcpu); |
250 | void kvm_toggle_cache(struct kvm_vcpu *vcpu, bool was_enabled); | |
9d218a1f | 251 | |
e4c5a685 AB |
252 | static inline bool __kvm_cpu_uses_extended_idmap(void) |
253 | { | |
254 | return false; | |
255 | } | |
256 | ||
257 | static inline void __kvm_extend_hypmap(pgd_t *boot_hyp_pgd, | |
258 | pgd_t *hyp_pgd, | |
259 | pgd_t *merged_hyp_pgd, | |
260 | unsigned long hyp_idmap_start) { } | |
261 | ||
20475f78 VM |
262 | static inline unsigned int kvm_get_vmid_bits(void) |
263 | { | |
264 | return 8; | |
265 | } | |
266 | ||
5a677ce0 MZ |
267 | #endif /* !__ASSEMBLY__ */ |
268 | ||
342cd0ab | 269 | #endif /* __ARM_KVM_MMU_H__ */ |