Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * linux/arch/arm/kernel/entry-armv.S | |
3 | * | |
4 | * Copyright (C) 1996,1997,1998 Russell King. | |
5 | * ARM700 fix by Matthew Godbolt (linux-user@willothewisp.demon.co.uk) | |
afeb90ca | 6 | * nommu support by Hyok S. Choi (hyok.choi@samsung.com) |
1da177e4 LT |
7 | * |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * Low-level vector interface routines | |
13 | * | |
70b6f2b4 NP |
14 | * Note: there is a StrongARM bug in the STMIA rn, {regs}^ instruction |
15 | * that causes it to save wrong values... Be aware! | |
1da177e4 | 16 | */ |
1da177e4 | 17 | |
9b9cf81a PG |
18 | #include <linux/init.h> |
19 | ||
6f6f6a70 | 20 | #include <asm/assembler.h> |
f09b9979 | 21 | #include <asm/memory.h> |
753790e7 RK |
22 | #include <asm/glue-df.h> |
23 | #include <asm/glue-pf.h> | |
1da177e4 | 24 | #include <asm/vfpmacros.h> |
243c8654 | 25 | #ifndef CONFIG_MULTI_IRQ_HANDLER |
a09e64fb | 26 | #include <mach/entry-macro.S> |
243c8654 | 27 | #endif |
d6551e88 | 28 | #include <asm/thread_notify.h> |
c4c5716e | 29 | #include <asm/unwind.h> |
cc20d429 | 30 | #include <asm/unistd.h> |
f159f4ed | 31 | #include <asm/tls.h> |
9f97da78 | 32 | #include <asm/system_info.h> |
1da177e4 LT |
33 | |
34 | #include "entry-header.S" | |
cd544ce7 | 35 | #include <asm/entry-macro-multi.S> |
a0266c21 | 36 | #include <asm/probes.h> |
1da177e4 | 37 | |
187a51ad | 38 | /* |
d9600c99 | 39 | * Interrupt handling. |
187a51ad RK |
40 | */ |
41 | .macro irq_handler | |
52108641 | 42 | #ifdef CONFIG_MULTI_IRQ_HANDLER |
d9600c99 | 43 | ldr r1, =handle_arch_irq |
52108641 | 44 | mov r0, sp |
14327c66 | 45 | badr lr, 9997f |
abeb24ae MZ |
46 | ldr pc, [r1] |
47 | #else | |
cd544ce7 | 48 | arch_irq_handler_default |
abeb24ae | 49 | #endif |
f00ec48f | 50 | 9997: |
187a51ad RK |
51 | .endm |
52 | ||
ac8b9c1c | 53 | .macro pabt_helper |
8dfe7ac9 | 54 | @ PABORT handler takes pt_regs in r2, fault address in r4 and psr in r5 |
ac8b9c1c | 55 | #ifdef MULTI_PABORT |
0402bece | 56 | ldr ip, .LCprocfns |
ac8b9c1c | 57 | mov lr, pc |
0402bece | 58 | ldr pc, [ip, #PROCESSOR_PABT_FUNC] |
ac8b9c1c RK |
59 | #else |
60 | bl CPU_PABORT_HANDLER | |
61 | #endif | |
62 | .endm | |
63 | ||
64 | .macro dabt_helper | |
65 | ||
66 | @ | |
67 | @ Call the processor-specific abort handler: | |
68 | @ | |
da740472 | 69 | @ r2 - pt_regs |
3e287bec RK |
70 | @ r4 - aborted context pc |
71 | @ r5 - aborted context psr | |
ac8b9c1c RK |
72 | @ |
73 | @ The abort handler must return the aborted address in r0, and | |
74 | @ the fault status register in r1. r9 must be preserved. | |
75 | @ | |
76 | #ifdef MULTI_DABORT | |
0402bece | 77 | ldr ip, .LCprocfns |
ac8b9c1c | 78 | mov lr, pc |
0402bece | 79 | ldr pc, [ip, #PROCESSOR_DABT_FUNC] |
ac8b9c1c RK |
80 | #else |
81 | bl CPU_DABORT_HANDLER | |
82 | #endif | |
83 | .endm | |
84 | ||
785d3cd2 NP |
85 | #ifdef CONFIG_KPROBES |
86 | .section .kprobes.text,"ax",%progbits | |
87 | #else | |
88 | .text | |
89 | #endif | |
90 | ||
1da177e4 LT |
91 | /* |
92 | * Invalid mode handlers | |
93 | */ | |
ccea7a19 | 94 | .macro inv_entry, reason |
5745eef6 | 95 | sub sp, sp, #PT_REGS_SIZE |
b86040a5 CM |
96 | ARM( stmib sp, {r1 - lr} ) |
97 | THUMB( stmia sp, {r0 - r12} ) | |
98 | THUMB( str sp, [sp, #S_SP] ) | |
99 | THUMB( str lr, [sp, #S_LR] ) | |
1da177e4 LT |
100 | mov r1, #\reason |
101 | .endm | |
102 | ||
103 | __pabt_invalid: | |
ccea7a19 RK |
104 | inv_entry BAD_PREFETCH |
105 | b common_invalid | |
93ed3970 | 106 | ENDPROC(__pabt_invalid) |
1da177e4 LT |
107 | |
108 | __dabt_invalid: | |
ccea7a19 RK |
109 | inv_entry BAD_DATA |
110 | b common_invalid | |
93ed3970 | 111 | ENDPROC(__dabt_invalid) |
1da177e4 LT |
112 | |
113 | __irq_invalid: | |
ccea7a19 RK |
114 | inv_entry BAD_IRQ |
115 | b common_invalid | |
93ed3970 | 116 | ENDPROC(__irq_invalid) |
1da177e4 LT |
117 | |
118 | __und_invalid: | |
ccea7a19 RK |
119 | inv_entry BAD_UNDEFINSTR |
120 | ||
121 | @ | |
122 | @ XXX fall through to common_invalid | |
123 | @ | |
124 | ||
125 | @ | |
126 | @ common_invalid - generic code for failed exception (re-entrant version of handlers) | |
127 | @ | |
128 | common_invalid: | |
129 | zero_fp | |
130 | ||
131 | ldmia r0, {r4 - r6} | |
132 | add r0, sp, #S_PC @ here for interlock avoidance | |
133 | mov r7, #-1 @ "" "" "" "" | |
134 | str r4, [sp] @ save preserved r0 | |
135 | stmia r0, {r5 - r7} @ lr_<exception>, | |
136 | @ cpsr_<exception>, "old_r0" | |
1da177e4 | 137 | |
1da177e4 | 138 | mov r0, sp |
1da177e4 | 139 | b bad_mode |
93ed3970 | 140 | ENDPROC(__und_invalid) |
1da177e4 LT |
141 | |
142 | /* | |
143 | * SVC mode handlers | |
144 | */ | |
2dede2d8 NP |
145 | |
146 | #if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5) | |
147 | #define SPFIX(code...) code | |
148 | #else | |
149 | #define SPFIX(code...) | |
150 | #endif | |
151 | ||
2190fed6 | 152 | .macro svc_entry, stack_hole=0, trace=1, uaccess=1 |
c4c5716e CM |
153 | UNWIND(.fnstart ) |
154 | UNWIND(.save {r0 - pc} ) | |
5745eef6 | 155 | sub sp, sp, #(PT_REGS_SIZE + 8 + \stack_hole - 4) |
b86040a5 CM |
156 | #ifdef CONFIG_THUMB2_KERNEL |
157 | SPFIX( str r0, [sp] ) @ temporarily saved | |
158 | SPFIX( mov r0, sp ) | |
159 | SPFIX( tst r0, #4 ) @ test original stack alignment | |
160 | SPFIX( ldr r0, [sp] ) @ restored | |
161 | #else | |
2dede2d8 | 162 | SPFIX( tst sp, #4 ) |
b86040a5 CM |
163 | #endif |
164 | SPFIX( subeq sp, sp, #4 ) | |
165 | stmia sp, {r1 - r12} | |
ccea7a19 | 166 | |
b059bdc3 RK |
167 | ldmia r0, {r3 - r5} |
168 | add r7, sp, #S_SP - 4 @ here for interlock avoidance | |
169 | mov r6, #-1 @ "" "" "" "" | |
5745eef6 | 170 | add r2, sp, #(PT_REGS_SIZE + 8 + \stack_hole - 4) |
b059bdc3 RK |
171 | SPFIX( addeq r2, r2, #4 ) |
172 | str r3, [sp, #-4]! @ save the "real" r0 copied | |
ccea7a19 RK |
173 | @ from the exception stack |
174 | ||
b059bdc3 | 175 | mov r3, lr |
1da177e4 LT |
176 | |
177 | @ | |
178 | @ We are now ready to fill in the remaining blanks on the stack: | |
179 | @ | |
b059bdc3 RK |
180 | @ r2 - sp_svc |
181 | @ r3 - lr_svc | |
182 | @ r4 - lr_<exception>, already fixed up for correct return/restart | |
183 | @ r5 - spsr_<exception> | |
184 | @ r6 - orig_r0 (see pt_regs definition in ptrace.h) | |
1da177e4 | 185 | @ |
b059bdc3 | 186 | stmia r7, {r2 - r6} |
1da177e4 | 187 | |
2190fed6 RK |
188 | uaccess_save r0 |
189 | .if \uaccess | |
190 | uaccess_disable r0 | |
191 | .endif | |
192 | ||
c0e7f7ee | 193 | .if \trace |
02fe2845 RK |
194 | #ifdef CONFIG_TRACE_IRQFLAGS |
195 | bl trace_hardirqs_off | |
196 | #endif | |
c0e7f7ee | 197 | .endif |
f2741b78 | 198 | .endm |
1da177e4 | 199 | |
f2741b78 RK |
200 | .align 5 |
201 | __dabt_svc: | |
2190fed6 | 202 | svc_entry uaccess=0 |
1da177e4 | 203 | mov r2, sp |
da740472 | 204 | dabt_helper |
e16b31bf | 205 | THUMB( ldr r5, [sp, #S_PSR] ) @ potentially updated CPSR |
b059bdc3 | 206 | svc_exit r5 @ return from exception |
c4c5716e | 207 | UNWIND(.fnend ) |
93ed3970 | 208 | ENDPROC(__dabt_svc) |
1da177e4 LT |
209 | |
210 | .align 5 | |
211 | __irq_svc: | |
ccea7a19 | 212 | svc_entry |
187a51ad | 213 | irq_handler |
1613cc11 | 214 | |
1da177e4 | 215 | #ifdef CONFIG_PREEMPT |
1613cc11 RK |
216 | get_thread_info tsk |
217 | ldr r8, [tsk, #TI_PREEMPT] @ get preempt count | |
706fdd9f | 218 | ldr r0, [tsk, #TI_FLAGS] @ get flags |
28fab1a2 RK |
219 | teq r8, #0 @ if preempt count != 0 |
220 | movne r0, #0 @ force flags to 0 | |
1da177e4 LT |
221 | tst r0, #_TIF_NEED_RESCHED |
222 | blne svc_preempt | |
1da177e4 | 223 | #endif |
30891c90 | 224 | |
9b56febe | 225 | svc_exit r5, irq = 1 @ return from exception |
c4c5716e | 226 | UNWIND(.fnend ) |
93ed3970 | 227 | ENDPROC(__irq_svc) |
1da177e4 LT |
228 | |
229 | .ltorg | |
230 | ||
231 | #ifdef CONFIG_PREEMPT | |
232 | svc_preempt: | |
28fab1a2 | 233 | mov r8, lr |
1da177e4 | 234 | 1: bl preempt_schedule_irq @ irq en/disable is done inside |
706fdd9f | 235 | ldr r0, [tsk, #TI_FLAGS] @ get new tasks TI_FLAGS |
1da177e4 | 236 | tst r0, #_TIF_NEED_RESCHED |
6ebbf2ce | 237 | reteq r8 @ go again |
1da177e4 LT |
238 | b 1b |
239 | #endif | |
240 | ||
15ac49b6 RK |
241 | __und_fault: |
242 | @ Correct the PC such that it is pointing at the instruction | |
243 | @ which caused the fault. If the faulting instruction was ARM | |
244 | @ the PC will be pointing at the next instruction, and have to | |
245 | @ subtract 4. Otherwise, it is Thumb, and the PC will be | |
246 | @ pointing at the second half of the Thumb instruction. We | |
247 | @ have to subtract 2. | |
248 | ldr r2, [r0, #S_PC] | |
249 | sub r2, r2, r1 | |
250 | str r2, [r0, #S_PC] | |
251 | b do_undefinstr | |
252 | ENDPROC(__und_fault) | |
253 | ||
1da177e4 LT |
254 | .align 5 |
255 | __und_svc: | |
d30a0c8b NP |
256 | #ifdef CONFIG_KPROBES |
257 | @ If a kprobe is about to simulate a "stmdb sp..." instruction, | |
258 | @ it obviously needs free stack space which then will belong to | |
259 | @ the saved context. | |
a0266c21 | 260 | svc_entry MAX_STACK_SIZE |
d30a0c8b | 261 | #else |
ccea7a19 | 262 | svc_entry |
d30a0c8b | 263 | #endif |
1da177e4 LT |
264 | @ |
265 | @ call emulation code, which returns using r9 if it has emulated | |
266 | @ the instruction, or the more conventional lr if we are to treat | |
267 | @ this as a real undefined instruction | |
268 | @ | |
269 | @ r0 - instruction | |
270 | @ | |
15ac49b6 | 271 | #ifndef CONFIG_THUMB2_KERNEL |
b059bdc3 | 272 | ldr r0, [r4, #-4] |
83e686ea | 273 | #else |
15ac49b6 | 274 | mov r1, #2 |
b059bdc3 | 275 | ldrh r0, [r4, #-2] @ Thumb instruction at LR - 2 |
85519189 | 276 | cmp r0, #0xe800 @ 32-bit instruction if xx >= 0 |
15ac49b6 RK |
277 | blo __und_svc_fault |
278 | ldrh r9, [r4] @ bottom 16 bits | |
279 | add r4, r4, #2 | |
280 | str r4, [sp, #S_PC] | |
281 | orr r0, r9, r0, lsl #16 | |
83e686ea | 282 | #endif |
14327c66 | 283 | badr r9, __und_svc_finish |
b059bdc3 | 284 | mov r2, r4 |
1da177e4 LT |
285 | bl call_fpe |
286 | ||
15ac49b6 RK |
287 | mov r1, #4 @ PC correction to apply |
288 | __und_svc_fault: | |
1da177e4 | 289 | mov r0, sp @ struct pt_regs *regs |
15ac49b6 | 290 | bl __und_fault |
1da177e4 | 291 | |
15ac49b6 | 292 | __und_svc_finish: |
b059bdc3 RK |
293 | ldr r5, [sp, #S_PSR] @ Get SVC cpsr |
294 | svc_exit r5 @ return from exception | |
c4c5716e | 295 | UNWIND(.fnend ) |
93ed3970 | 296 | ENDPROC(__und_svc) |
1da177e4 LT |
297 | |
298 | .align 5 | |
299 | __pabt_svc: | |
ccea7a19 | 300 | svc_entry |
4fb28474 | 301 | mov r2, sp @ regs |
8dfe7ac9 | 302 | pabt_helper |
b059bdc3 | 303 | svc_exit r5 @ return from exception |
c4c5716e | 304 | UNWIND(.fnend ) |
93ed3970 | 305 | ENDPROC(__pabt_svc) |
1da177e4 | 306 | |
c0e7f7ee DT |
307 | .align 5 |
308 | __fiq_svc: | |
309 | svc_entry trace=0 | |
310 | mov r0, sp @ struct pt_regs *regs | |
311 | bl handle_fiq_as_nmi | |
312 | svc_exit_via_fiq | |
313 | UNWIND(.fnend ) | |
314 | ENDPROC(__fiq_svc) | |
315 | ||
1da177e4 | 316 | .align 5 |
49f680ea RK |
317 | .LCcralign: |
318 | .word cr_alignment | |
48d7927b | 319 | #ifdef MULTI_DABORT |
1da177e4 LT |
320 | .LCprocfns: |
321 | .word processor | |
322 | #endif | |
323 | .LCfp: | |
324 | .word fp_enter | |
1da177e4 | 325 | |
c0e7f7ee DT |
326 | /* |
327 | * Abort mode handlers | |
328 | */ | |
329 | ||
330 | @ | |
331 | @ Taking a FIQ in abort mode is similar to taking a FIQ in SVC mode | |
332 | @ and reuses the same macros. However in abort mode we must also | |
333 | @ save/restore lr_abt and spsr_abt to make nested aborts safe. | |
334 | @ | |
335 | .align 5 | |
336 | __fiq_abt: | |
337 | svc_entry trace=0 | |
338 | ||
339 | ARM( msr cpsr_c, #ABT_MODE | PSR_I_BIT | PSR_F_BIT ) | |
340 | THUMB( mov r0, #ABT_MODE | PSR_I_BIT | PSR_F_BIT ) | |
341 | THUMB( msr cpsr_c, r0 ) | |
342 | mov r1, lr @ Save lr_abt | |
343 | mrs r2, spsr @ Save spsr_abt, abort is now safe | |
344 | ARM( msr cpsr_c, #SVC_MODE | PSR_I_BIT | PSR_F_BIT ) | |
345 | THUMB( mov r0, #SVC_MODE | PSR_I_BIT | PSR_F_BIT ) | |
346 | THUMB( msr cpsr_c, r0 ) | |
347 | stmfd sp!, {r1 - r2} | |
348 | ||
349 | add r0, sp, #8 @ struct pt_regs *regs | |
350 | bl handle_fiq_as_nmi | |
351 | ||
352 | ldmfd sp!, {r1 - r2} | |
353 | ARM( msr cpsr_c, #ABT_MODE | PSR_I_BIT | PSR_F_BIT ) | |
354 | THUMB( mov r0, #ABT_MODE | PSR_I_BIT | PSR_F_BIT ) | |
355 | THUMB( msr cpsr_c, r0 ) | |
356 | mov lr, r1 @ Restore lr_abt, abort is unsafe | |
357 | msr spsr_cxsf, r2 @ Restore spsr_abt | |
358 | ARM( msr cpsr_c, #SVC_MODE | PSR_I_BIT | PSR_F_BIT ) | |
359 | THUMB( mov r0, #SVC_MODE | PSR_I_BIT | PSR_F_BIT ) | |
360 | THUMB( msr cpsr_c, r0 ) | |
361 | ||
362 | svc_exit_via_fiq | |
363 | UNWIND(.fnend ) | |
364 | ENDPROC(__fiq_abt) | |
365 | ||
1da177e4 LT |
366 | /* |
367 | * User mode handlers | |
2dede2d8 | 368 | * |
5745eef6 | 369 | * EABI note: sp_svc is always 64-bit aligned here, so should PT_REGS_SIZE |
1da177e4 | 370 | */ |
2dede2d8 | 371 | |
5745eef6 | 372 | #if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5) && (PT_REGS_SIZE & 7) |
2dede2d8 NP |
373 | #error "sizeof(struct pt_regs) must be a multiple of 8" |
374 | #endif | |
375 | ||
2190fed6 | 376 | .macro usr_entry, trace=1, uaccess=1 |
c4c5716e CM |
377 | UNWIND(.fnstart ) |
378 | UNWIND(.cantunwind ) @ don't unwind the user space | |
5745eef6 | 379 | sub sp, sp, #PT_REGS_SIZE |
b86040a5 CM |
380 | ARM( stmib sp, {r1 - r12} ) |
381 | THUMB( stmia sp, {r0 - r12} ) | |
ccea7a19 | 382 | |
195b58ad RK |
383 | ATRAP( mrc p15, 0, r7, c1, c0, 0) |
384 | ATRAP( ldr r8, .LCcralign) | |
385 | ||
b059bdc3 | 386 | ldmia r0, {r3 - r5} |
ccea7a19 | 387 | add r0, sp, #S_PC @ here for interlock avoidance |
b059bdc3 | 388 | mov r6, #-1 @ "" "" "" "" |
ccea7a19 | 389 | |
b059bdc3 | 390 | str r3, [sp] @ save the "real" r0 copied |
ccea7a19 | 391 | @ from the exception stack |
1da177e4 | 392 | |
195b58ad RK |
393 | ATRAP( ldr r8, [r8, #0]) |
394 | ||
1da177e4 LT |
395 | @ |
396 | @ We are now ready to fill in the remaining blanks on the stack: | |
397 | @ | |
b059bdc3 RK |
398 | @ r4 - lr_<exception>, already fixed up for correct return/restart |
399 | @ r5 - spsr_<exception> | |
400 | @ r6 - orig_r0 (see pt_regs definition in ptrace.h) | |
1da177e4 LT |
401 | @ |
402 | @ Also, separately save sp_usr and lr_usr | |
403 | @ | |
b059bdc3 | 404 | stmia r0, {r4 - r6} |
b86040a5 CM |
405 | ARM( stmdb r0, {sp, lr}^ ) |
406 | THUMB( store_user_sp_lr r0, r1, S_SP - S_PC ) | |
1da177e4 | 407 | |
2190fed6 RK |
408 | .if \uaccess |
409 | uaccess_disable ip | |
410 | .endif | |
411 | ||
1da177e4 | 412 | @ Enable the alignment trap while in kernel mode |
195b58ad RK |
413 | ATRAP( teq r8, r7) |
414 | ATRAP( mcrne p15, 0, r8, c1, c0, 0) | |
1da177e4 LT |
415 | |
416 | @ | |
417 | @ Clear FP to mark the first stack frame | |
418 | @ | |
419 | zero_fp | |
f2741b78 | 420 | |
c0e7f7ee | 421 | .if \trace |
11b8b25c | 422 | #ifdef CONFIG_TRACE_IRQFLAGS |
f2741b78 RK |
423 | bl trace_hardirqs_off |
424 | #endif | |
b0088480 | 425 | ct_user_exit save = 0 |
c0e7f7ee | 426 | .endif |
1da177e4 LT |
427 | .endm |
428 | ||
b49c0f24 | 429 | .macro kuser_cmpxchg_check |
db695c05 | 430 | #if !defined(CONFIG_CPU_32v6K) && defined(CONFIG_KUSER_HELPERS) |
b49c0f24 NP |
431 | #ifndef CONFIG_MMU |
432 | #warning "NPTL on non MMU needs fixing" | |
433 | #else | |
434 | @ Make sure our user space atomic helper is restarted | |
435 | @ if it was interrupted in a critical region. Here we | |
436 | @ perform a quick test inline since it should be false | |
437 | @ 99.9999% of the time. The rest is done out of line. | |
b059bdc3 | 438 | cmp r4, #TASK_SIZE |
40fb79c8 | 439 | blhs kuser_cmpxchg64_fixup |
b49c0f24 NP |
440 | #endif |
441 | #endif | |
442 | .endm | |
443 | ||
1da177e4 LT |
444 | .align 5 |
445 | __dabt_usr: | |
2190fed6 | 446 | usr_entry uaccess=0 |
b49c0f24 | 447 | kuser_cmpxchg_check |
1da177e4 | 448 | mov r2, sp |
da740472 RK |
449 | dabt_helper |
450 | b ret_from_exception | |
c4c5716e | 451 | UNWIND(.fnend ) |
93ed3970 | 452 | ENDPROC(__dabt_usr) |
1da177e4 LT |
453 | |
454 | .align 5 | |
455 | __irq_usr: | |
ccea7a19 | 456 | usr_entry |
bc089602 | 457 | kuser_cmpxchg_check |
187a51ad | 458 | irq_handler |
1613cc11 | 459 | get_thread_info tsk |
1da177e4 | 460 | mov why, #0 |
9fc2552a | 461 | b ret_to_user_from_irq |
c4c5716e | 462 | UNWIND(.fnend ) |
93ed3970 | 463 | ENDPROC(__irq_usr) |
1da177e4 LT |
464 | |
465 | .ltorg | |
466 | ||
467 | .align 5 | |
468 | __und_usr: | |
2190fed6 | 469 | usr_entry uaccess=0 |
bc089602 | 470 | |
b059bdc3 RK |
471 | mov r2, r4 |
472 | mov r3, r5 | |
1da177e4 | 473 | |
15ac49b6 RK |
474 | @ r2 = regs->ARM_pc, which is either 2 or 4 bytes ahead of the |
475 | @ faulting instruction depending on Thumb mode. | |
476 | @ r3 = regs->ARM_cpsr | |
1da177e4 | 477 | @ |
15ac49b6 RK |
478 | @ The emulation code returns using r9 if it has emulated the |
479 | @ instruction, or the more conventional lr if we are to treat | |
480 | @ this as a real undefined instruction | |
1da177e4 | 481 | @ |
14327c66 | 482 | badr r9, ret_from_exception |
15ac49b6 | 483 | |
1417a6b8 CM |
484 | @ IRQs must be enabled before attempting to read the instruction from |
485 | @ user space since that could cause a page/translation fault if the | |
486 | @ page table was modified by another CPU. | |
487 | enable_irq | |
488 | ||
cb170a45 | 489 | tst r3, #PSR_T_BIT @ Thumb mode? |
15ac49b6 RK |
490 | bne __und_usr_thumb |
491 | sub r4, r2, #4 @ ARM instr at LR - 4 | |
492 | 1: ldrt r0, [r4] | |
457c2403 BD |
493 | ARM_BE8(rev r0, r0) @ little endian instruction |
494 | ||
2190fed6 RK |
495 | uaccess_disable ip |
496 | ||
15ac49b6 RK |
497 | @ r0 = 32-bit ARM instruction which caused the exception |
498 | @ r2 = PC value for the following instruction (:= regs->ARM_pc) | |
499 | @ r4 = PC value for the faulting instruction | |
500 | @ lr = 32-bit undefined instruction function | |
14327c66 | 501 | badr lr, __und_usr_fault_32 |
15ac49b6 RK |
502 | b call_fpe |
503 | ||
504 | __und_usr_thumb: | |
cb170a45 | 505 | @ Thumb instruction |
15ac49b6 | 506 | sub r4, r2, #2 @ First half of thumb instr at LR - 2 |
ef4c5368 DM |
507 | #if CONFIG_ARM_THUMB && __LINUX_ARM_ARCH__ >= 6 && CONFIG_CPU_V7 |
508 | /* | |
509 | * Thumb-2 instruction handling. Note that because pre-v6 and >= v6 platforms | |
510 | * can never be supported in a single kernel, this code is not applicable at | |
511 | * all when __LINUX_ARM_ARCH__ < 6. This allows simplifying assumptions to be | |
512 | * made about .arch directives. | |
513 | */ | |
514 | #if __LINUX_ARM_ARCH__ < 7 | |
515 | /* If the target CPU may not be Thumb-2-capable, a run-time check is needed: */ | |
516 | #define NEED_CPU_ARCHITECTURE | |
517 | ldr r5, .LCcpu_architecture | |
518 | ldr r5, [r5] | |
519 | cmp r5, #CPU_ARCH_ARMv7 | |
15ac49b6 | 520 | blo __und_usr_fault_16 @ 16bit undefined instruction |
ef4c5368 DM |
521 | /* |
522 | * The following code won't get run unless the running CPU really is v7, so | |
523 | * coding round the lack of ldrht on older arches is pointless. Temporarily | |
524 | * override the assembler target arch with the minimum required instead: | |
525 | */ | |
526 | .arch armv6t2 | |
527 | #endif | |
15ac49b6 | 528 | 2: ldrht r5, [r4] |
f8fe23ec | 529 | ARM_BE8(rev16 r5, r5) @ little endian instruction |
85519189 | 530 | cmp r5, #0xe800 @ 32bit instruction if xx != 0 |
2190fed6 | 531 | blo __und_usr_fault_16_pan @ 16bit undefined instruction |
15ac49b6 | 532 | 3: ldrht r0, [r2] |
f8fe23ec | 533 | ARM_BE8(rev16 r0, r0) @ little endian instruction |
2190fed6 | 534 | uaccess_disable ip |
cb170a45 | 535 | add r2, r2, #2 @ r2 is PC + 2, make it PC + 4 |
15ac49b6 | 536 | str r2, [sp, #S_PC] @ it's a 2x16bit instr, update |
cb170a45 | 537 | orr r0, r0, r5, lsl #16 |
14327c66 | 538 | badr lr, __und_usr_fault_32 |
15ac49b6 RK |
539 | @ r0 = the two 16-bit Thumb instructions which caused the exception |
540 | @ r2 = PC value for the following Thumb instruction (:= regs->ARM_pc) | |
541 | @ r4 = PC value for the first 16-bit Thumb instruction | |
542 | @ lr = 32bit undefined instruction function | |
ef4c5368 DM |
543 | |
544 | #if __LINUX_ARM_ARCH__ < 7 | |
545 | /* If the target arch was overridden, change it back: */ | |
546 | #ifdef CONFIG_CPU_32v6K | |
547 | .arch armv6k | |
cb170a45 | 548 | #else |
ef4c5368 DM |
549 | .arch armv6 |
550 | #endif | |
551 | #endif /* __LINUX_ARM_ARCH__ < 7 */ | |
552 | #else /* !(CONFIG_ARM_THUMB && __LINUX_ARM_ARCH__ >= 6 && CONFIG_CPU_V7) */ | |
15ac49b6 | 553 | b __und_usr_fault_16 |
cb170a45 | 554 | #endif |
15ac49b6 | 555 | UNWIND(.fnend) |
93ed3970 | 556 | ENDPROC(__und_usr) |
cb170a45 | 557 | |
1da177e4 | 558 | /* |
15ac49b6 | 559 | * The out of line fixup for the ldrt instructions above. |
1da177e4 | 560 | */ |
c4a84ae3 | 561 | .pushsection .text.fixup, "ax" |
667d1b48 | 562 | .align 2 |
3780f7ab | 563 | 4: str r4, [sp, #S_PC] @ retry current instruction |
6ebbf2ce | 564 | ret r9 |
4260415f RK |
565 | .popsection |
566 | .pushsection __ex_table,"a" | |
cb170a45 | 567 | .long 1b, 4b |
c89cefed | 568 | #if CONFIG_ARM_THUMB && __LINUX_ARM_ARCH__ >= 6 && CONFIG_CPU_V7 |
cb170a45 PB |
569 | .long 2b, 4b |
570 | .long 3b, 4b | |
571 | #endif | |
4260415f | 572 | .popsection |
1da177e4 LT |
573 | |
574 | /* | |
575 | * Check whether the instruction is a co-processor instruction. | |
576 | * If yes, we need to call the relevant co-processor handler. | |
577 | * | |
578 | * Note that we don't do a full check here for the co-processor | |
579 | * instructions; all instructions with bit 27 set are well | |
580 | * defined. The only instructions that should fault are the | |
581 | * co-processor instructions. However, we have to watch out | |
582 | * for the ARM6/ARM7 SWI bug. | |
583 | * | |
b5872db4 CM |
584 | * NEON is a special case that has to be handled here. Not all |
585 | * NEON instructions are co-processor instructions, so we have | |
586 | * to make a special case of checking for them. Plus, there's | |
587 | * five groups of them, so we have a table of mask/opcode pairs | |
588 | * to check against, and if any match then we branch off into the | |
589 | * NEON handler code. | |
590 | * | |
1da177e4 | 591 | * Emulators may wish to make use of the following registers: |
15ac49b6 RK |
592 | * r0 = instruction opcode (32-bit ARM or two 16-bit Thumb) |
593 | * r2 = PC value to resume execution after successful emulation | |
db6ccbb6 | 594 | * r9 = normal "successful" return address |
15ac49b6 | 595 | * r10 = this threads thread_info structure |
db6ccbb6 | 596 | * lr = unrecognised instruction return address |
1417a6b8 | 597 | * IRQs enabled, FIQs enabled. |
1da177e4 | 598 | */ |
cb170a45 PB |
599 | @ |
600 | @ Fall-through from Thumb-2 __und_usr | |
601 | @ | |
602 | #ifdef CONFIG_NEON | |
d3f79584 | 603 | get_thread_info r10 @ get current thread |
cb170a45 PB |
604 | adr r6, .LCneon_thumb_opcodes |
605 | b 2f | |
606 | #endif | |
1da177e4 | 607 | call_fpe: |
d3f79584 | 608 | get_thread_info r10 @ get current thread |
b5872db4 | 609 | #ifdef CONFIG_NEON |
cb170a45 | 610 | adr r6, .LCneon_arm_opcodes |
d3f79584 | 611 | 2: ldr r5, [r6], #4 @ mask value |
b5872db4 | 612 | ldr r7, [r6], #4 @ opcode bits matching in mask |
d3f79584 RK |
613 | cmp r5, #0 @ end mask? |
614 | beq 1f | |
615 | and r8, r0, r5 | |
b5872db4 CM |
616 | cmp r8, r7 @ NEON instruction? |
617 | bne 2b | |
b5872db4 CM |
618 | mov r7, #1 |
619 | strb r7, [r10, #TI_USED_CP + 10] @ mark CP#10 as used | |
620 | strb r7, [r10, #TI_USED_CP + 11] @ mark CP#11 as used | |
621 | b do_vfp @ let VFP handler handle this | |
622 | 1: | |
623 | #endif | |
1da177e4 | 624 | tst r0, #0x08000000 @ only CDP/CPRT/LDC/STC have bit 27 |
cb170a45 | 625 | tstne r0, #0x04000000 @ bit 26 set on both ARM and Thumb-2 |
6ebbf2ce | 626 | reteq lr |
1da177e4 | 627 | and r8, r0, #0x00000f00 @ mask out CP number |
b86040a5 | 628 | THUMB( lsr r8, r8, #8 ) |
1da177e4 LT |
629 | mov r7, #1 |
630 | add r6, r10, #TI_USED_CP | |
b86040a5 CM |
631 | ARM( strb r7, [r6, r8, lsr #8] ) @ set appropriate used_cp[] |
632 | THUMB( strb r7, [r6, r8] ) @ set appropriate used_cp[] | |
1da177e4 LT |
633 | #ifdef CONFIG_IWMMXT |
634 | @ Test if we need to give access to iWMMXt coprocessors | |
635 | ldr r5, [r10, #TI_FLAGS] | |
636 | rsbs r7, r8, #(1 << 8) @ CP 0 or 1 only | |
637 | movcss r7, r5, lsr #(TIF_USING_IWMMXT + 1) | |
638 | bcs iwmmxt_task_enable | |
639 | #endif | |
b86040a5 CM |
640 | ARM( add pc, pc, r8, lsr #6 ) |
641 | THUMB( lsl r8, r8, #2 ) | |
642 | THUMB( add pc, r8 ) | |
643 | nop | |
644 | ||
6ebbf2ce | 645 | ret.w lr @ CP#0 |
b86040a5 CM |
646 | W(b) do_fpe @ CP#1 (FPE) |
647 | W(b) do_fpe @ CP#2 (FPE) | |
6ebbf2ce | 648 | ret.w lr @ CP#3 |
c17fad11 LB |
649 | #ifdef CONFIG_CRUNCH |
650 | b crunch_task_enable @ CP#4 (MaverickCrunch) | |
651 | b crunch_task_enable @ CP#5 (MaverickCrunch) | |
652 | b crunch_task_enable @ CP#6 (MaverickCrunch) | |
653 | #else | |
6ebbf2ce RK |
654 | ret.w lr @ CP#4 |
655 | ret.w lr @ CP#5 | |
656 | ret.w lr @ CP#6 | |
c17fad11 | 657 | #endif |
6ebbf2ce RK |
658 | ret.w lr @ CP#7 |
659 | ret.w lr @ CP#8 | |
660 | ret.w lr @ CP#9 | |
1da177e4 | 661 | #ifdef CONFIG_VFP |
b86040a5 CM |
662 | W(b) do_vfp @ CP#10 (VFP) |
663 | W(b) do_vfp @ CP#11 (VFP) | |
1da177e4 | 664 | #else |
6ebbf2ce RK |
665 | ret.w lr @ CP#10 (VFP) |
666 | ret.w lr @ CP#11 (VFP) | |
1da177e4 | 667 | #endif |
6ebbf2ce RK |
668 | ret.w lr @ CP#12 |
669 | ret.w lr @ CP#13 | |
670 | ret.w lr @ CP#14 (Debug) | |
671 | ret.w lr @ CP#15 (Control) | |
1da177e4 | 672 | |
ef4c5368 DM |
673 | #ifdef NEED_CPU_ARCHITECTURE |
674 | .align 2 | |
675 | .LCcpu_architecture: | |
676 | .word __cpu_architecture | |
677 | #endif | |
678 | ||
b5872db4 CM |
679 | #ifdef CONFIG_NEON |
680 | .align 6 | |
681 | ||
cb170a45 | 682 | .LCneon_arm_opcodes: |
b5872db4 CM |
683 | .word 0xfe000000 @ mask |
684 | .word 0xf2000000 @ opcode | |
685 | ||
686 | .word 0xff100000 @ mask | |
687 | .word 0xf4000000 @ opcode | |
688 | ||
cb170a45 PB |
689 | .word 0x00000000 @ mask |
690 | .word 0x00000000 @ opcode | |
691 | ||
692 | .LCneon_thumb_opcodes: | |
693 | .word 0xef000000 @ mask | |
694 | .word 0xef000000 @ opcode | |
695 | ||
696 | .word 0xff100000 @ mask | |
697 | .word 0xf9000000 @ opcode | |
698 | ||
b5872db4 CM |
699 | .word 0x00000000 @ mask |
700 | .word 0x00000000 @ opcode | |
701 | #endif | |
702 | ||
1da177e4 LT |
703 | do_fpe: |
704 | ldr r4, .LCfp | |
705 | add r10, r10, #TI_FPSTATE @ r10 = workspace | |
706 | ldr pc, [r4] @ Call FP module USR entry point | |
707 | ||
708 | /* | |
709 | * The FP module is called with these registers set: | |
710 | * r0 = instruction | |
711 | * r2 = PC+4 | |
712 | * r9 = normal "successful" return address | |
713 | * r10 = FP workspace | |
714 | * lr = unrecognised FP instruction return address | |
715 | */ | |
716 | ||
124efc27 | 717 | .pushsection .data |
1da177e4 | 718 | ENTRY(fp_enter) |
db6ccbb6 | 719 | .word no_fp |
124efc27 | 720 | .popsection |
1da177e4 | 721 | |
83e686ea | 722 | ENTRY(no_fp) |
6ebbf2ce | 723 | ret lr |
83e686ea | 724 | ENDPROC(no_fp) |
db6ccbb6 | 725 | |
15ac49b6 RK |
726 | __und_usr_fault_32: |
727 | mov r1, #4 | |
728 | b 1f | |
2190fed6 RK |
729 | __und_usr_fault_16_pan: |
730 | uaccess_disable ip | |
15ac49b6 RK |
731 | __und_usr_fault_16: |
732 | mov r1, #2 | |
1417a6b8 | 733 | 1: mov r0, sp |
14327c66 | 734 | badr lr, ret_from_exception |
15ac49b6 RK |
735 | b __und_fault |
736 | ENDPROC(__und_usr_fault_32) | |
737 | ENDPROC(__und_usr_fault_16) | |
1da177e4 LT |
738 | |
739 | .align 5 | |
740 | __pabt_usr: | |
ccea7a19 | 741 | usr_entry |
4fb28474 | 742 | mov r2, sp @ regs |
8dfe7ac9 | 743 | pabt_helper |
c4c5716e | 744 | UNWIND(.fnend ) |
1da177e4 LT |
745 | /* fall through */ |
746 | /* | |
747 | * This is the return code to user mode for abort handlers | |
748 | */ | |
749 | ENTRY(ret_from_exception) | |
c4c5716e CM |
750 | UNWIND(.fnstart ) |
751 | UNWIND(.cantunwind ) | |
1da177e4 LT |
752 | get_thread_info tsk |
753 | mov why, #0 | |
754 | b ret_to_user | |
c4c5716e | 755 | UNWIND(.fnend ) |
93ed3970 CM |
756 | ENDPROC(__pabt_usr) |
757 | ENDPROC(ret_from_exception) | |
1da177e4 | 758 | |
c0e7f7ee DT |
759 | .align 5 |
760 | __fiq_usr: | |
761 | usr_entry trace=0 | |
762 | kuser_cmpxchg_check | |
763 | mov r0, sp @ struct pt_regs *regs | |
764 | bl handle_fiq_as_nmi | |
765 | get_thread_info tsk | |
766 | restore_user_regs fast = 0, offset = 0 | |
767 | UNWIND(.fnend ) | |
768 | ENDPROC(__fiq_usr) | |
769 | ||
1da177e4 LT |
770 | /* |
771 | * Register switch for ARMv3 and ARMv4 processors | |
772 | * r0 = previous task_struct, r1 = previous thread_info, r2 = next thread_info | |
773 | * previous and next are guaranteed not to be the same. | |
774 | */ | |
775 | ENTRY(__switch_to) | |
c4c5716e CM |
776 | UNWIND(.fnstart ) |
777 | UNWIND(.cantunwind ) | |
1da177e4 | 778 | add ip, r1, #TI_CPU_SAVE |
b86040a5 CM |
779 | ARM( stmia ip!, {r4 - sl, fp, sp, lr} ) @ Store most regs on stack |
780 | THUMB( stmia ip!, {r4 - sl, fp} ) @ Store most regs on stack | |
781 | THUMB( str sp, [ip], #4 ) | |
782 | THUMB( str lr, [ip], #4 ) | |
a4780ade AH |
783 | ldr r4, [r2, #TI_TP_VALUE] |
784 | ldr r5, [r2, #TI_TP_VALUE + 4] | |
247055aa | 785 | #ifdef CONFIG_CPU_USE_DOMAINS |
1eef5d2f RK |
786 | mrc p15, 0, r6, c3, c0, 0 @ Get domain register |
787 | str r6, [r1, #TI_CPU_DOMAIN] @ Save old domain register | |
d6551e88 | 788 | ldr r6, [r2, #TI_CPU_DOMAIN] |
afeb90ca | 789 | #endif |
a4780ade | 790 | switch_tls r1, r4, r5, r3, r7 |
df0698be NP |
791 | #if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP) |
792 | ldr r7, [r2, #TI_TASK] | |
793 | ldr r8, =__stack_chk_guard | |
794 | ldr r7, [r7, #TSK_STACK_CANARY] | |
795 | #endif | |
247055aa | 796 | #ifdef CONFIG_CPU_USE_DOMAINS |
1da177e4 | 797 | mcr p15, 0, r6, c3, c0, 0 @ Set domain register |
1da177e4 | 798 | #endif |
d6551e88 RK |
799 | mov r5, r0 |
800 | add r4, r2, #TI_CPU_SAVE | |
801 | ldr r0, =thread_notify_head | |
802 | mov r1, #THREAD_NOTIFY_SWITCH | |
803 | bl atomic_notifier_call_chain | |
df0698be NP |
804 | #if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP) |
805 | str r7, [r8] | |
806 | #endif | |
b86040a5 | 807 | THUMB( mov ip, r4 ) |
d6551e88 | 808 | mov r0, r5 |
b86040a5 CM |
809 | ARM( ldmia r4, {r4 - sl, fp, sp, pc} ) @ Load all regs saved previously |
810 | THUMB( ldmia ip!, {r4 - sl, fp} ) @ Load all regs saved previously | |
811 | THUMB( ldr sp, [ip], #4 ) | |
812 | THUMB( ldr pc, [ip] ) | |
c4c5716e | 813 | UNWIND(.fnend ) |
93ed3970 | 814 | ENDPROC(__switch_to) |
1da177e4 LT |
815 | |
816 | __INIT | |
2d2669b6 NP |
817 | |
818 | /* | |
819 | * User helpers. | |
820 | * | |
2d2669b6 NP |
821 | * Each segment is 32-byte aligned and will be moved to the top of the high |
822 | * vector page. New segments (if ever needed) must be added in front of | |
823 | * existing ones. This mechanism should be used only for things that are | |
824 | * really small and justified, and not be abused freely. | |
825 | * | |
37b83046 | 826 | * See Documentation/arm/kernel_user_helpers.txt for formal definitions. |
2d2669b6 | 827 | */ |
b86040a5 | 828 | THUMB( .arm ) |
2d2669b6 | 829 | |
ba9b5d76 NP |
830 | .macro usr_ret, reg |
831 | #ifdef CONFIG_ARM_THUMB | |
832 | bx \reg | |
833 | #else | |
6ebbf2ce | 834 | ret \reg |
ba9b5d76 NP |
835 | #endif |
836 | .endm | |
837 | ||
5b43e7a3 RK |
838 | .macro kuser_pad, sym, size |
839 | .if (. - \sym) & 3 | |
840 | .rept 4 - (. - \sym) & 3 | |
841 | .byte 0 | |
842 | .endr | |
843 | .endif | |
844 | .rept (\size - (. - \sym)) / 4 | |
845 | .word 0xe7fddef1 | |
846 | .endr | |
847 | .endm | |
848 | ||
f6f91b0d | 849 | #ifdef CONFIG_KUSER_HELPERS |
2d2669b6 NP |
850 | .align 5 |
851 | .globl __kuser_helper_start | |
852 | __kuser_helper_start: | |
853 | ||
7c612bfd | 854 | /* |
40fb79c8 NP |
855 | * Due to the length of some sequences, __kuser_cmpxchg64 spans 2 regular |
856 | * kuser "slots", therefore 0xffff0f80 is not used as a valid entry point. | |
7c612bfd NP |
857 | */ |
858 | ||
40fb79c8 NP |
859 | __kuser_cmpxchg64: @ 0xffff0f60 |
860 | ||
db695c05 | 861 | #if defined(CONFIG_CPU_32v6K) |
40fb79c8 NP |
862 | |
863 | stmfd sp!, {r4, r5, r6, r7} | |
864 | ldrd r4, r5, [r0] @ load old val | |
865 | ldrd r6, r7, [r1] @ load new val | |
866 | smp_dmb arm | |
867 | 1: ldrexd r0, r1, [r2] @ load current val | |
868 | eors r3, r0, r4 @ compare with oldval (1) | |
869 | eoreqs r3, r1, r5 @ compare with oldval (2) | |
870 | strexdeq r3, r6, r7, [r2] @ store newval if eq | |
871 | teqeq r3, #1 @ success? | |
872 | beq 1b @ if no then retry | |
ed3768a8 | 873 | smp_dmb arm |
40fb79c8 NP |
874 | rsbs r0, r3, #0 @ set returned val and C flag |
875 | ldmfd sp!, {r4, r5, r6, r7} | |
5a97d0ae | 876 | usr_ret lr |
40fb79c8 NP |
877 | |
878 | #elif !defined(CONFIG_SMP) | |
879 | ||
880 | #ifdef CONFIG_MMU | |
881 | ||
882 | /* | |
883 | * The only thing that can break atomicity in this cmpxchg64 | |
884 | * implementation is either an IRQ or a data abort exception | |
885 | * causing another process/thread to be scheduled in the middle of | |
886 | * the critical sequence. The same strategy as for cmpxchg is used. | |
887 | */ | |
888 | stmfd sp!, {r4, r5, r6, lr} | |
889 | ldmia r0, {r4, r5} @ load old val | |
890 | ldmia r1, {r6, lr} @ load new val | |
891 | 1: ldmia r2, {r0, r1} @ load current val | |
892 | eors r3, r0, r4 @ compare with oldval (1) | |
893 | eoreqs r3, r1, r5 @ compare with oldval (2) | |
894 | 2: stmeqia r2, {r6, lr} @ store newval if eq | |
895 | rsbs r0, r3, #0 @ set return val and C flag | |
896 | ldmfd sp!, {r4, r5, r6, pc} | |
897 | ||
898 | .text | |
899 | kuser_cmpxchg64_fixup: | |
900 | @ Called from kuser_cmpxchg_fixup. | |
3ad55155 | 901 | @ r4 = address of interrupted insn (must be preserved). |
40fb79c8 NP |
902 | @ sp = saved regs. r7 and r8 are clobbered. |
903 | @ 1b = first critical insn, 2b = last critical insn. | |
3ad55155 | 904 | @ If r4 >= 1b and r4 <= 2b then saved pc_usr is set to 1b. |
40fb79c8 NP |
905 | mov r7, #0xffff0fff |
906 | sub r7, r7, #(0xffff0fff - (0xffff0f60 + (1b - __kuser_cmpxchg64))) | |
3ad55155 | 907 | subs r8, r4, r7 |
40fb79c8 NP |
908 | rsbcss r8, r8, #(2b - 1b) |
909 | strcs r7, [sp, #S_PC] | |
910 | #if __LINUX_ARM_ARCH__ < 6 | |
911 | bcc kuser_cmpxchg32_fixup | |
912 | #endif | |
6ebbf2ce | 913 | ret lr |
40fb79c8 NP |
914 | .previous |
915 | ||
916 | #else | |
917 | #warning "NPTL on non MMU needs fixing" | |
918 | mov r0, #-1 | |
919 | adds r0, r0, #0 | |
ba9b5d76 | 920 | usr_ret lr |
40fb79c8 NP |
921 | #endif |
922 | ||
923 | #else | |
924 | #error "incoherent kernel configuration" | |
925 | #endif | |
926 | ||
5b43e7a3 | 927 | kuser_pad __kuser_cmpxchg64, 64 |
7c612bfd | 928 | |
7c612bfd | 929 | __kuser_memory_barrier: @ 0xffff0fa0 |
ed3768a8 | 930 | smp_dmb arm |
ba9b5d76 | 931 | usr_ret lr |
7c612bfd | 932 | |
5b43e7a3 | 933 | kuser_pad __kuser_memory_barrier, 32 |
2d2669b6 NP |
934 | |
935 | __kuser_cmpxchg: @ 0xffff0fc0 | |
936 | ||
db695c05 | 937 | #if __LINUX_ARM_ARCH__ < 6 |
2d2669b6 | 938 | |
b49c0f24 NP |
939 | #ifdef CONFIG_MMU |
940 | ||
2d2669b6 | 941 | /* |
b49c0f24 NP |
942 | * The only thing that can break atomicity in this cmpxchg |
943 | * implementation is either an IRQ or a data abort exception | |
944 | * causing another process/thread to be scheduled in the middle | |
945 | * of the critical sequence. To prevent this, code is added to | |
946 | * the IRQ and data abort exception handlers to set the pc back | |
947 | * to the beginning of the critical section if it is found to be | |
948 | * within that critical section (see kuser_cmpxchg_fixup). | |
2d2669b6 | 949 | */ |
b49c0f24 NP |
950 | 1: ldr r3, [r2] @ load current val |
951 | subs r3, r3, r0 @ compare with oldval | |
952 | 2: streq r1, [r2] @ store newval if eq | |
953 | rsbs r0, r3, #0 @ set return val and C flag | |
954 | usr_ret lr | |
955 | ||
956 | .text | |
40fb79c8 | 957 | kuser_cmpxchg32_fixup: |
b49c0f24 | 958 | @ Called from kuser_cmpxchg_check macro. |
b059bdc3 | 959 | @ r4 = address of interrupted insn (must be preserved). |
b49c0f24 NP |
960 | @ sp = saved regs. r7 and r8 are clobbered. |
961 | @ 1b = first critical insn, 2b = last critical insn. | |
b059bdc3 | 962 | @ If r4 >= 1b and r4 <= 2b then saved pc_usr is set to 1b. |
b49c0f24 NP |
963 | mov r7, #0xffff0fff |
964 | sub r7, r7, #(0xffff0fff - (0xffff0fc0 + (1b - __kuser_cmpxchg))) | |
b059bdc3 | 965 | subs r8, r4, r7 |
b49c0f24 NP |
966 | rsbcss r8, r8, #(2b - 1b) |
967 | strcs r7, [sp, #S_PC] | |
6ebbf2ce | 968 | ret lr |
b49c0f24 NP |
969 | .previous |
970 | ||
49bca4c2 NP |
971 | #else |
972 | #warning "NPTL on non MMU needs fixing" | |
973 | mov r0, #-1 | |
974 | adds r0, r0, #0 | |
ba9b5d76 | 975 | usr_ret lr |
b49c0f24 | 976 | #endif |
2d2669b6 NP |
977 | |
978 | #else | |
979 | ||
ed3768a8 | 980 | smp_dmb arm |
b49c0f24 | 981 | 1: ldrex r3, [r2] |
2d2669b6 NP |
982 | subs r3, r3, r0 |
983 | strexeq r3, r1, [r2] | |
b49c0f24 NP |
984 | teqeq r3, #1 |
985 | beq 1b | |
2d2669b6 | 986 | rsbs r0, r3, #0 |
b49c0f24 | 987 | /* beware -- each __kuser slot must be 8 instructions max */ |
f00ec48f RK |
988 | ALT_SMP(b __kuser_memory_barrier) |
989 | ALT_UP(usr_ret lr) | |
2d2669b6 NP |
990 | |
991 | #endif | |
992 | ||
5b43e7a3 | 993 | kuser_pad __kuser_cmpxchg, 32 |
2d2669b6 | 994 | |
2d2669b6 | 995 | __kuser_get_tls: @ 0xffff0fe0 |
f159f4ed | 996 | ldr r0, [pc, #(16 - 8)] @ read TLS, set in kuser_get_tls_init |
ba9b5d76 | 997 | usr_ret lr |
f159f4ed | 998 | mrc p15, 0, r0, c13, c0, 3 @ 0xffff0fe8 hardware TLS code |
5b43e7a3 RK |
999 | kuser_pad __kuser_get_tls, 16 |
1000 | .rep 3 | |
f159f4ed TL |
1001 | .word 0 @ 0xffff0ff0 software TLS value, then |
1002 | .endr @ pad up to __kuser_helper_version | |
2d2669b6 | 1003 | |
2d2669b6 NP |
1004 | __kuser_helper_version: @ 0xffff0ffc |
1005 | .word ((__kuser_helper_end - __kuser_helper_start) >> 5) | |
1006 | ||
1007 | .globl __kuser_helper_end | |
1008 | __kuser_helper_end: | |
1009 | ||
f6f91b0d RK |
1010 | #endif |
1011 | ||
b86040a5 | 1012 | THUMB( .thumb ) |
2d2669b6 | 1013 | |
1da177e4 LT |
1014 | /* |
1015 | * Vector stubs. | |
1016 | * | |
19accfd3 RK |
1017 | * This code is copied to 0xffff1000 so we can use branches in the |
1018 | * vectors, rather than ldr's. Note that this code must not exceed | |
1019 | * a page size. | |
1da177e4 LT |
1020 | * |
1021 | * Common stub entry macro: | |
1022 | * Enter in IRQ mode, spsr = SVC/USR CPSR, lr = SVC/USR PC | |
ccea7a19 RK |
1023 | * |
1024 | * SP points to a minimal amount of processor-private memory, the address | |
1025 | * of which is copied into r0 for the mode specific abort handler. | |
1da177e4 | 1026 | */ |
b7ec4795 | 1027 | .macro vector_stub, name, mode, correction=0 |
1da177e4 LT |
1028 | .align 5 |
1029 | ||
1030 | vector_\name: | |
1da177e4 LT |
1031 | .if \correction |
1032 | sub lr, lr, #\correction | |
1033 | .endif | |
ccea7a19 RK |
1034 | |
1035 | @ | |
1036 | @ Save r0, lr_<exception> (parent PC) and spsr_<exception> | |
1037 | @ (parent CPSR) | |
1038 | @ | |
1039 | stmia sp, {r0, lr} @ save r0, lr | |
1da177e4 | 1040 | mrs lr, spsr |
ccea7a19 RK |
1041 | str lr, [sp, #8] @ save spsr |
1042 | ||
1da177e4 | 1043 | @ |
ccea7a19 | 1044 | @ Prepare for SVC32 mode. IRQs remain disabled. |
1da177e4 | 1045 | @ |
ccea7a19 | 1046 | mrs r0, cpsr |
b86040a5 | 1047 | eor r0, r0, #(\mode ^ SVC_MODE | PSR_ISETSTATE) |
ccea7a19 | 1048 | msr spsr_cxsf, r0 |
1da177e4 | 1049 | |
ccea7a19 RK |
1050 | @ |
1051 | @ the branch table must immediately follow this code | |
1052 | @ | |
ccea7a19 | 1053 | and lr, lr, #0x0f |
b86040a5 CM |
1054 | THUMB( adr r0, 1f ) |
1055 | THUMB( ldr lr, [r0, lr, lsl #2] ) | |
b7ec4795 | 1056 | mov r0, sp |
b86040a5 | 1057 | ARM( ldr lr, [pc, lr, lsl #2] ) |
ccea7a19 | 1058 | movs pc, lr @ branch to handler in SVC mode |
93ed3970 | 1059 | ENDPROC(vector_\name) |
88987ef9 CM |
1060 | |
1061 | .align 2 | |
1062 | @ handler addresses follow this label | |
1063 | 1: | |
1da177e4 LT |
1064 | .endm |
1065 | ||
b9b32bf7 | 1066 | .section .stubs, "ax", %progbits |
19accfd3 RK |
1067 | @ This must be the first word |
1068 | .word vector_swi | |
1069 | ||
1070 | vector_rst: | |
1071 | ARM( swi SYS_ERROR0 ) | |
1072 | THUMB( svc #0 ) | |
1073 | THUMB( nop ) | |
1074 | b vector_und | |
1075 | ||
1da177e4 LT |
1076 | /* |
1077 | * Interrupt dispatcher | |
1078 | */ | |
b7ec4795 | 1079 | vector_stub irq, IRQ_MODE, 4 |
1da177e4 LT |
1080 | |
1081 | .long __irq_usr @ 0 (USR_26 / USR_32) | |
1082 | .long __irq_invalid @ 1 (FIQ_26 / FIQ_32) | |
1083 | .long __irq_invalid @ 2 (IRQ_26 / IRQ_32) | |
1084 | .long __irq_svc @ 3 (SVC_26 / SVC_32) | |
1085 | .long __irq_invalid @ 4 | |
1086 | .long __irq_invalid @ 5 | |
1087 | .long __irq_invalid @ 6 | |
1088 | .long __irq_invalid @ 7 | |
1089 | .long __irq_invalid @ 8 | |
1090 | .long __irq_invalid @ 9 | |
1091 | .long __irq_invalid @ a | |
1092 | .long __irq_invalid @ b | |
1093 | .long __irq_invalid @ c | |
1094 | .long __irq_invalid @ d | |
1095 | .long __irq_invalid @ e | |
1096 | .long __irq_invalid @ f | |
1097 | ||
1098 | /* | |
1099 | * Data abort dispatcher | |
1100 | * Enter in ABT mode, spsr = USR CPSR, lr = USR PC | |
1101 | */ | |
b7ec4795 | 1102 | vector_stub dabt, ABT_MODE, 8 |
1da177e4 LT |
1103 | |
1104 | .long __dabt_usr @ 0 (USR_26 / USR_32) | |
1105 | .long __dabt_invalid @ 1 (FIQ_26 / FIQ_32) | |
1106 | .long __dabt_invalid @ 2 (IRQ_26 / IRQ_32) | |
1107 | .long __dabt_svc @ 3 (SVC_26 / SVC_32) | |
1108 | .long __dabt_invalid @ 4 | |
1109 | .long __dabt_invalid @ 5 | |
1110 | .long __dabt_invalid @ 6 | |
1111 | .long __dabt_invalid @ 7 | |
1112 | .long __dabt_invalid @ 8 | |
1113 | .long __dabt_invalid @ 9 | |
1114 | .long __dabt_invalid @ a | |
1115 | .long __dabt_invalid @ b | |
1116 | .long __dabt_invalid @ c | |
1117 | .long __dabt_invalid @ d | |
1118 | .long __dabt_invalid @ e | |
1119 | .long __dabt_invalid @ f | |
1120 | ||
1121 | /* | |
1122 | * Prefetch abort dispatcher | |
1123 | * Enter in ABT mode, spsr = USR CPSR, lr = USR PC | |
1124 | */ | |
b7ec4795 | 1125 | vector_stub pabt, ABT_MODE, 4 |
1da177e4 LT |
1126 | |
1127 | .long __pabt_usr @ 0 (USR_26 / USR_32) | |
1128 | .long __pabt_invalid @ 1 (FIQ_26 / FIQ_32) | |
1129 | .long __pabt_invalid @ 2 (IRQ_26 / IRQ_32) | |
1130 | .long __pabt_svc @ 3 (SVC_26 / SVC_32) | |
1131 | .long __pabt_invalid @ 4 | |
1132 | .long __pabt_invalid @ 5 | |
1133 | .long __pabt_invalid @ 6 | |
1134 | .long __pabt_invalid @ 7 | |
1135 | .long __pabt_invalid @ 8 | |
1136 | .long __pabt_invalid @ 9 | |
1137 | .long __pabt_invalid @ a | |
1138 | .long __pabt_invalid @ b | |
1139 | .long __pabt_invalid @ c | |
1140 | .long __pabt_invalid @ d | |
1141 | .long __pabt_invalid @ e | |
1142 | .long __pabt_invalid @ f | |
1143 | ||
1144 | /* | |
1145 | * Undef instr entry dispatcher | |
1146 | * Enter in UND mode, spsr = SVC/USR CPSR, lr = SVC/USR PC | |
1147 | */ | |
b7ec4795 | 1148 | vector_stub und, UND_MODE |
1da177e4 LT |
1149 | |
1150 | .long __und_usr @ 0 (USR_26 / USR_32) | |
1151 | .long __und_invalid @ 1 (FIQ_26 / FIQ_32) | |
1152 | .long __und_invalid @ 2 (IRQ_26 / IRQ_32) | |
1153 | .long __und_svc @ 3 (SVC_26 / SVC_32) | |
1154 | .long __und_invalid @ 4 | |
1155 | .long __und_invalid @ 5 | |
1156 | .long __und_invalid @ 6 | |
1157 | .long __und_invalid @ 7 | |
1158 | .long __und_invalid @ 8 | |
1159 | .long __und_invalid @ 9 | |
1160 | .long __und_invalid @ a | |
1161 | .long __und_invalid @ b | |
1162 | .long __und_invalid @ c | |
1163 | .long __und_invalid @ d | |
1164 | .long __und_invalid @ e | |
1165 | .long __und_invalid @ f | |
1166 | ||
1167 | .align 5 | |
1168 | ||
19accfd3 RK |
1169 | /*============================================================================= |
1170 | * Address exception handler | |
1171 | *----------------------------------------------------------------------------- | |
1172 | * These aren't too critical. | |
1173 | * (they're not supposed to happen, and won't happen in 32-bit data mode). | |
1174 | */ | |
1175 | ||
1176 | vector_addrexcptn: | |
1177 | b vector_addrexcptn | |
1178 | ||
1da177e4 | 1179 | /*============================================================================= |
c0e7f7ee | 1180 | * FIQ "NMI" handler |
1da177e4 | 1181 | *----------------------------------------------------------------------------- |
c0e7f7ee DT |
1182 | * Handle a FIQ using the SVC stack allowing FIQ act like NMI on x86 |
1183 | * systems. | |
1da177e4 | 1184 | */ |
c0e7f7ee DT |
1185 | vector_stub fiq, FIQ_MODE, 4 |
1186 | ||
1187 | .long __fiq_usr @ 0 (USR_26 / USR_32) | |
1188 | .long __fiq_svc @ 1 (FIQ_26 / FIQ_32) | |
1189 | .long __fiq_svc @ 2 (IRQ_26 / IRQ_32) | |
1190 | .long __fiq_svc @ 3 (SVC_26 / SVC_32) | |
1191 | .long __fiq_svc @ 4 | |
1192 | .long __fiq_svc @ 5 | |
1193 | .long __fiq_svc @ 6 | |
1194 | .long __fiq_abt @ 7 | |
1195 | .long __fiq_svc @ 8 | |
1196 | .long __fiq_svc @ 9 | |
1197 | .long __fiq_svc @ a | |
1198 | .long __fiq_svc @ b | |
1199 | .long __fiq_svc @ c | |
1200 | .long __fiq_svc @ d | |
1201 | .long __fiq_svc @ e | |
1202 | .long __fiq_svc @ f | |
1da177e4 | 1203 | |
31b96cae | 1204 | .globl vector_fiq |
e39e3f3e | 1205 | |
b9b32bf7 | 1206 | .section .vectors, "ax", %progbits |
b48da558 | 1207 | .L__vectors_start: |
b9b32bf7 RK |
1208 | W(b) vector_rst |
1209 | W(b) vector_und | |
b48da558 | 1210 | W(ldr) pc, .L__vectors_start + 0x1000 |
b9b32bf7 RK |
1211 | W(b) vector_pabt |
1212 | W(b) vector_dabt | |
1213 | W(b) vector_addrexcptn | |
1214 | W(b) vector_irq | |
1215 | W(b) vector_fiq | |
1da177e4 LT |
1216 | |
1217 | .data | |
1218 | ||
1da177e4 | 1219 | .globl cr_alignment |
1da177e4 LT |
1220 | cr_alignment: |
1221 | .space 4 | |
52108641 | 1222 | |
1223 | #ifdef CONFIG_MULTI_IRQ_HANDLER | |
1224 | .globl handle_arch_irq | |
1225 | handle_arch_irq: | |
1226 | .space 4 | |
1227 | #endif |