Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * linux/arch/arm/kernel/head.S | |
3 | * | |
4 | * Copyright (C) 1994-2002 Russell King | |
e65f38ed RK |
5 | * Copyright (c) 2003 ARM Limited |
6 | * All Rights Reserved | |
1da177e4 LT |
7 | * |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * Kernel startup code for all 32-bit CPUs | |
13 | */ | |
1da177e4 LT |
14 | #include <linux/linkage.h> |
15 | #include <linux/init.h> | |
16 | ||
17 | #include <asm/assembler.h> | |
195864cf | 18 | #include <asm/cp15.h> |
1da177e4 | 19 | #include <asm/domain.h> |
1da177e4 | 20 | #include <asm/ptrace.h> |
e6ae744d | 21 | #include <asm/asm-offsets.h> |
f09b9979 | 22 | #include <asm/memory.h> |
4f7a1812 | 23 | #include <asm/thread_info.h> |
e73fc88e | 24 | #include <asm/pgtable.h> |
4dd1837d | 25 | #include <asm/export.h> |
1da177e4 | 26 | |
91a9fec0 RH |
27 | #if defined(CONFIG_DEBUG_LL) && !defined(CONFIG_DEBUG_SEMIHOSTING) |
28 | #include CONFIG_DEBUG_LL_INCLUDE | |
c293393f JK |
29 | #endif |
30 | ||
1da177e4 | 31 | /* |
37d07b72 | 32 | * swapper_pg_dir is the virtual address of the initial page table. |
f06b97ff RK |
33 | * We place the page tables 16K below KERNEL_RAM_VADDR. Therefore, we must |
34 | * make sure that KERNEL_RAM_VADDR is correctly set. Currently, we expect | |
37d07b72 | 35 | * the least significant 16 bits to be 0x8000, but we could probably |
f06b97ff | 36 | * relax this restriction to KERNEL_RAM_VADDR >= PAGE_OFFSET + 0x4000. |
1da177e4 | 37 | */ |
72a20e22 | 38 | #define KERNEL_RAM_VADDR (PAGE_OFFSET + TEXT_OFFSET) |
f06b97ff RK |
39 | #if (KERNEL_RAM_VADDR & 0xffff) != 0x8000 |
40 | #error KERNEL_RAM_VADDR must start at 0xXXXX8000 | |
1da177e4 LT |
41 | #endif |
42 | ||
1b6ba46b CM |
43 | #ifdef CONFIG_ARM_LPAE |
44 | /* LPAE requires an additional page for the PGD */ | |
45 | #define PG_DIR_SIZE 0x5000 | |
46 | #define PMD_ORDER 3 | |
47 | #else | |
e73fc88e CM |
48 | #define PG_DIR_SIZE 0x4000 |
49 | #define PMD_ORDER 2 | |
1b6ba46b | 50 | #endif |
e73fc88e | 51 | |
1da177e4 | 52 | .globl swapper_pg_dir |
e73fc88e | 53 | .equ swapper_pg_dir, KERNEL_RAM_VADDR - PG_DIR_SIZE |
1da177e4 | 54 | |
72a20e22 | 55 | .macro pgtbl, rd, phys |
2ab4e8c0 CC |
56 | add \rd, \phys, #TEXT_OFFSET |
57 | sub \rd, \rd, #PG_DIR_SIZE | |
1da177e4 | 58 | .endm |
1da177e4 | 59 | |
1da177e4 LT |
60 | /* |
61 | * Kernel startup entry point. | |
62 | * --------------------------- | |
63 | * | |
64 | * This is normally called from the decompressor code. The requirements | |
65 | * are: MMU = off, D-cache = off, I-cache = dont care, r0 = 0, | |
4c2896e8 | 66 | * r1 = machine nr, r2 = atags or dtb pointer. |
1da177e4 LT |
67 | * |
68 | * This code is mostly position independent, so if you link the kernel at | |
69 | * 0xc0008000, you call this at __pa(0xc0008000). | |
70 | * | |
71 | * See linux/arch/arm/tools/mach-types for the complete list of machine | |
72 | * numbers for r1. | |
73 | * | |
74 | * We're trying to keep crap to a minimum; DO NOT add any machine specific | |
75 | * crap here - that's what the boot loader (or in extreme, well justified | |
76 | * circumstances, zImage) is for. | |
77 | */ | |
540b5738 DM |
78 | .arm |
79 | ||
2abc1c50 | 80 | __HEAD |
1da177e4 | 81 | ENTRY(stext) |
97bcb0fe | 82 | ARM_BE8(setend be ) @ ensure we are in BE8 mode |
540b5738 | 83 | |
14327c66 | 84 | THUMB( badr r9, 1f ) @ Kernel is always entered in ARM. |
540b5738 DM |
85 | THUMB( bx r9 ) @ If this is a Thumb-2 kernel, |
86 | THUMB( .thumb ) @ switch to Thumb now. | |
87 | THUMB(1: ) | |
88 | ||
80c59daf DM |
89 | #ifdef CONFIG_ARM_VIRT_EXT |
90 | bl __hyp_stub_install | |
91 | #endif | |
92 | @ ensure svc mode and all interrupts masked | |
93 | safe_svcmode_maskall r9 | |
94 | ||
0f44ba1d | 95 | mrc p15, 0, r9, c0, c0 @ get processor id |
1da177e4 LT |
96 | bl __lookup_processor_type @ r5=procinfo r9=cpuid |
97 | movs r10, r5 @ invalid processor (r5=0)? | |
a75e5248 | 98 | THUMB( it eq ) @ force fixup-able long branch encoding |
3c0bdac3 | 99 | beq __error_p @ yes, error 'p' |
0eb0511d | 100 | |
294064f5 CM |
101 | #ifdef CONFIG_ARM_LPAE |
102 | mrc p15, 0, r3, c0, c1, 4 @ read ID_MMFR0 | |
103 | and r3, r3, #0xf @ extract VMSA support | |
104 | cmp r3, #5 @ long-descriptor translation table format? | |
105 | THUMB( it lo ) @ force fixup-able long branch encoding | |
b3634575 | 106 | blo __error_lpae @ only classic page table format |
294064f5 CM |
107 | #endif |
108 | ||
72a20e22 RK |
109 | #ifndef CONFIG_XIP_KERNEL |
110 | adr r3, 2f | |
111 | ldmia r3, {r4, r8} | |
112 | sub r4, r3, r4 @ (PHYS_OFFSET - PAGE_OFFSET) | |
113 | add r8, r8, r4 @ PHYS_OFFSET | |
114 | #else | |
b713aa0b | 115 | ldr r8, =PLAT_PHYS_OFFSET @ always constant in this case |
72a20e22 RK |
116 | #endif |
117 | ||
0eb0511d | 118 | /* |
4c2896e8 | 119 | * r1 = machine no, r2 = atags or dtb, |
72a20e22 | 120 | * r8 = phys_offset, r9 = cpuid, r10 = procinfo |
0eb0511d | 121 | */ |
9d20fdd5 | 122 | bl __vet_atags |
f00ec48f RK |
123 | #ifdef CONFIG_SMP_ON_UP |
124 | bl __fixup_smp | |
dc21af99 RK |
125 | #endif |
126 | #ifdef CONFIG_ARM_PATCH_PHYS_VIRT | |
127 | bl __fixup_pv_table | |
f00ec48f | 128 | #endif |
1da177e4 LT |
129 | bl __create_page_tables |
130 | ||
131 | /* | |
132 | * The following calls CPU specific code in a position independent | |
133 | * manner. See arch/arm/mm/proc-*.S for details. r10 = base of | |
6fc31d54 | 134 | * xxx_proc_info structure selected by __lookup_processor_type |
b2c3e38a RK |
135 | * above. |
136 | * | |
137 | * The processor init function will be called with: | |
138 | * r1 - machine type | |
139 | * r2 - boot data (atags/dt) pointer | |
140 | * r4 - translation table base (low word) | |
141 | * r5 - translation table base (high word, if LPAE) | |
142 | * r8 - translation table base 1 (pfn if LPAE) | |
143 | * r9 - cpuid | |
144 | * r13 - virtual address for __enable_mmu -> __turn_mmu_on | |
145 | * | |
146 | * On return, the CPU will be ready for the MMU to be turned on, | |
147 | * r0 will hold the CPU control register value, r1, r2, r4, and | |
148 | * r9 will be preserved. r5 will also be preserved if LPAE. | |
1da177e4 | 149 | */ |
a4ae4134 | 150 | ldr r13, =__mmap_switched @ address to jump to after |
1da177e4 | 151 | @ mmu has been enabled |
14327c66 | 152 | badr lr, 1f @ return (PIC) address |
b2c3e38a RK |
153 | #ifdef CONFIG_ARM_LPAE |
154 | mov r5, #0 @ high TTBR0 | |
155 | mov r8, r4, lsr #12 @ TTBR1 is swapper_pg_dir pfn | |
156 | #else | |
d427958a | 157 | mov r8, r4 @ set TTBR1 to swapper_pg_dir |
b2c3e38a | 158 | #endif |
bf35706f AB |
159 | ldr r12, [r10, #PROCINFO_INITFUNC] |
160 | add r12, r12, r10 | |
161 | ret r12 | |
00945010 | 162 | 1: b __enable_mmu |
93ed3970 | 163 | ENDPROC(stext) |
a4ae4134 | 164 | .ltorg |
72a20e22 RK |
165 | #ifndef CONFIG_XIP_KERNEL |
166 | 2: .long . | |
167 | .long PAGE_OFFSET | |
168 | #endif | |
1da177e4 LT |
169 | |
170 | /* | |
171 | * Setup the initial page tables. We only setup the barest | |
172 | * amount which are required to get the kernel running, which | |
173 | * generally means mapping in the kernel code. | |
174 | * | |
72a20e22 | 175 | * r8 = phys_offset, r9 = cpuid, r10 = procinfo |
1da177e4 LT |
176 | * |
177 | * Returns: | |
786f1b73 | 178 | * r0, r3, r5-r7 corrupted |
b2c3e38a | 179 | * r4 = physical page table address |
1da177e4 | 180 | */ |
1da177e4 | 181 | __create_page_tables: |
72a20e22 | 182 | pgtbl r4, r8 @ page table address |
1da177e4 LT |
183 | |
184 | /* | |
e73fc88e | 185 | * Clear the swapper page table |
1da177e4 LT |
186 | */ |
187 | mov r0, r4 | |
188 | mov r3, #0 | |
e73fc88e | 189 | add r6, r0, #PG_DIR_SIZE |
1da177e4 LT |
190 | 1: str r3, [r0], #4 |
191 | str r3, [r0], #4 | |
192 | str r3, [r0], #4 | |
193 | str r3, [r0], #4 | |
194 | teq r0, r6 | |
195 | bne 1b | |
196 | ||
1b6ba46b CM |
197 | #ifdef CONFIG_ARM_LPAE |
198 | /* | |
199 | * Build the PGD table (first level) to point to the PMD table. A PGD | |
200 | * entry is 64-bit wide. | |
201 | */ | |
202 | mov r0, r4 | |
203 | add r3, r4, #0x1000 @ first PMD table address | |
204 | orr r3, r3, #3 @ PGD block type | |
205 | mov r6, #4 @ PTRS_PER_PGD | |
206 | mov r7, #1 << (55 - 32) @ L_PGD_SWAPPER | |
d61947a1 WD |
207 | 1: |
208 | #ifdef CONFIG_CPU_ENDIAN_BE8 | |
1b6ba46b | 209 | str r7, [r0], #4 @ set top PGD entry bits |
d61947a1 WD |
210 | str r3, [r0], #4 @ set bottom PGD entry bits |
211 | #else | |
212 | str r3, [r0], #4 @ set bottom PGD entry bits | |
213 | str r7, [r0], #4 @ set top PGD entry bits | |
214 | #endif | |
1b6ba46b CM |
215 | add r3, r3, #0x1000 @ next PMD table |
216 | subs r6, r6, #1 | |
217 | bne 1b | |
218 | ||
219 | add r4, r4, #0x1000 @ point to the PMD tables | |
d61947a1 WD |
220 | #ifdef CONFIG_CPU_ENDIAN_BE8 |
221 | add r4, r4, #4 @ we only write the bottom word | |
222 | #endif | |
1b6ba46b CM |
223 | #endif |
224 | ||
8799ee9f | 225 | ldr r7, [r10, #PROCINFO_MM_MMUFLAGS] @ mm_mmuflags |
1da177e4 LT |
226 | |
227 | /* | |
786f1b73 RK |
228 | * Create identity mapping to cater for __enable_mmu. |
229 | * This identity mapping will be removed by paging_init(). | |
1da177e4 | 230 | */ |
72662e01 | 231 | adr r0, __turn_mmu_on_loc |
786f1b73 RK |
232 | ldmia r0, {r3, r5, r6} |
233 | sub r0, r0, r3 @ virt->phys offset | |
72662e01 WD |
234 | add r5, r5, r0 @ phys __turn_mmu_on |
235 | add r6, r6, r0 @ phys __turn_mmu_on_end | |
e73fc88e CM |
236 | mov r5, r5, lsr #SECTION_SHIFT |
237 | mov r6, r6, lsr #SECTION_SHIFT | |
786f1b73 | 238 | |
e73fc88e CM |
239 | 1: orr r3, r7, r5, lsl #SECTION_SHIFT @ flags + kernel base |
240 | str r3, [r4, r5, lsl #PMD_ORDER] @ identity mapping | |
241 | cmp r5, r6 | |
242 | addlo r5, r5, #1 @ next section | |
243 | blo 1b | |
1da177e4 LT |
244 | |
245 | /* | |
9fa16b77 | 246 | * Map our RAM from the start to the end of the kernel .bss section. |
1da177e4 | 247 | */ |
9fa16b77 NP |
248 | add r0, r4, #PAGE_OFFSET >> (SECTION_SHIFT - PMD_ORDER) |
249 | ldr r6, =(_end - 1) | |
250 | orr r3, r8, r7 | |
e73fc88e | 251 | add r6, r4, r6, lsr #(SECTION_SHIFT - PMD_ORDER) |
9fa16b77 | 252 | 1: str r3, [r0], #1 << PMD_ORDER |
e73fc88e | 253 | add r3, r3, #1 << SECTION_SHIFT |
9fa16b77 | 254 | cmp r0, r6 |
e98ff7f6 | 255 | bls 1b |
1da177e4 | 256 | |
ec3622d9 NP |
257 | #ifdef CONFIG_XIP_KERNEL |
258 | /* | |
9fa16b77 | 259 | * Map the kernel image separately as it is not located in RAM. |
ec3622d9 | 260 | */ |
9fa16b77 NP |
261 | #define XIP_START XIP_VIRT_ADDR(CONFIG_XIP_PHYS_ADDR) |
262 | mov r3, pc | |
263 | mov r3, r3, lsr #SECTION_SHIFT | |
264 | orr r3, r7, r3, lsl #SECTION_SHIFT | |
265 | add r0, r4, #(XIP_START & 0xff000000) >> (SECTION_SHIFT - PMD_ORDER) | |
266 | str r3, [r0, #((XIP_START & 0x00f00000) >> SECTION_SHIFT) << PMD_ORDER]! | |
267 | ldr r6, =(_edata_loc - 1) | |
268 | add r0, r0, #1 << PMD_ORDER | |
e73fc88e | 269 | add r6, r4, r6, lsr #(SECTION_SHIFT - PMD_ORDER) |
ec3622d9 | 270 | 1: cmp r0, r6 |
9fa16b77 NP |
271 | add r3, r3, #1 << SECTION_SHIFT |
272 | strls r3, [r0], #1 << PMD_ORDER | |
ec3622d9 NP |
273 | bls 1b |
274 | #endif | |
275 | ||
1da177e4 | 276 | /* |
9fa16b77 | 277 | * Then map boot params address in r2 if specified. |
6f16f499 | 278 | * We map 2 sections in case the ATAGs/DTB crosses a section boundary. |
1da177e4 | 279 | */ |
e73fc88e CM |
280 | mov r0, r2, lsr #SECTION_SHIFT |
281 | movs r0, r0, lsl #SECTION_SHIFT | |
9fa16b77 NP |
282 | subne r3, r0, r8 |
283 | addne r3, r3, #PAGE_OFFSET | |
284 | addne r3, r4, r3, lsr #(SECTION_SHIFT - PMD_ORDER) | |
285 | orrne r6, r7, r0 | |
6f16f499 NP |
286 | strne r6, [r3], #1 << PMD_ORDER |
287 | addne r6, r6, #1 << SECTION_SHIFT | |
9fa16b77 | 288 | strne r6, [r3] |
1da177e4 | 289 | |
4e1db26a | 290 | #if defined(CONFIG_ARM_LPAE) && defined(CONFIG_CPU_ENDIAN_BE8) |
d61947a1 WD |
291 | sub r4, r4, #4 @ Fixup page table pointer |
292 | @ for 64-bit descriptors | |
293 | #endif | |
294 | ||
c77b0427 | 295 | #ifdef CONFIG_DEBUG_LL |
9b5a146a | 296 | #if !defined(CONFIG_DEBUG_ICEDCC) && !defined(CONFIG_DEBUG_SEMIHOSTING) |
1da177e4 LT |
297 | /* |
298 | * Map in IO space for serial debugging. | |
299 | * This allows debug messages to be output | |
300 | * via a serial console before paging_init. | |
301 | */ | |
639da5ee | 302 | addruart r7, r3, r0 |
c293393f | 303 | |
e73fc88e CM |
304 | mov r3, r3, lsr #SECTION_SHIFT |
305 | mov r3, r3, lsl #PMD_ORDER | |
c293393f | 306 | |
1da177e4 | 307 | add r0, r4, r3 |
e73fc88e | 308 | mov r3, r7, lsr #SECTION_SHIFT |
c293393f | 309 | ldr r7, [r10, #PROCINFO_IO_MMUFLAGS] @ io_mmuflags |
e73fc88e | 310 | orr r3, r7, r3, lsl #SECTION_SHIFT |
1b6ba46b CM |
311 | #ifdef CONFIG_ARM_LPAE |
312 | mov r7, #1 << (54 - 32) @ XN | |
d61947a1 WD |
313 | #ifdef CONFIG_CPU_ENDIAN_BE8 |
314 | str r7, [r0], #4 | |
315 | str r3, [r0], #4 | |
1b6ba46b | 316 | #else |
f67860a7 | 317 | str r3, [r0], #4 |
1b6ba46b CM |
318 | str r7, [r0], #4 |
319 | #endif | |
d61947a1 WD |
320 | #else |
321 | orr r3, r3, #PMD_SECT_XN | |
322 | str r3, [r0], #4 | |
323 | #endif | |
c293393f | 324 | |
9b5a146a NP |
325 | #else /* CONFIG_DEBUG_ICEDCC || CONFIG_DEBUG_SEMIHOSTING */ |
326 | /* we don't need any serial debugging mappings */ | |
c293393f | 327 | ldr r7, [r10, #PROCINFO_IO_MMUFLAGS] @ io_mmuflags |
9b5a146a | 328 | #endif |
c293393f | 329 | |
1da177e4 LT |
330 | #if defined(CONFIG_ARCH_NETWINDER) || defined(CONFIG_ARCH_CATS) |
331 | /* | |
3c0bdac3 RK |
332 | * If we're using the NetWinder or CATS, we also need to map |
333 | * in the 16550-type serial port for the debug messages | |
1da177e4 | 334 | */ |
e73fc88e | 335 | add r0, r4, #0xff000000 >> (SECTION_SHIFT - PMD_ORDER) |
c77b0427 RK |
336 | orr r3, r7, #0x7c000000 |
337 | str r3, [r0] | |
1da177e4 | 338 | #endif |
1da177e4 LT |
339 | #ifdef CONFIG_ARCH_RPC |
340 | /* | |
341 | * Map in screen at 0x02000000 & SCREEN2_BASE | |
342 | * Similar reasons here - for debug. This is | |
343 | * only for Acorn RiscPC architectures. | |
344 | */ | |
e73fc88e | 345 | add r0, r4, #0x02000000 >> (SECTION_SHIFT - PMD_ORDER) |
c77b0427 | 346 | orr r3, r7, #0x02000000 |
1da177e4 | 347 | str r3, [r0] |
e73fc88e | 348 | add r0, r4, #0xd8000000 >> (SECTION_SHIFT - PMD_ORDER) |
1da177e4 | 349 | str r3, [r0] |
c77b0427 | 350 | #endif |
1b6ba46b CM |
351 | #endif |
352 | #ifdef CONFIG_ARM_LPAE | |
353 | sub r4, r4, #0x1000 @ point to the PGD table | |
1da177e4 | 354 | #endif |
6ebbf2ce | 355 | ret lr |
93ed3970 | 356 | ENDPROC(__create_page_tables) |
1da177e4 | 357 | .ltorg |
4f79a5dd | 358 | .align |
72662e01 | 359 | __turn_mmu_on_loc: |
786f1b73 | 360 | .long . |
72662e01 WD |
361 | .long __turn_mmu_on |
362 | .long __turn_mmu_on_end | |
1da177e4 | 363 | |
00945010 | 364 | #if defined(CONFIG_SMP) |
2449189b | 365 | .text |
bafe5865 | 366 | .arm |
c07b5fd0 | 367 | ENTRY(secondary_startup_arm) |
14327c66 | 368 | THUMB( badr r9, 1f ) @ Kernel is entered in ARM. |
bafe5865 SB |
369 | THUMB( bx r9 ) @ If this is a Thumb-2 kernel, |
370 | THUMB( .thumb ) @ switch to Thumb now. | |
371 | THUMB(1: ) | |
00945010 RK |
372 | ENTRY(secondary_startup) |
373 | /* | |
374 | * Common entry point for secondary CPUs. | |
375 | * | |
376 | * Ensure that we're in SVC mode, and IRQs are disabled. Lookup | |
377 | * the processor type - there is no need to check the machine type | |
378 | * as it has already been validated by the primary processor. | |
379 | */ | |
97bcb0fe BD |
380 | |
381 | ARM_BE8(setend be) @ ensure we are in BE8 mode | |
382 | ||
80c59daf | 383 | #ifdef CONFIG_ARM_VIRT_EXT |
6e484be1 | 384 | bl __hyp_stub_install_secondary |
80c59daf DM |
385 | #endif |
386 | safe_svcmode_maskall r9 | |
387 | ||
00945010 RK |
388 | mrc p15, 0, r9, c0, c0 @ get processor id |
389 | bl __lookup_processor_type | |
390 | movs r10, r5 @ invalid processor? | |
391 | moveq r0, #'p' @ yes, error 'p' | |
a75e5248 | 392 | THUMB( it eq ) @ force fixup-able long branch encoding |
00945010 RK |
393 | beq __error_p |
394 | ||
395 | /* | |
396 | * Use the page tables supplied from __cpu_up. | |
397 | */ | |
398 | adr r4, __secondary_data | |
399 | ldmia r4, {r5, r7, r12} @ address to jump to after | |
d427958a | 400 | sub lr, r4, r5 @ mmu has been enabled |
b2c3e38a RK |
401 | add r3, r7, lr |
402 | ldrd r4, [r3, #0] @ get secondary_data.pgdir | |
998ef5d8 GC |
403 | ARM_BE8(eor r4, r4, r5) @ Swap r5 and r4 in BE: |
404 | ARM_BE8(eor r5, r4, r5) @ it can be done in 3 steps | |
405 | ARM_BE8(eor r4, r4, r5) @ without using a temp reg. | |
b2c3e38a | 406 | ldr r8, [r3, #8] @ get secondary_data.swapper_pg_dir |
14327c66 | 407 | badr lr, __enable_mmu @ return address |
00945010 | 408 | mov r13, r12 @ __secondary_switched address |
bf35706f AB |
409 | ldr r12, [r10, #PROCINFO_INITFUNC] |
410 | add r12, r12, r10 @ initialise processor | |
411 | @ (return control reg) | |
412 | ret r12 | |
00945010 | 413 | ENDPROC(secondary_startup) |
bafe5865 | 414 | ENDPROC(secondary_startup_arm) |
00945010 RK |
415 | |
416 | /* | |
417 | * r6 = &secondary_data | |
418 | */ | |
419 | ENTRY(__secondary_switched) | |
b2c3e38a | 420 | ldr sp, [r7, #12] @ get secondary_data.stack |
00945010 RK |
421 | mov fp, #0 |
422 | b secondary_start_kernel | |
423 | ENDPROC(__secondary_switched) | |
424 | ||
4f79a5dd DM |
425 | .align |
426 | ||
00945010 RK |
427 | .type __secondary_data, %object |
428 | __secondary_data: | |
429 | .long . | |
430 | .long secondary_data | |
431 | .long __secondary_switched | |
432 | #endif /* defined(CONFIG_SMP) */ | |
433 | ||
434 | ||
435 | ||
436 | /* | |
437 | * Setup common bits before finally enabling the MMU. Essentially | |
438 | * this is just loading the page table pointer and domain access | |
b2c3e38a RK |
439 | * registers. All these registers need to be preserved by the |
440 | * processor setup function (or set in the case of r0) | |
865a4fae RK |
441 | * |
442 | * r0 = cp#15 control register | |
443 | * r1 = machine ID | |
4c2896e8 | 444 | * r2 = atags or dtb pointer |
b2c3e38a RK |
445 | * r4 = TTBR pointer (low word) |
446 | * r5 = TTBR pointer (high word if LPAE) | |
865a4fae RK |
447 | * r9 = processor ID |
448 | * r13 = *virtual* address to jump to upon completion | |
00945010 RK |
449 | */ |
450 | __enable_mmu: | |
8428e84d | 451 | #if defined(CONFIG_ALIGNMENT_TRAP) && __LINUX_ARM_ARCH__ < 6 |
00945010 RK |
452 | orr r0, r0, #CR_A |
453 | #else | |
454 | bic r0, r0, #CR_A | |
455 | #endif | |
456 | #ifdef CONFIG_CPU_DCACHE_DISABLE | |
457 | bic r0, r0, #CR_C | |
458 | #endif | |
459 | #ifdef CONFIG_CPU_BPREDICT_DISABLE | |
460 | bic r0, r0, #CR_Z | |
461 | #endif | |
462 | #ifdef CONFIG_CPU_ICACHE_DISABLE | |
463 | bic r0, r0, #CR_I | |
464 | #endif | |
b2c3e38a RK |
465 | #ifdef CONFIG_ARM_LPAE |
466 | mcrr p15, 0, r4, r5, c2 @ load TTBR0 | |
467 | #else | |
0171356a | 468 | mov r5, #DACR_INIT |
00945010 RK |
469 | mcr p15, 0, r5, c3, c0, 0 @ load domain access register |
470 | mcr p15, 0, r4, c2, c0, 0 @ load page table pointer | |
1b6ba46b | 471 | #endif |
00945010 RK |
472 | b __turn_mmu_on |
473 | ENDPROC(__enable_mmu) | |
474 | ||
475 | /* | |
476 | * Enable the MMU. This completely changes the structure of the visible | |
477 | * memory space. You will not be able to trace execution through this. | |
478 | * If you have an enquiry about this, *please* check the linux-arm-kernel | |
479 | * mailing list archives BEFORE sending another post to the list. | |
480 | * | |
481 | * r0 = cp#15 control register | |
865a4fae | 482 | * r1 = machine ID |
4c2896e8 | 483 | * r2 = atags or dtb pointer |
865a4fae | 484 | * r9 = processor ID |
00945010 RK |
485 | * r13 = *virtual* address to jump to upon completion |
486 | * | |
487 | * other registers depend on the function called upon completion | |
488 | */ | |
489 | .align 5 | |
4e8ee7de WD |
490 | .pushsection .idmap.text, "ax" |
491 | ENTRY(__turn_mmu_on) | |
00945010 | 492 | mov r0, r0 |
d675d0bc | 493 | instr_sync |
00945010 RK |
494 | mcr p15, 0, r0, c1, c0, 0 @ write control reg |
495 | mrc p15, 0, r3, c0, c0, 0 @ read id reg | |
d675d0bc | 496 | instr_sync |
00945010 RK |
497 | mov r3, r3 |
498 | mov r3, r13 | |
6ebbf2ce | 499 | ret r3 |
72662e01 | 500 | __turn_mmu_on_end: |
00945010 | 501 | ENDPROC(__turn_mmu_on) |
4e8ee7de | 502 | .popsection |
00945010 | 503 | |
1da177e4 | 504 | |
f00ec48f | 505 | #ifdef CONFIG_SMP_ON_UP |
1dc5455f | 506 | __HEAD |
f00ec48f | 507 | __fixup_smp: |
e98ff0f5 RK |
508 | and r3, r9, #0x000f0000 @ architecture version |
509 | teq r3, #0x000f0000 @ CPU ID supported? | |
f00ec48f RK |
510 | bne __fixup_smp_on_up @ no, assume UP |
511 | ||
e98ff0f5 RK |
512 | bic r3, r9, #0x00ff0000 |
513 | bic r3, r3, #0x0000000f @ mask 0xff00fff0 | |
514 | mov r4, #0x41000000 | |
0eb0511d | 515 | orr r4, r4, #0x0000b000 |
e98ff0f5 RK |
516 | orr r4, r4, #0x00000020 @ val 0x4100b020 |
517 | teq r3, r4 @ ARM 11MPCore? | |
6ebbf2ce | 518 | reteq lr @ yes, assume SMP |
f00ec48f RK |
519 | |
520 | mrc p15, 0, r0, c0, c0, 5 @ read MPIDR | |
e98ff0f5 RK |
521 | and r0, r0, #0xc0000000 @ multiprocessing extensions and |
522 | teq r0, #0x80000000 @ not part of a uniprocessor system? | |
bc41b872 SS |
523 | bne __fixup_smp_on_up @ no, assume UP |
524 | ||
525 | @ Core indicates it is SMP. Check for Aegis SOC where a single | |
526 | @ Cortex-A9 CPU is present but SMP operations fault. | |
527 | mov r4, #0x41000000 | |
528 | orr r4, r4, #0x0000c000 | |
529 | orr r4, r4, #0x00000090 | |
530 | teq r3, r4 @ Check for ARM Cortex-A9 | |
6ebbf2ce | 531 | retne lr @ Not ARM Cortex-A9, |
bc41b872 SS |
532 | |
533 | @ If a future SoC *does* use 0x0 as the PERIPH_BASE, then the | |
534 | @ below address check will need to be #ifdef'd or equivalent | |
535 | @ for the Aegis platform. | |
536 | mrc p15, 4, r0, c15, c0 @ get SCU base address | |
537 | teq r0, #0x0 @ '0' on actual UP A9 hardware | |
538 | beq __fixup_smp_on_up @ So its an A9 UP | |
539 | ldr r0, [r0, #4] @ read SCU Config | |
10593b2e | 540 | ARM_BE8(rev r0, r0) @ byteswap if big endian |
bc41b872 SS |
541 | and r0, r0, #0x3 @ number of CPUs |
542 | teq r0, #0x0 @ is 1? | |
6ebbf2ce | 543 | retne lr |
f00ec48f RK |
544 | |
545 | __fixup_smp_on_up: | |
546 | adr r0, 1f | |
0eb0511d | 547 | ldmia r0, {r3 - r5} |
f00ec48f | 548 | sub r3, r0, r3 |
0eb0511d RK |
549 | add r4, r4, r3 |
550 | add r5, r5, r3 | |
4a9cb360 | 551 | b __do_fixup_smp_on_up |
f00ec48f RK |
552 | ENDPROC(__fixup_smp) |
553 | ||
4f79a5dd | 554 | .align |
f00ec48f RK |
555 | 1: .word . |
556 | .word __smpalt_begin | |
557 | .word __smpalt_end | |
558 | ||
559 | .pushsection .data | |
560 | .globl smp_on_up | |
561 | smp_on_up: | |
562 | ALT_SMP(.long 1) | |
563 | ALT_UP(.long 0) | |
564 | .popsection | |
4a9cb360 | 565 | #endif |
f00ec48f | 566 | |
4a9cb360 RK |
567 | .text |
568 | __do_fixup_smp_on_up: | |
569 | cmp r4, r5 | |
6ebbf2ce | 570 | reths lr |
4a9cb360 RK |
571 | ldmia r4!, {r0, r6} |
572 | ARM( str r6, [r0, r3] ) | |
573 | THUMB( add r0, r0, r3 ) | |
574 | #ifdef __ARMEB__ | |
575 | THUMB( mov r6, r6, ror #16 ) @ Convert word order for big-endian. | |
f00ec48f | 576 | #endif |
4a9cb360 RK |
577 | THUMB( strh r6, [r0], #2 ) @ For Thumb-2, store as two halfwords |
578 | THUMB( mov r6, r6, lsr #16 ) @ to be robust against misaligned r3. | |
579 | THUMB( strh r6, [r0] ) | |
580 | b __do_fixup_smp_on_up | |
581 | ENDPROC(__do_fixup_smp_on_up) | |
582 | ||
583 | ENTRY(fixup_smp) | |
584 | stmfd sp!, {r4 - r6, lr} | |
585 | mov r4, r0 | |
586 | add r5, r0, r1 | |
587 | mov r3, #0 | |
588 | bl __do_fixup_smp_on_up | |
589 | ldmfd sp!, {r4 - r6, pc} | |
590 | ENDPROC(fixup_smp) | |
f00ec48f | 591 | |
830fd4d6 | 592 | #ifdef __ARMEB__ |
f52bb722 S |
593 | #define LOW_OFFSET 0x4 |
594 | #define HIGH_OFFSET 0x0 | |
595 | #else | |
596 | #define LOW_OFFSET 0x0 | |
597 | #define HIGH_OFFSET 0x4 | |
598 | #endif | |
599 | ||
dc21af99 RK |
600 | #ifdef CONFIG_ARM_PATCH_PHYS_VIRT |
601 | ||
602 | /* __fixup_pv_table - patch the stub instructions with the delta between | |
603 | * PHYS_OFFSET and PAGE_OFFSET, which is assumed to be 16MiB aligned and | |
604 | * can be expressed by an immediate shifter operand. The stub instruction | |
605 | * has a form of '(add|sub) rd, rn, #imm'. | |
606 | */ | |
607 | __HEAD | |
608 | __fixup_pv_table: | |
609 | adr r0, 1f | |
f52bb722 S |
610 | ldmia r0, {r3-r7} |
611 | mvn ip, #0 | |
612 | subs r3, r0, r3 @ PHYS_OFFSET - PAGE_OFFSET | |
dc21af99 RK |
613 | add r4, r4, r3 @ adjust table start address |
614 | add r5, r5, r3 @ adjust table end address | |
e26a9e00 | 615 | add r6, r6, r3 @ adjust __pv_phys_pfn_offset address |
f52bb722 | 616 | add r7, r7, r3 @ adjust __pv_offset address |
7a061928 | 617 | mov r0, r8, lsr #PAGE_SHIFT @ convert to PFN |
e3892e91 | 618 | str r0, [r6] @ save computed PHYS_OFFSET to __pv_phys_pfn_offset |
f52bb722 | 619 | strcc ip, [r7, #HIGH_OFFSET] @ save to __pv_offset high bits |
dc21af99 RK |
620 | mov r6, r3, lsr #24 @ constant for add/sub instructions |
621 | teq r3, r6, lsl #24 @ must be 16MiB aligned | |
b511d75d | 622 | THUMB( it ne @ cross section branch ) |
dc21af99 | 623 | bne __error |
f52bb722 | 624 | str r3, [r7, #LOW_OFFSET] @ save to __pv_offset low bits |
dc21af99 RK |
625 | b __fixup_a_pv_table |
626 | ENDPROC(__fixup_pv_table) | |
627 | ||
628 | .align | |
629 | 1: .long . | |
630 | .long __pv_table_begin | |
631 | .long __pv_table_end | |
e26a9e00 | 632 | 2: .long __pv_phys_pfn_offset |
f52bb722 | 633 | .long __pv_offset |
dc21af99 RK |
634 | |
635 | .text | |
636 | __fixup_a_pv_table: | |
f52bb722 S |
637 | adr r0, 3f |
638 | ldr r6, [r0] | |
639 | add r6, r6, r3 | |
640 | ldr r0, [r6, #HIGH_OFFSET] @ pv_offset high word | |
641 | ldr r6, [r6, #LOW_OFFSET] @ pv_offset low word | |
642 | mov r6, r6, lsr #24 | |
643 | cmn r0, #1 | |
b511d75d | 644 | #ifdef CONFIG_THUMB2_KERNEL |
f52bb722 | 645 | moveq r0, #0x200000 @ set bit 21, mov to mvn instruction |
daece596 NP |
646 | lsls r6, #24 |
647 | beq 2f | |
b511d75d NP |
648 | clz r7, r6 |
649 | lsr r6, #24 | |
650 | lsl r6, r7 | |
651 | bic r6, #0x0080 | |
652 | lsrs r7, #1 | |
653 | orrcs r6, #0x0080 | |
654 | orr r6, r6, r7, lsl #12 | |
655 | orr r6, #0x4000 | |
daece596 NP |
656 | b 2f |
657 | 1: add r7, r3 | |
658 | ldrh ip, [r7, #2] | |
2f9bf9be | 659 | ARM_BE8(rev16 ip, ip) |
f52bb722 S |
660 | tst ip, #0x4000 |
661 | and ip, #0x8f00 | |
662 | orrne ip, r6 @ mask in offset bits 31-24 | |
663 | orreq ip, r0 @ mask in offset bits 7-0 | |
2f9bf9be | 664 | ARM_BE8(rev16 ip, ip) |
b511d75d | 665 | strh ip, [r7, #2] |
2098990e RK |
666 | bne 2f |
667 | ldrh ip, [r7] | |
668 | ARM_BE8(rev16 ip, ip) | |
669 | bic ip, #0x20 | |
670 | orr ip, ip, r0, lsr #16 | |
671 | ARM_BE8(rev16 ip, ip) | |
672 | strh ip, [r7] | |
daece596 | 673 | 2: cmp r4, r5 |
b511d75d | 674 | ldrcc r7, [r4], #4 @ use branch for delay slot |
daece596 | 675 | bcc 1b |
b511d75d | 676 | bx lr |
d9a790df VK |
677 | #else |
678 | #ifdef CONFIG_CPU_ENDIAN_BE8 | |
679 | moveq r0, #0x00004000 @ set bit 22, mov to mvn instruction | |
b511d75d | 680 | #else |
f52bb722 | 681 | moveq r0, #0x400000 @ set bit 22, mov to mvn instruction |
d9a790df | 682 | #endif |
daece596 NP |
683 | b 2f |
684 | 1: ldr ip, [r7, r3] | |
2f9bf9be BD |
685 | #ifdef CONFIG_CPU_ENDIAN_BE8 |
686 | @ in BE8, we load data in BE, but instructions still in LE | |
687 | bic ip, ip, #0xff000000 | |
2098990e RK |
688 | tst ip, #0x000f0000 @ check the rotation field |
689 | orrne ip, ip, r6, lsl #24 @ mask in offset bits 31-24 | |
690 | biceq ip, ip, #0x00004000 @ clear bit 22 | |
d9a790df | 691 | orreq ip, ip, r0 @ mask in offset bits 7-0 |
2f9bf9be | 692 | #else |
dc21af99 | 693 | bic ip, ip, #0x000000ff |
f52bb722 S |
694 | tst ip, #0xf00 @ check the rotation field |
695 | orrne ip, ip, r6 @ mask in offset bits 31-24 | |
696 | biceq ip, ip, #0x400000 @ clear bit 22 | |
697 | orreq ip, ip, r0 @ mask in offset bits 7-0 | |
2f9bf9be | 698 | #endif |
dc21af99 | 699 | str ip, [r7, r3] |
daece596 | 700 | 2: cmp r4, r5 |
dc21af99 | 701 | ldrcc r7, [r4], #4 @ use branch for delay slot |
daece596 | 702 | bcc 1b |
6ebbf2ce | 703 | ret lr |
b511d75d | 704 | #endif |
dc21af99 RK |
705 | ENDPROC(__fixup_a_pv_table) |
706 | ||
830fd4d6 | 707 | .align |
f52bb722 S |
708 | 3: .long __pv_offset |
709 | ||
dc21af99 RK |
710 | ENTRY(fixup_pv_table) |
711 | stmfd sp!, {r4 - r7, lr} | |
dc21af99 RK |
712 | mov r3, #0 @ no offset |
713 | mov r4, r0 @ r0 = table start | |
714 | add r5, r0, r1 @ r1 = table size | |
dc21af99 RK |
715 | bl __fixup_a_pv_table |
716 | ldmfd sp!, {r4 - r7, pc} | |
717 | ENDPROC(fixup_pv_table) | |
718 | ||
dc21af99 | 719 | .data |
e26a9e00 RK |
720 | .globl __pv_phys_pfn_offset |
721 | .type __pv_phys_pfn_offset, %object | |
722 | __pv_phys_pfn_offset: | |
723 | .word 0 | |
724 | .size __pv_phys_pfn_offset, . -__pv_phys_pfn_offset | |
f52bb722 S |
725 | |
726 | .globl __pv_offset | |
727 | .type __pv_offset, %object | |
dc21af99 | 728 | __pv_offset: |
f52bb722 S |
729 | .quad 0 |
730 | .size __pv_offset, . -__pv_offset | |
4dd1837d AV |
731 | EXPORT_SYMBOL(__pv_phys_pfn_offset) |
732 | EXPORT_SYMBOL(__pv_offset) | |
dc21af99 RK |
733 | #endif |
734 | ||
75d90832 | 735 | #include "head-common.S" |