Commit | Line | Data |
---|---|---|
6ebbf2ce | 1 | #include <asm/assembler.h> |
c36ef4b1 | 2 | #include <asm/unwind.h> |
4dd1837d | 3 | #include <asm/export.h> |
c36ef4b1 | 4 | |
6323f0cc | 5 | #if __LINUX_ARM_ARCH__ >= 6 |
c36ef4b1 WD |
6 | .macro bitop, name, instr |
7 | ENTRY( \name ) | |
8 | UNWIND( .fnstart ) | |
a16ede35 RK |
9 | ands ip, r1, #3 |
10 | strneb r1, [ip] @ assert word-aligned | |
54ea06f6 | 11 | mov r2, #1 |
6323f0cc RK |
12 | and r3, r0, #31 @ Get bit offset |
13 | mov r0, r0, lsr #5 | |
14 | add r1, r1, r0, lsl #2 @ Get word offset | |
b7ec6994 | 15 | #if __LINUX_ARM_ARCH__ >= 7 && defined(CONFIG_SMP) |
d779c07d WD |
16 | .arch_extension mp |
17 | ALT_SMP(W(pldw) [r1]) | |
18 | ALT_UP(W(nop)) | |
19 | #endif | |
54ea06f6 | 20 | mov r3, r2, lsl r3 |
6323f0cc | 21 | 1: ldrex r2, [r1] |
54ea06f6 | 22 | \instr r2, r2, r3 |
6323f0cc | 23 | strex r0, r2, [r1] |
e7ec0293 | 24 | cmp r0, #0 |
54ea06f6 | 25 | bne 1b |
3ba6e69a | 26 | bx lr |
c36ef4b1 WD |
27 | UNWIND( .fnend ) |
28 | ENDPROC(\name ) | |
4dd1837d | 29 | EXPORT_SYMBOL(\name ) |
54ea06f6 RK |
30 | .endm |
31 | ||
c36ef4b1 WD |
32 | .macro testop, name, instr, store |
33 | ENTRY( \name ) | |
34 | UNWIND( .fnstart ) | |
a16ede35 RK |
35 | ands ip, r1, #3 |
36 | strneb r1, [ip] @ assert word-aligned | |
54ea06f6 | 37 | mov r2, #1 |
6323f0cc RK |
38 | and r3, r0, #31 @ Get bit offset |
39 | mov r0, r0, lsr #5 | |
40 | add r1, r1, r0, lsl #2 @ Get word offset | |
54ea06f6 | 41 | mov r3, r2, lsl r3 @ create mask |
bac4e960 | 42 | smp_dmb |
c32ffce0 WD |
43 | #if __LINUX_ARM_ARCH__ >= 7 && defined(CONFIG_SMP) |
44 | .arch_extension mp | |
45 | ALT_SMP(W(pldw) [r1]) | |
46 | ALT_UP(W(nop)) | |
47 | #endif | |
6323f0cc | 48 | 1: ldrex r2, [r1] |
54ea06f6 | 49 | ands r0, r2, r3 @ save old value of bit |
6323f0cc RK |
50 | \instr r2, r2, r3 @ toggle bit |
51 | strex ip, r2, [r1] | |
614d73ed | 52 | cmp ip, #0 |
54ea06f6 | 53 | bne 1b |
bac4e960 | 54 | smp_dmb |
54ea06f6 RK |
55 | cmp r0, #0 |
56 | movne r0, #1 | |
3ba6e69a | 57 | 2: bx lr |
c36ef4b1 WD |
58 | UNWIND( .fnend ) |
59 | ENDPROC(\name ) | |
4dd1837d | 60 | EXPORT_SYMBOL(\name ) |
54ea06f6 RK |
61 | .endm |
62 | #else | |
c36ef4b1 WD |
63 | .macro bitop, name, instr |
64 | ENTRY( \name ) | |
65 | UNWIND( .fnstart ) | |
a16ede35 RK |
66 | ands ip, r1, #3 |
67 | strneb r1, [ip] @ assert word-aligned | |
6323f0cc RK |
68 | and r2, r0, #31 |
69 | mov r0, r0, lsr #5 | |
7a55fd0b RK |
70 | mov r3, #1 |
71 | mov r3, r3, lsl r2 | |
59d1ff3b | 72 | save_and_disable_irqs ip |
6323f0cc | 73 | ldr r2, [r1, r0, lsl #2] |
7a55fd0b | 74 | \instr r2, r2, r3 |
6323f0cc | 75 | str r2, [r1, r0, lsl #2] |
7a55fd0b | 76 | restore_irqs ip |
6ebbf2ce | 77 | ret lr |
c36ef4b1 WD |
78 | UNWIND( .fnend ) |
79 | ENDPROC(\name ) | |
4dd1837d | 80 | EXPORT_SYMBOL(\name ) |
7a55fd0b RK |
81 | .endm |
82 | ||
83 | /** | |
84 | * testop - implement a test_and_xxx_bit operation. | |
85 | * @instr: operational instruction | |
86 | * @store: store instruction | |
87 | * | |
88 | * Note: we can trivially conditionalise the store instruction | |
6cbdc8c5 | 89 | * to avoid dirtying the data cache. |
7a55fd0b | 90 | */ |
c36ef4b1 WD |
91 | .macro testop, name, instr, store |
92 | ENTRY( \name ) | |
93 | UNWIND( .fnstart ) | |
a16ede35 RK |
94 | ands ip, r1, #3 |
95 | strneb r1, [ip] @ assert word-aligned | |
6323f0cc RK |
96 | and r3, r0, #31 |
97 | mov r0, r0, lsr #5 | |
59d1ff3b | 98 | save_and_disable_irqs ip |
6323f0cc RK |
99 | ldr r2, [r1, r0, lsl #2]! |
100 | mov r0, #1 | |
7a55fd0b RK |
101 | tst r2, r0, lsl r3 |
102 | \instr r2, r2, r0, lsl r3 | |
103 | \store r2, [r1] | |
7a55fd0b | 104 | moveq r0, #0 |
0d928b0b | 105 | restore_irqs ip |
6ebbf2ce | 106 | ret lr |
c36ef4b1 WD |
107 | UNWIND( .fnend ) |
108 | ENDPROC(\name ) | |
4dd1837d | 109 | EXPORT_SYMBOL(\name ) |
7a55fd0b | 110 | .endm |
54ea06f6 | 111 | #endif |