projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 1da177e4 | 1 | /* |
| a09e64fb | 2 | * arch/arm/mach-footbridge/include/mach/hardware.h |
| 1da177e4 LT |
3 | * |
| 4 | * Copyright (C) 1998-1999 Russell King. | |
| 5 | * | |
| 6 | * This program is free software; you can redistribute it and/or modify | |
| 7 | * it under the terms of the GNU General Public License version 2 as | |
| 8 | * published by the Free Software Foundation. | |
| 9 | * | |
| 10 | * This file contains the hardware definitions of the EBSA-285. | |
| 11 | */ | |
| 12 | #ifndef __ASM_ARCH_HARDWARE_H | |
| 13 | #define __ASM_ARCH_HARDWARE_H | |
| 14 | ||
| 1da177e4 LT |
15 | /* Virtual Physical Size |
| 16 | * 0xff800000 0x40000000 1MB X-Bus | |
| 17 | * 0xff000000 0x7c000000 1MB PCI I/O space | |
| 18 | * 0xfe000000 0x42000000 1MB CSR | |
| 19 | * 0xfd000000 0x78000000 1MB Outbound write flush (not supported) | |
| 20 | * 0xfc000000 0x79000000 1MB PCI IACK/special space | |
| 21 | * 0xfb000000 0x7a000000 16MB PCI Config type 1 | |
| 22 | * 0xfa000000 0x7b000000 16MB PCI Config type 0 | |
| 23 | * 0xf9000000 0x50000000 1MB Cache flush | |
| 24 | * 0xf0000000 0x80000000 16MB ISA memory | |
| 25 | */ | |
| 6fa85e5c SM |
26 | |
| 27 | #ifdef CONFIG_MMU | |
| 28 | #define MMU_IO(a, b) (a) | |
| 29 | #else | |
| 30 | #define MMU_IO(a, b) (b) | |
| 31 | #endif | |
| 32 | ||
| 1da177e4 | 33 | #define XBUS_SIZE 0x00100000 |
| 6fa85e5c | 34 | #define XBUS_BASE MMU_IO(0xff800000, 0x40000000) |
| 1da177e4 | 35 | |
| 1da177e4 | 36 | #define ARMCSR_SIZE 0x00100000 |
| 6fa85e5c | 37 | #define ARMCSR_BASE MMU_IO(0xfe000000, 0x42000000) |
| 1da177e4 LT |
38 | |
| 39 | #define WFLUSH_SIZE 0x00100000 | |
| 6fa85e5c | 40 | #define WFLUSH_BASE MMU_IO(0xfd000000, 0x78000000) |
| 1da177e4 LT |
41 | |
| 42 | #define PCIIACK_SIZE 0x00100000 | |
| 6fa85e5c | 43 | #define PCIIACK_BASE MMU_IO(0xfc000000, 0x79000000) |
| 1da177e4 LT |
44 | |
| 45 | #define PCICFG1_SIZE 0x01000000 | |
| 6fa85e5c | 46 | #define PCICFG1_BASE MMU_IO(0xfb000000, 0x7a000000) |
| 1da177e4 LT |
47 | |
| 48 | #define PCICFG0_SIZE 0x01000000 | |
| 6fa85e5c | 49 | #define PCICFG0_BASE MMU_IO(0xfa000000, 0x7b000000) |
| 1da177e4 | 50 | |
| 1da177e4 | 51 | #define PCIMEM_SIZE 0x01000000 |
| 6fa85e5c | 52 | #define PCIMEM_BASE MMU_IO(0xf0000000, 0x80000000) |
| 1da177e4 | 53 | |
| 43024ed6 | 54 | #define XBUS_CS2 0x40012000 |
| 1da177e4 LT |
55 | |
| 56 | #define XBUS_SWITCH ((volatile unsigned char *)(XBUS_BASE + 0x12000)) | |
| 57 | #define XBUS_SWITCH_SWITCH ((*XBUS_SWITCH) & 15) | |
| 58 | #define XBUS_SWITCH_J17_13 ((*XBUS_SWITCH) & (1 << 4)) | |
| 59 | #define XBUS_SWITCH_J17_11 ((*XBUS_SWITCH) & (1 << 5)) | |
| 60 | #define XBUS_SWITCH_J17_9 ((*XBUS_SWITCH) & (1 << 6)) | |
| 61 | ||
| c94e4ad2 | 62 | #define UNCACHEABLE_ADDR (ARMCSR_BASE + 0x108) /* CSR_ROMBASEMASK */ |
| 1da177e4 LT |
63 | |
| 64 | ||
| 65 | /* PIC irq control */ | |
| 66 | #define PIC_LO 0x20 | |
| 67 | #define PIC_MASK_LO 0x21 | |
| 68 | #define PIC_HI 0xA0 | |
| 69 | #define PIC_MASK_HI 0xA1 | |
| 70 | ||
| 71 | /* GPIO pins */ | |
| 72 | #define GPIO_CCLK 0x800 | |
| 73 | #define GPIO_DSCLK 0x400 | |
| 74 | #define GPIO_E2CLK 0x200 | |
| 75 | #define GPIO_IOLOAD 0x100 | |
| 76 | #define GPIO_RED_LED 0x080 | |
| 77 | #define GPIO_WDTIMER 0x040 | |
| 78 | #define GPIO_DATA 0x020 | |
| 79 | #define GPIO_IOCLK 0x010 | |
| 80 | #define GPIO_DONE 0x008 | |
| 81 | #define GPIO_FAN 0x004 | |
| 82 | #define GPIO_GREEN_LED 0x002 | |
| 83 | #define GPIO_RESET 0x001 | |
| 84 | ||
| 85 | /* CPLD pins */ | |
| 86 | #define CPLD_DS_ENABLE 8 | |
| 87 | #define CPLD_7111_DISABLE 4 | |
| 88 | #define CPLD_UNMUTE 2 | |
| 89 | #define CPLD_FLASH_WR_ENABLE 1 | |
| 90 | ||
| 91 | #ifndef __ASSEMBLY__ | |
| bd31b859 | 92 | extern raw_spinlock_t nw_gpio_lock; |
| 70d13e08 RK |
93 | extern void nw_gpio_modify_op(unsigned int mask, unsigned int set); |
| 94 | extern void nw_gpio_modify_io(unsigned int mask, unsigned int in); | |
| 95 | extern unsigned int nw_gpio_read(void); | |
| 96 | extern void nw_cpld_modify(unsigned int mask, unsigned int set); | |
| 1da177e4 LT |
97 | #endif |
| 98 | ||
| 1da177e4 | 99 | #endif |