projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 022d0716 FL |
1 | /* |
| 2 | * Copyright (C) 2015 Freescale Semiconductor, Inc. | |
| 3 | * | |
| 4 | * This program is free software; you can redistribute it and/or modify | |
| 5 | * it under the terms of the GNU General Public License version 2 as | |
| 6 | * published by the Free Software Foundation. | |
| 7 | */ | |
| 8 | #include <linux/irqchip.h> | |
| 709bc065 FD |
9 | #include <linux/mfd/syscon.h> |
| 10 | #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h> | |
| 11 | #include <linux/micrel_phy.h> | |
| 022d0716 | 12 | #include <linux/of_platform.h> |
| 709bc065 FD |
13 | #include <linux/phy.h> |
| 14 | #include <linux/regmap.h> | |
| 022d0716 FL |
15 | #include <asm/mach/arch.h> |
| 16 | #include <asm/mach/map.h> | |
| 17 | ||
| 18 | #include "common.h" | |
| 547e8f52 | 19 | #include "cpuidle.h" |
| 022d0716 | 20 | |
| 709bc065 FD |
21 | static void __init imx6ul_enet_clk_init(void) |
| 22 | { | |
| 23 | struct regmap *gpr; | |
| 24 | ||
| 25 | gpr = syscon_regmap_lookup_by_compatible("fsl,imx6ul-iomuxc-gpr"); | |
| 26 | if (!IS_ERR(gpr)) | |
| 27 | regmap_update_bits(gpr, IOMUXC_GPR1, IMX6UL_GPR1_ENET_CLK_DIR, | |
| 28 | IMX6UL_GPR1_ENET_CLK_OUTPUT); | |
| 29 | else | |
| 30 | pr_err("failed to find fsl,imx6ul-iomux-gpr regmap\n"); | |
| 31 | ||
| 32 | } | |
| 33 | ||
| 34 | static int ksz8081_phy_fixup(struct phy_device *dev) | |
| 35 | { | |
| 36 | if (dev && dev->interface == PHY_INTERFACE_MODE_MII) { | |
| 37 | phy_write(dev, 0x1f, 0x8110); | |
| 38 | phy_write(dev, 0x16, 0x201); | |
| 39 | } else if (dev && dev->interface == PHY_INTERFACE_MODE_RMII) { | |
| 40 | phy_write(dev, 0x1f, 0x8190); | |
| 41 | phy_write(dev, 0x16, 0x202); | |
| 42 | } | |
| 43 | ||
| 44 | return 0; | |
| 45 | } | |
| 46 | ||
| 47 | static void __init imx6ul_enet_phy_init(void) | |
| 48 | { | |
| 6be4b0da | 49 | if (IS_BUILTIN(CONFIG_PHYLIB)) |
| 20c15226 | 50 | phy_register_fixup_for_uid(PHY_ID_KSZ8081, MICREL_PHY_ID_MASK, |
| 6be4b0da | 51 | ksz8081_phy_fixup); |
| 709bc065 FD |
52 | } |
| 53 | ||
| 54 | static inline void imx6ul_enet_init(void) | |
| 55 | { | |
| 56 | imx6ul_enet_clk_init(); | |
| 57 | imx6ul_enet_phy_init(); | |
| 58 | } | |
| 59 | ||
| 022d0716 FL |
60 | static void __init imx6ul_init_machine(void) |
| 61 | { | |
| 62 | struct device *parent; | |
| 63 | ||
| 64 | parent = imx_soc_device_init(); | |
| 65 | if (parent == NULL) | |
| 66 | pr_warn("failed to initialize soc device\n"); | |
| 67 | ||
| cfee6b58 | 68 | of_platform_default_populate(NULL, NULL, parent); |
| 709bc065 | 69 | imx6ul_enet_init(); |
| 022d0716 | 70 | imx_anatop_init(); |
| ee4a5f83 | 71 | imx6ul_pm_init(); |
| 022d0716 FL |
72 | } |
| 73 | ||
| 74 | static void __init imx6ul_init_irq(void) | |
| 75 | { | |
| 76 | imx_init_revision_from_anatop(); | |
| 77 | imx_src_init(); | |
| 78 | irqchip_init(); | |
| ee4a5f83 | 79 | imx6_pm_ccm_init("fsl,imx6ul-ccm"); |
| 022d0716 FL |
80 | } |
| 81 | ||
| 7f730819 BP |
82 | static void __init imx6ul_init_late(void) |
| 83 | { | |
| 547e8f52 AH |
84 | imx6sx_cpuidle_init(); |
| 85 | ||
| 7f730819 BP |
86 | if (IS_ENABLED(CONFIG_ARM_IMX6Q_CPUFREQ)) |
| 87 | platform_device_register_simple("imx6q-cpufreq", -1, NULL, 0); | |
| 88 | } | |
| 89 | ||
| 5d484175 | 90 | static const char * const imx6ul_dt_compat[] __initconst = { |
| 022d0716 FL |
91 | "fsl,imx6ul", |
| 92 | NULL, | |
| 93 | }; | |
| 94 | ||
| 95 | DT_MACHINE_START(IMX6UL, "Freescale i.MX6 Ultralite (Device Tree)") | |
| 96 | .init_irq = imx6ul_init_irq, | |
| 97 | .init_machine = imx6ul_init_machine, | |
| 7f730819 | 98 | .init_late = imx6ul_init_late, |
| 022d0716 FL |
99 | .dt_compat = imx6ul_dt_compat, |
| 100 | MACHINE_END |