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7359154e PW |
1 | /* |
2 | * omap_hwmod_3xxx_data.c - hardware modules present on the OMAP3xxx chips | |
3 | * | |
78183f3f | 4 | * Copyright (C) 2009-2011 Nokia Corporation |
0a78c5c5 | 5 | * Copyright (C) 2012 Texas Instruments, Inc. |
7359154e PW |
6 | * Paul Walmsley |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * The data in this file should be completely autogeneratable from | |
13 | * the TI hardware database or other technical documentation. | |
14 | * | |
15 | * XXX these should be marked initdata for multi-OMAP kernels | |
16 | */ | |
3a8761c0 TL |
17 | |
18 | #include <linux/i2c-omap.h> | |
b86aeafc | 19 | #include <linux/power/smartreflex.h> |
4b25408f | 20 | #include <linux/platform_data/gpio-omap.h> |
55143438 | 21 | #include <linux/platform_data/hsmmc-omap.h> |
b86aeafc | 22 | |
45c3eb7d | 23 | #include <linux/omap-dma.h> |
79e3cb22 | 24 | #include "l3_3xxx.h" |
957988c7 | 25 | #include "l4_3xxx.h" |
2203747c AB |
26 | #include <linux/platform_data/asoc-ti-mcbsp.h> |
27 | #include <linux/platform_data/spi-omap2-mcspi.h> | |
ce722d26 | 28 | #include <plat/dmtimer.h> |
7359154e | 29 | |
dbc04161 | 30 | #include "soc.h" |
2a296c8f | 31 | #include "omap_hwmod.h" |
43b40992 | 32 | #include "omap_hwmod_common_data.h" |
7359154e | 33 | #include "prm-regbits-34xx.h" |
6b667f88 | 34 | #include "cm-regbits-34xx.h" |
d5e7c864 | 35 | |
3a8761c0 | 36 | #include "i2c.h" |
ff2516fb | 37 | #include "wd_timer.h" |
3d82cbbb | 38 | #include "serial.h" |
7359154e PW |
39 | |
40 | /* | |
41 | * OMAP3xxx hardware module integration data | |
42 | * | |
844a3b63 | 43 | * All of the data in this section should be autogeneratable from the |
7359154e PW |
44 | * TI hardware database or other technical documentation. Data that |
45 | * is driver-specific or driver-kernel integration-specific belongs | |
46 | * elsewhere. | |
47 | */ | |
48 | ||
13eeb0f3 TL |
49 | #define AM35XX_IPSS_USBOTGSS_BASE 0x5C040000 |
50 | ||
844a3b63 PW |
51 | /* |
52 | * IP blocks | |
53 | */ | |
7359154e | 54 | |
844a3b63 | 55 | /* L3 */ |
4bb194dc | 56 | static struct omap_hwmod_irq_info omap3xxx_l3_main_irqs[] = { |
7d7e1eba TL |
57 | { .irq = 9 + OMAP_INTC_START, }, |
58 | { .irq = 10 + OMAP_INTC_START, }, | |
59 | { .irq = -1 }, | |
4bb194dc | 60 | }; |
61 | ||
4a7cf90a | 62 | static struct omap_hwmod omap3xxx_l3_main_hwmod = { |
fa98347e | 63 | .name = "l3_main", |
43b40992 | 64 | .class = &l3_hwmod_class, |
0d619a89 | 65 | .mpu_irqs = omap3xxx_l3_main_irqs, |
2eb1875d | 66 | .flags = HWMOD_NO_IDLEST, |
7359154e PW |
67 | }; |
68 | ||
844a3b63 PW |
69 | /* L4 CORE */ |
70 | static struct omap_hwmod omap3xxx_l4_core_hwmod = { | |
71 | .name = "l4_core", | |
72 | .class = &l4_hwmod_class, | |
73 | .flags = HWMOD_NO_IDLEST, | |
870ea2b8 | 74 | }; |
7359154e | 75 | |
844a3b63 PW |
76 | /* L4 PER */ |
77 | static struct omap_hwmod omap3xxx_l4_per_hwmod = { | |
78 | .name = "l4_per", | |
79 | .class = &l4_hwmod_class, | |
80 | .flags = HWMOD_NO_IDLEST, | |
273ff8c3 | 81 | }; |
844a3b63 PW |
82 | |
83 | /* L4 WKUP */ | |
84 | static struct omap_hwmod omap3xxx_l4_wkup_hwmod = { | |
85 | .name = "l4_wkup", | |
86 | .class = &l4_hwmod_class, | |
87 | .flags = HWMOD_NO_IDLEST, | |
7359154e PW |
88 | }; |
89 | ||
844a3b63 PW |
90 | /* L4 SEC */ |
91 | static struct omap_hwmod omap3xxx_l4_sec_hwmod = { | |
92 | .name = "l4_sec", | |
93 | .class = &l4_hwmod_class, | |
94 | .flags = HWMOD_NO_IDLEST, | |
4a9efb62 PW |
95 | }; |
96 | ||
844a3b63 | 97 | /* MPU */ |
ee75d95c | 98 | static struct omap_hwmod_irq_info omap3xxx_mpu_irqs[] = { |
3dc3401c | 99 | { .name = "pmu", .irq = 3 + OMAP_INTC_START }, |
ee75d95c JH |
100 | { .irq = -1 } |
101 | }; | |
102 | ||
844a3b63 PW |
103 | static struct omap_hwmod omap3xxx_mpu_hwmod = { |
104 | .name = "mpu", | |
ee75d95c | 105 | .mpu_irqs = omap3xxx_mpu_irqs, |
844a3b63 PW |
106 | .class = &mpu_hwmod_class, |
107 | .main_clk = "arm_fck", | |
b163605e PW |
108 | }; |
109 | ||
844a3b63 | 110 | /* IVA2 (IVA2) */ |
f42c5496 | 111 | static struct omap_hwmod_rst_info omap3xxx_iva_resets[] = { |
ed733619 TK |
112 | { .name = "logic", .rst_shift = 0, .st_shift = 8 }, |
113 | { .name = "seq0", .rst_shift = 1, .st_shift = 9 }, | |
114 | { .name = "seq1", .rst_shift = 2, .st_shift = 10 }, | |
f42c5496 PW |
115 | }; |
116 | ||
844a3b63 PW |
117 | static struct omap_hwmod omap3xxx_iva_hwmod = { |
118 | .name = "iva", | |
119 | .class = &iva_hwmod_class, | |
f42c5496 PW |
120 | .clkdm_name = "iva2_clkdm", |
121 | .rst_lines = omap3xxx_iva_resets, | |
122 | .rst_lines_cnt = ARRAY_SIZE(omap3xxx_iva_resets), | |
123 | .main_clk = "iva2_ck", | |
ed733619 TK |
124 | .prcm = { |
125 | .omap2 = { | |
126 | .module_offs = OMAP3430_IVA2_MOD, | |
127 | .prcm_reg_id = 1, | |
128 | .module_bit = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT, | |
129 | .idlest_reg_id = 1, | |
130 | .idlest_idle_bit = OMAP3430_ST_IVA2_SHIFT, | |
131 | } | |
132 | }, | |
4a9efb62 PW |
133 | }; |
134 | ||
c7dad45f JH |
135 | /* |
136 | * 'debugss' class | |
137 | * debug and emulation sub system | |
138 | */ | |
139 | ||
140 | static struct omap_hwmod_class omap3xxx_debugss_hwmod_class = { | |
141 | .name = "debugss", | |
142 | }; | |
143 | ||
144 | /* debugss */ | |
145 | static struct omap_hwmod omap3xxx_debugss_hwmod = { | |
146 | .name = "debugss", | |
147 | .class = &omap3xxx_debugss_hwmod_class, | |
148 | .clkdm_name = "emu_clkdm", | |
149 | .main_clk = "emu_src_ck", | |
150 | .flags = HWMOD_NO_IDLEST, | |
151 | }; | |
152 | ||
844a3b63 | 153 | /* timer class */ |
844a3b63 PW |
154 | static struct omap_hwmod_class_sysconfig omap3xxx_timer_sysc = { |
155 | .rev_offs = 0x0000, | |
156 | .sysc_offs = 0x0010, | |
157 | .syss_offs = 0x0014, | |
725a8fe3 JH |
158 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY | |
159 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | | |
f3a13e72 JH |
160 | SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE | |
161 | SYSS_HAS_RESET_STATUS), | |
844a3b63 | 162 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), |
10759e82 | 163 | .clockact = CLOCKACT_TEST_ICLK, |
844a3b63 | 164 | .sysc_fields = &omap_hwmod_sysc_type1, |
b163605e PW |
165 | }; |
166 | ||
844a3b63 PW |
167 | static struct omap_hwmod_class omap3xxx_timer_hwmod_class = { |
168 | .name = "timer", | |
169 | .sysc = &omap3xxx_timer_sysc, | |
046465b7 KH |
170 | }; |
171 | ||
844a3b63 PW |
172 | /* secure timers dev attribute */ |
173 | static struct omap_timer_capability_dev_attr capability_secure_dev_attr = { | |
139486fa | 174 | .timer_capability = OMAP_TIMER_ALWON | OMAP_TIMER_SECURE, |
046465b7 KH |
175 | }; |
176 | ||
844a3b63 PW |
177 | /* always-on timers dev attribute */ |
178 | static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = { | |
179 | .timer_capability = OMAP_TIMER_ALWON, | |
046465b7 KH |
180 | }; |
181 | ||
844a3b63 PW |
182 | /* pwm timers dev attribute */ |
183 | static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = { | |
184 | .timer_capability = OMAP_TIMER_HAS_PWM, | |
046465b7 KH |
185 | }; |
186 | ||
5c3e4ec4 JH |
187 | /* timers with DSP interrupt dev attribute */ |
188 | static struct omap_timer_capability_dev_attr capability_dsp_dev_attr = { | |
189 | .timer_capability = OMAP_TIMER_HAS_DSP_IRQ, | |
190 | }; | |
191 | ||
192 | /* pwm timers with DSP interrupt dev attribute */ | |
193 | static struct omap_timer_capability_dev_attr capability_dsp_pwm_dev_attr = { | |
194 | .timer_capability = OMAP_TIMER_HAS_DSP_IRQ | OMAP_TIMER_HAS_PWM, | |
195 | }; | |
196 | ||
844a3b63 PW |
197 | /* timer1 */ |
198 | static struct omap_hwmod omap3xxx_timer1_hwmod = { | |
199 | .name = "timer1", | |
200 | .mpu_irqs = omap2_timer1_mpu_irqs, | |
201 | .main_clk = "gpt1_fck", | |
202 | .prcm = { | |
203 | .omap2 = { | |
204 | .prcm_reg_id = 1, | |
205 | .module_bit = OMAP3430_EN_GPT1_SHIFT, | |
206 | .module_offs = WKUP_MOD, | |
207 | .idlest_reg_id = 1, | |
208 | .idlest_idle_bit = OMAP3430_ST_GPT1_SHIFT, | |
209 | }, | |
046465b7 | 210 | }, |
844a3b63 | 211 | .dev_attr = &capability_alwon_dev_attr, |
725a8fe3 | 212 | .class = &omap3xxx_timer_hwmod_class, |
10759e82 | 213 | .flags = HWMOD_SET_DEFAULT_CLOCKACT, |
046465b7 KH |
214 | }; |
215 | ||
844a3b63 PW |
216 | /* timer2 */ |
217 | static struct omap_hwmod omap3xxx_timer2_hwmod = { | |
218 | .name = "timer2", | |
219 | .mpu_irqs = omap2_timer2_mpu_irqs, | |
220 | .main_clk = "gpt2_fck", | |
221 | .prcm = { | |
222 | .omap2 = { | |
223 | .prcm_reg_id = 1, | |
224 | .module_bit = OMAP3430_EN_GPT2_SHIFT, | |
225 | .module_offs = OMAP3430_PER_MOD, | |
226 | .idlest_reg_id = 1, | |
227 | .idlest_idle_bit = OMAP3430_ST_GPT2_SHIFT, | |
228 | }, | |
229 | }, | |
725a8fe3 | 230 | .class = &omap3xxx_timer_hwmod_class, |
10759e82 | 231 | .flags = HWMOD_SET_DEFAULT_CLOCKACT, |
046465b7 KH |
232 | }; |
233 | ||
844a3b63 PW |
234 | /* timer3 */ |
235 | static struct omap_hwmod omap3xxx_timer3_hwmod = { | |
236 | .name = "timer3", | |
237 | .mpu_irqs = omap2_timer3_mpu_irqs, | |
238 | .main_clk = "gpt3_fck", | |
239 | .prcm = { | |
240 | .omap2 = { | |
241 | .prcm_reg_id = 1, | |
242 | .module_bit = OMAP3430_EN_GPT3_SHIFT, | |
243 | .module_offs = OMAP3430_PER_MOD, | |
244 | .idlest_reg_id = 1, | |
245 | .idlest_idle_bit = OMAP3430_ST_GPT3_SHIFT, | |
246 | }, | |
247 | }, | |
844a3b63 | 248 | .class = &omap3xxx_timer_hwmod_class, |
10759e82 | 249 | .flags = HWMOD_SET_DEFAULT_CLOCKACT, |
046465b7 KH |
250 | }; |
251 | ||
844a3b63 PW |
252 | /* timer4 */ |
253 | static struct omap_hwmod omap3xxx_timer4_hwmod = { | |
254 | .name = "timer4", | |
255 | .mpu_irqs = omap2_timer4_mpu_irqs, | |
256 | .main_clk = "gpt4_fck", | |
257 | .prcm = { | |
258 | .omap2 = { | |
259 | .prcm_reg_id = 1, | |
260 | .module_bit = OMAP3430_EN_GPT4_SHIFT, | |
261 | .module_offs = OMAP3430_PER_MOD, | |
262 | .idlest_reg_id = 1, | |
263 | .idlest_idle_bit = OMAP3430_ST_GPT4_SHIFT, | |
264 | }, | |
265 | }, | |
844a3b63 | 266 | .class = &omap3xxx_timer_hwmod_class, |
10759e82 | 267 | .flags = HWMOD_SET_DEFAULT_CLOCKACT, |
046465b7 KH |
268 | }; |
269 | ||
844a3b63 PW |
270 | /* timer5 */ |
271 | static struct omap_hwmod omap3xxx_timer5_hwmod = { | |
272 | .name = "timer5", | |
273 | .mpu_irqs = omap2_timer5_mpu_irqs, | |
274 | .main_clk = "gpt5_fck", | |
275 | .prcm = { | |
276 | .omap2 = { | |
277 | .prcm_reg_id = 1, | |
278 | .module_bit = OMAP3430_EN_GPT5_SHIFT, | |
279 | .module_offs = OMAP3430_PER_MOD, | |
280 | .idlest_reg_id = 1, | |
281 | .idlest_idle_bit = OMAP3430_ST_GPT5_SHIFT, | |
282 | }, | |
4bf90f65 | 283 | }, |
5c3e4ec4 | 284 | .dev_attr = &capability_dsp_dev_attr, |
844a3b63 | 285 | .class = &omap3xxx_timer_hwmod_class, |
10759e82 | 286 | .flags = HWMOD_SET_DEFAULT_CLOCKACT, |
4bf90f65 KM |
287 | }; |
288 | ||
844a3b63 PW |
289 | /* timer6 */ |
290 | static struct omap_hwmod omap3xxx_timer6_hwmod = { | |
291 | .name = "timer6", | |
292 | .mpu_irqs = omap2_timer6_mpu_irqs, | |
293 | .main_clk = "gpt6_fck", | |
294 | .prcm = { | |
295 | .omap2 = { | |
296 | .prcm_reg_id = 1, | |
297 | .module_bit = OMAP3430_EN_GPT6_SHIFT, | |
298 | .module_offs = OMAP3430_PER_MOD, | |
299 | .idlest_reg_id = 1, | |
300 | .idlest_idle_bit = OMAP3430_ST_GPT6_SHIFT, | |
301 | }, | |
302 | }, | |
5c3e4ec4 | 303 | .dev_attr = &capability_dsp_dev_attr, |
844a3b63 | 304 | .class = &omap3xxx_timer_hwmod_class, |
10759e82 | 305 | .flags = HWMOD_SET_DEFAULT_CLOCKACT, |
4bf90f65 KM |
306 | }; |
307 | ||
844a3b63 PW |
308 | /* timer7 */ |
309 | static struct omap_hwmod omap3xxx_timer7_hwmod = { | |
310 | .name = "timer7", | |
311 | .mpu_irqs = omap2_timer7_mpu_irqs, | |
312 | .main_clk = "gpt7_fck", | |
313 | .prcm = { | |
4fe20e97 | 314 | .omap2 = { |
844a3b63 PW |
315 | .prcm_reg_id = 1, |
316 | .module_bit = OMAP3430_EN_GPT7_SHIFT, | |
317 | .module_offs = OMAP3430_PER_MOD, | |
318 | .idlest_reg_id = 1, | |
319 | .idlest_idle_bit = OMAP3430_ST_GPT7_SHIFT, | |
320 | }, | |
4fe20e97 | 321 | }, |
5c3e4ec4 | 322 | .dev_attr = &capability_dsp_dev_attr, |
844a3b63 | 323 | .class = &omap3xxx_timer_hwmod_class, |
10759e82 | 324 | .flags = HWMOD_SET_DEFAULT_CLOCKACT, |
4fe20e97 RN |
325 | }; |
326 | ||
844a3b63 PW |
327 | /* timer8 */ |
328 | static struct omap_hwmod omap3xxx_timer8_hwmod = { | |
329 | .name = "timer8", | |
330 | .mpu_irqs = omap2_timer8_mpu_irqs, | |
331 | .main_clk = "gpt8_fck", | |
332 | .prcm = { | |
4fe20e97 | 333 | .omap2 = { |
844a3b63 PW |
334 | .prcm_reg_id = 1, |
335 | .module_bit = OMAP3430_EN_GPT8_SHIFT, | |
336 | .module_offs = OMAP3430_PER_MOD, | |
337 | .idlest_reg_id = 1, | |
338 | .idlest_idle_bit = OMAP3430_ST_GPT8_SHIFT, | |
339 | }, | |
4fe20e97 | 340 | }, |
5c3e4ec4 | 341 | .dev_attr = &capability_dsp_pwm_dev_attr, |
844a3b63 | 342 | .class = &omap3xxx_timer_hwmod_class, |
10759e82 | 343 | .flags = HWMOD_SET_DEFAULT_CLOCKACT, |
4fe20e97 RN |
344 | }; |
345 | ||
844a3b63 PW |
346 | /* timer9 */ |
347 | static struct omap_hwmod omap3xxx_timer9_hwmod = { | |
348 | .name = "timer9", | |
349 | .mpu_irqs = omap2_timer9_mpu_irqs, | |
350 | .main_clk = "gpt9_fck", | |
351 | .prcm = { | |
352 | .omap2 = { | |
353 | .prcm_reg_id = 1, | |
354 | .module_bit = OMAP3430_EN_GPT9_SHIFT, | |
355 | .module_offs = OMAP3430_PER_MOD, | |
356 | .idlest_reg_id = 1, | |
357 | .idlest_idle_bit = OMAP3430_ST_GPT9_SHIFT, | |
358 | }, | |
4fe20e97 | 359 | }, |
844a3b63 PW |
360 | .dev_attr = &capability_pwm_dev_attr, |
361 | .class = &omap3xxx_timer_hwmod_class, | |
10759e82 | 362 | .flags = HWMOD_SET_DEFAULT_CLOCKACT, |
4fe20e97 RN |
363 | }; |
364 | ||
844a3b63 PW |
365 | /* timer10 */ |
366 | static struct omap_hwmod omap3xxx_timer10_hwmod = { | |
367 | .name = "timer10", | |
368 | .mpu_irqs = omap2_timer10_mpu_irqs, | |
369 | .main_clk = "gpt10_fck", | |
370 | .prcm = { | |
4fe20e97 | 371 | .omap2 = { |
844a3b63 PW |
372 | .prcm_reg_id = 1, |
373 | .module_bit = OMAP3430_EN_GPT10_SHIFT, | |
374 | .module_offs = CORE_MOD, | |
375 | .idlest_reg_id = 1, | |
376 | .idlest_idle_bit = OMAP3430_ST_GPT10_SHIFT, | |
377 | }, | |
4fe20e97 | 378 | }, |
844a3b63 | 379 | .dev_attr = &capability_pwm_dev_attr, |
725a8fe3 | 380 | .class = &omap3xxx_timer_hwmod_class, |
10759e82 | 381 | .flags = HWMOD_SET_DEFAULT_CLOCKACT, |
4fe20e97 RN |
382 | }; |
383 | ||
844a3b63 PW |
384 | /* timer11 */ |
385 | static struct omap_hwmod omap3xxx_timer11_hwmod = { | |
386 | .name = "timer11", | |
387 | .mpu_irqs = omap2_timer11_mpu_irqs, | |
388 | .main_clk = "gpt11_fck", | |
389 | .prcm = { | |
390 | .omap2 = { | |
391 | .prcm_reg_id = 1, | |
392 | .module_bit = OMAP3430_EN_GPT11_SHIFT, | |
393 | .module_offs = CORE_MOD, | |
394 | .idlest_reg_id = 1, | |
395 | .idlest_idle_bit = OMAP3430_ST_GPT11_SHIFT, | |
396 | }, | |
397 | }, | |
398 | .dev_attr = &capability_pwm_dev_attr, | |
399 | .class = &omap3xxx_timer_hwmod_class, | |
10759e82 | 400 | .flags = HWMOD_SET_DEFAULT_CLOCKACT, |
d62bc78a NM |
401 | }; |
402 | ||
844a3b63 PW |
403 | /* timer12 */ |
404 | static struct omap_hwmod_irq_info omap3xxx_timer12_mpu_irqs[] = { | |
7d7e1eba TL |
405 | { .irq = 95 + OMAP_INTC_START, }, |
406 | { .irq = -1 }, | |
d62bc78a NM |
407 | }; |
408 | ||
844a3b63 PW |
409 | static struct omap_hwmod omap3xxx_timer12_hwmod = { |
410 | .name = "timer12", | |
411 | .mpu_irqs = omap3xxx_timer12_mpu_irqs, | |
412 | .main_clk = "gpt12_fck", | |
413 | .prcm = { | |
414 | .omap2 = { | |
415 | .prcm_reg_id = 1, | |
416 | .module_bit = OMAP3430_EN_GPT12_SHIFT, | |
417 | .module_offs = WKUP_MOD, | |
418 | .idlest_reg_id = 1, | |
419 | .idlest_idle_bit = OMAP3430_ST_GPT12_SHIFT, | |
420 | }, | |
d3442726 | 421 | }, |
844a3b63 PW |
422 | .dev_attr = &capability_secure_dev_attr, |
423 | .class = &omap3xxx_timer_hwmod_class, | |
10759e82 | 424 | .flags = HWMOD_SET_DEFAULT_CLOCKACT, |
d3442726 TG |
425 | }; |
426 | ||
844a3b63 PW |
427 | /* |
428 | * 'wd_timer' class | |
429 | * 32-bit watchdog upward counter that generates a pulse on the reset pin on | |
430 | * overflow condition | |
431 | */ | |
432 | ||
433 | static struct omap_hwmod_class_sysconfig omap3xxx_wd_timer_sysc = { | |
434 | .rev_offs = 0x0000, | |
435 | .sysc_offs = 0x0010, | |
436 | .syss_offs = 0x0014, | |
437 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE | | |
438 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | | |
439 | SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | |
440 | SYSS_HAS_RESET_STATUS), | |
441 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
442 | .sysc_fields = &omap_hwmod_sysc_type1, | |
d3442726 TG |
443 | }; |
444 | ||
844a3b63 PW |
445 | /* I2C common */ |
446 | static struct omap_hwmod_class_sysconfig i2c_sysc = { | |
447 | .rev_offs = 0x00, | |
448 | .sysc_offs = 0x20, | |
449 | .syss_offs = 0x10, | |
450 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | | |
451 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | | |
452 | SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), | |
453 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
454 | .clockact = CLOCKACT_TEST_ICLK, | |
455 | .sysc_fields = &omap_hwmod_sysc_type1, | |
d3442726 TG |
456 | }; |
457 | ||
844a3b63 PW |
458 | static struct omap_hwmod_class omap3xxx_wd_timer_hwmod_class = { |
459 | .name = "wd_timer", | |
460 | .sysc = &omap3xxx_wd_timer_sysc, | |
414e4128 KH |
461 | .pre_shutdown = &omap2_wd_timer_disable, |
462 | .reset = &omap2_wd_timer_reset, | |
d3442726 TG |
463 | }; |
464 | ||
844a3b63 PW |
465 | static struct omap_hwmod omap3xxx_wd_timer2_hwmod = { |
466 | .name = "wd_timer2", | |
467 | .class = &omap3xxx_wd_timer_hwmod_class, | |
468 | .main_clk = "wdt2_fck", | |
469 | .prcm = { | |
470 | .omap2 = { | |
471 | .prcm_reg_id = 1, | |
472 | .module_bit = OMAP3430_EN_WDT2_SHIFT, | |
473 | .module_offs = WKUP_MOD, | |
474 | .idlest_reg_id = 1, | |
475 | .idlest_idle_bit = OMAP3430_ST_WDT2_SHIFT, | |
476 | }, | |
477 | }, | |
478 | /* | |
479 | * XXX: Use software supervised mode, HW supervised smartidle seems to | |
480 | * block CORE power domain idle transitions. Maybe a HW bug in wdt2? | |
481 | */ | |
482 | .flags = HWMOD_SWSUP_SIDLE, | |
483 | }; | |
870ea2b8 | 484 | |
844a3b63 PW |
485 | /* UART1 */ |
486 | static struct omap_hwmod omap3xxx_uart1_hwmod = { | |
487 | .name = "uart1", | |
488 | .mpu_irqs = omap2_uart1_mpu_irqs, | |
489 | .sdma_reqs = omap2_uart1_sdma_reqs, | |
490 | .main_clk = "uart1_fck", | |
a2fc3661 | 491 | .flags = DEBUG_TI81XXUART1_FLAGS | HWMOD_SWSUP_SIDLE, |
844a3b63 PW |
492 | .prcm = { |
493 | .omap2 = { | |
494 | .module_offs = CORE_MOD, | |
495 | .prcm_reg_id = 1, | |
496 | .module_bit = OMAP3430_EN_UART1_SHIFT, | |
497 | .idlest_reg_id = 1, | |
498 | .idlest_idle_bit = OMAP3430_EN_UART1_SHIFT, | |
499 | }, | |
870ea2b8 | 500 | }, |
844a3b63 | 501 | .class = &omap2_uart_class, |
870ea2b8 HH |
502 | }; |
503 | ||
844a3b63 PW |
504 | /* UART2 */ |
505 | static struct omap_hwmod omap3xxx_uart2_hwmod = { | |
506 | .name = "uart2", | |
507 | .mpu_irqs = omap2_uart2_mpu_irqs, | |
508 | .sdma_reqs = omap2_uart2_sdma_reqs, | |
509 | .main_clk = "uart2_fck", | |
a2fc3661 | 510 | .flags = DEBUG_TI81XXUART2_FLAGS | HWMOD_SWSUP_SIDLE, |
844a3b63 PW |
511 | .prcm = { |
512 | .omap2 = { | |
513 | .module_offs = CORE_MOD, | |
514 | .prcm_reg_id = 1, | |
515 | .module_bit = OMAP3430_EN_UART2_SHIFT, | |
516 | .idlest_reg_id = 1, | |
517 | .idlest_idle_bit = OMAP3430_EN_UART2_SHIFT, | |
518 | }, | |
519 | }, | |
520 | .class = &omap2_uart_class, | |
870ea2b8 HH |
521 | }; |
522 | ||
844a3b63 PW |
523 | /* UART3 */ |
524 | static struct omap_hwmod omap3xxx_uart3_hwmod = { | |
525 | .name = "uart3", | |
526 | .mpu_irqs = omap2_uart3_mpu_irqs, | |
527 | .sdma_reqs = omap2_uart3_sdma_reqs, | |
528 | .main_clk = "uart3_fck", | |
7dedd346 | 529 | .flags = DEBUG_OMAP3UART3_FLAGS | DEBUG_TI81XXUART3_FLAGS | |
a2fc3661 | 530 | HWMOD_SWSUP_SIDLE, |
844a3b63 PW |
531 | .prcm = { |
532 | .omap2 = { | |
533 | .module_offs = OMAP3430_PER_MOD, | |
534 | .prcm_reg_id = 1, | |
535 | .module_bit = OMAP3430_EN_UART3_SHIFT, | |
536 | .idlest_reg_id = 1, | |
537 | .idlest_idle_bit = OMAP3430_EN_UART3_SHIFT, | |
538 | }, | |
273ff8c3 | 539 | }, |
844a3b63 | 540 | .class = &omap2_uart_class, |
273ff8c3 HH |
541 | }; |
542 | ||
844a3b63 PW |
543 | /* UART4 */ |
544 | static struct omap_hwmod_irq_info uart4_mpu_irqs[] = { | |
7d7e1eba TL |
545 | { .irq = 80 + OMAP_INTC_START, }, |
546 | { .irq = -1 }, | |
273ff8c3 HH |
547 | }; |
548 | ||
844a3b63 | 549 | static struct omap_hwmod_dma_info uart4_sdma_reqs[] = { |
0fd8824f JN |
550 | { .name = "rx", .dma_req = 82, }, |
551 | { .name = "tx", .dma_req = 81, }, | |
844a3b63 | 552 | { .dma_req = -1 } |
7359154e PW |
553 | }; |
554 | ||
844a3b63 PW |
555 | static struct omap_hwmod omap36xx_uart4_hwmod = { |
556 | .name = "uart4", | |
557 | .mpu_irqs = uart4_mpu_irqs, | |
558 | .sdma_reqs = uart4_sdma_reqs, | |
559 | .main_clk = "uart4_fck", | |
a2fc3661 | 560 | .flags = DEBUG_OMAP3UART4_FLAGS | HWMOD_SWSUP_SIDLE, |
844a3b63 PW |
561 | .prcm = { |
562 | .omap2 = { | |
563 | .module_offs = OMAP3430_PER_MOD, | |
564 | .prcm_reg_id = 1, | |
565 | .module_bit = OMAP3630_EN_UART4_SHIFT, | |
566 | .idlest_reg_id = 1, | |
567 | .idlest_idle_bit = OMAP3630_EN_UART4_SHIFT, | |
568 | }, | |
569 | }, | |
570 | .class = &omap2_uart_class, | |
7359154e PW |
571 | }; |
572 | ||
844a3b63 | 573 | static struct omap_hwmod_irq_info am35xx_uart4_mpu_irqs[] = { |
7d7e1eba TL |
574 | { .irq = 84 + OMAP_INTC_START, }, |
575 | { .irq = -1 }, | |
43085705 PW |
576 | }; |
577 | ||
844a3b63 | 578 | static struct omap_hwmod_dma_info am35xx_uart4_sdma_reqs[] = { |
0fd8824f JN |
579 | { .name = "rx", .dma_req = 55, }, |
580 | { .name = "tx", .dma_req = 54, }, | |
bf765237 | 581 | { .dma_req = -1 } |
7359154e PW |
582 | }; |
583 | ||
82ee620d PW |
584 | /* |
585 | * XXX AM35xx UART4 cannot complete its softreset without uart1_fck or | |
586 | * uart2_fck being enabled. So we add uart1_fck as an optional clock, | |
587 | * below, and set the HWMOD_CONTROL_OPT_CLKS_IN_RESET. This really | |
588 | * should not be needed. The functional clock structure of the AM35xx | |
589 | * UART4 is extremely unclear and opaque; it is unclear what the role | |
590 | * of uart1/2_fck is for the UART4. Any clarification from either | |
591 | * empirical testing or the AM3505/3517 hardware designers would be | |
592 | * most welcome. | |
593 | */ | |
594 | static struct omap_hwmod_opt_clk am35xx_uart4_opt_clks[] = { | |
595 | { .role = "softreset_uart1_fck", .clk = "uart1_fck" }, | |
596 | }; | |
597 | ||
844a3b63 PW |
598 | static struct omap_hwmod am35xx_uart4_hwmod = { |
599 | .name = "uart4", | |
600 | .mpu_irqs = am35xx_uart4_mpu_irqs, | |
601 | .sdma_reqs = am35xx_uart4_sdma_reqs, | |
602 | .main_clk = "uart4_fck", | |
603 | .prcm = { | |
604 | .omap2 = { | |
605 | .module_offs = CORE_MOD, | |
606 | .prcm_reg_id = 1, | |
bf765237 | 607 | .module_bit = AM35XX_EN_UART4_SHIFT, |
844a3b63 | 608 | .idlest_reg_id = 1, |
bf765237 | 609 | .idlest_idle_bit = AM35XX_ST_UART4_SHIFT, |
844a3b63 PW |
610 | }, |
611 | }, | |
82ee620d PW |
612 | .opt_clks = am35xx_uart4_opt_clks, |
613 | .opt_clks_cnt = ARRAY_SIZE(am35xx_uart4_opt_clks), | |
614 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | |
844a3b63 PW |
615 | .class = &omap2_uart_class, |
616 | }; | |
617 | ||
618 | static struct omap_hwmod_class i2c_class = { | |
619 | .name = "i2c", | |
620 | .sysc = &i2c_sysc, | |
621 | .rev = OMAP_I2C_IP_VERSION_1, | |
622 | .reset = &omap_i2c_reset, | |
623 | }; | |
624 | ||
625 | static struct omap_hwmod_dma_info omap3xxx_dss_sdma_chs[] = { | |
626 | { .name = "dispc", .dma_req = 5 }, | |
627 | { .name = "dsi1", .dma_req = 74 }, | |
628 | { .dma_req = -1 } | |
43085705 PW |
629 | }; |
630 | ||
844a3b63 PW |
631 | /* dss */ |
632 | static struct omap_hwmod_opt_clk dss_opt_clks[] = { | |
633 | /* | |
634 | * The DSS HW needs all DSS clocks enabled during reset. The dss_core | |
635 | * driver does not use these clocks. | |
636 | */ | |
637 | { .role = "sys_clk", .clk = "dss2_alwon_fck" }, | |
638 | { .role = "tv_clk", .clk = "dss_tv_fck" }, | |
639 | /* required only on OMAP3430 */ | |
640 | { .role = "tv_dac_clk", .clk = "dss_96m_fck" }, | |
7359154e PW |
641 | }; |
642 | ||
844a3b63 PW |
643 | static struct omap_hwmod omap3430es1_dss_core_hwmod = { |
644 | .name = "dss_core", | |
645 | .class = &omap2_dss_hwmod_class, | |
646 | .main_clk = "dss1_alwon_fck", /* instead of dss_fck */ | |
647 | .sdma_reqs = omap3xxx_dss_sdma_chs, | |
648 | .prcm = { | |
649 | .omap2 = { | |
650 | .prcm_reg_id = 1, | |
651 | .module_bit = OMAP3430_EN_DSS1_SHIFT, | |
652 | .module_offs = OMAP3430_DSS_MOD, | |
653 | .idlest_reg_id = 1, | |
654 | .idlest_stdby_bit = OMAP3430ES1_ST_DSS_SHIFT, | |
655 | }, | |
656 | }, | |
657 | .opt_clks = dss_opt_clks, | |
658 | .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks), | |
659 | .flags = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET, | |
660 | }; | |
540064bf | 661 | |
844a3b63 PW |
662 | static struct omap_hwmod omap3xxx_dss_core_hwmod = { |
663 | .name = "dss_core", | |
664 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | |
665 | .class = &omap2_dss_hwmod_class, | |
666 | .main_clk = "dss1_alwon_fck", /* instead of dss_fck */ | |
667 | .sdma_reqs = omap3xxx_dss_sdma_chs, | |
668 | .prcm = { | |
669 | .omap2 = { | |
670 | .prcm_reg_id = 1, | |
671 | .module_bit = OMAP3430_EN_DSS1_SHIFT, | |
672 | .module_offs = OMAP3430_DSS_MOD, | |
673 | .idlest_reg_id = 1, | |
674 | .idlest_idle_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT, | |
675 | .idlest_stdby_bit = OMAP3430ES2_ST_DSS_STDBY_SHIFT, | |
676 | }, | |
677 | }, | |
678 | .opt_clks = dss_opt_clks, | |
679 | .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks), | |
540064bf KH |
680 | }; |
681 | ||
540064bf | 682 | /* |
844a3b63 PW |
683 | * 'dispc' class |
684 | * display controller | |
540064bf KH |
685 | */ |
686 | ||
844a3b63 | 687 | static struct omap_hwmod_class_sysconfig omap3_dispc_sysc = { |
ce722d26 TG |
688 | .rev_offs = 0x0000, |
689 | .sysc_offs = 0x0010, | |
690 | .syss_offs = 0x0014, | |
844a3b63 PW |
691 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE | |
692 | SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE | | |
693 | SYSC_HAS_ENAWAKEUP), | |
694 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
695 | MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), | |
ce722d26 | 696 | .sysc_fields = &omap_hwmod_sysc_type1, |
6b667f88 VC |
697 | }; |
698 | ||
844a3b63 PW |
699 | static struct omap_hwmod_class omap3_dispc_hwmod_class = { |
700 | .name = "dispc", | |
701 | .sysc = &omap3_dispc_sysc, | |
6b667f88 VC |
702 | }; |
703 | ||
844a3b63 PW |
704 | static struct omap_hwmod omap3xxx_dss_dispc_hwmod = { |
705 | .name = "dss_dispc", | |
706 | .class = &omap3_dispc_hwmod_class, | |
707 | .mpu_irqs = omap2_dispc_irqs, | |
708 | .main_clk = "dss1_alwon_fck", | |
709 | .prcm = { | |
710 | .omap2 = { | |
711 | .prcm_reg_id = 1, | |
712 | .module_bit = OMAP3430_EN_DSS1_SHIFT, | |
713 | .module_offs = OMAP3430_DSS_MOD, | |
714 | }, | |
715 | }, | |
716 | .flags = HWMOD_NO_IDLEST, | |
717 | .dev_attr = &omap2_3_dss_dispc_dev_attr | |
6b667f88 VC |
718 | }; |
719 | ||
844a3b63 PW |
720 | /* |
721 | * 'dsi' class | |
722 | * display serial interface controller | |
723 | */ | |
4fe20e97 | 724 | |
b46211d6 SR |
725 | static struct omap_hwmod_class_sysconfig omap3xxx_dsi_sysc = { |
726 | .rev_offs = 0x0000, | |
727 | .sysc_offs = 0x0010, | |
728 | .syss_offs = 0x0014, | |
729 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | |
730 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | | |
731 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), | |
732 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
733 | .sysc_fields = &omap_hwmod_sysc_type1, | |
734 | }; | |
735 | ||
844a3b63 PW |
736 | static struct omap_hwmod_class omap3xxx_dsi_hwmod_class = { |
737 | .name = "dsi", | |
b46211d6 | 738 | .sysc = &omap3xxx_dsi_sysc, |
c345c8b0 TKD |
739 | }; |
740 | ||
844a3b63 | 741 | static struct omap_hwmod_irq_info omap3xxx_dsi1_irqs[] = { |
7d7e1eba TL |
742 | { .irq = 25 + OMAP_INTC_START, }, |
743 | { .irq = -1 }, | |
c345c8b0 TKD |
744 | }; |
745 | ||
844a3b63 PW |
746 | /* dss_dsi1 */ |
747 | static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = { | |
748 | { .role = "sys_clk", .clk = "dss2_alwon_fck" }, | |
c345c8b0 TKD |
749 | }; |
750 | ||
844a3b63 PW |
751 | static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = { |
752 | .name = "dss_dsi1", | |
753 | .class = &omap3xxx_dsi_hwmod_class, | |
754 | .mpu_irqs = omap3xxx_dsi1_irqs, | |
755 | .main_clk = "dss1_alwon_fck", | |
756 | .prcm = { | |
757 | .omap2 = { | |
758 | .prcm_reg_id = 1, | |
759 | .module_bit = OMAP3430_EN_DSS1_SHIFT, | |
760 | .module_offs = OMAP3430_DSS_MOD, | |
761 | }, | |
ce722d26 | 762 | }, |
844a3b63 PW |
763 | .opt_clks = dss_dsi1_opt_clks, |
764 | .opt_clks_cnt = ARRAY_SIZE(dss_dsi1_opt_clks), | |
765 | .flags = HWMOD_NO_IDLEST, | |
6b667f88 VC |
766 | }; |
767 | ||
844a3b63 PW |
768 | static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = { |
769 | { .role = "ick", .clk = "dss_ick" }, | |
ce722d26 TG |
770 | }; |
771 | ||
844a3b63 PW |
772 | static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = { |
773 | .name = "dss_rfbi", | |
774 | .class = &omap2_rfbi_hwmod_class, | |
775 | .main_clk = "dss1_alwon_fck", | |
6b667f88 VC |
776 | .prcm = { |
777 | .omap2 = { | |
778 | .prcm_reg_id = 1, | |
844a3b63 PW |
779 | .module_bit = OMAP3430_EN_DSS1_SHIFT, |
780 | .module_offs = OMAP3430_DSS_MOD, | |
6b667f88 VC |
781 | }, |
782 | }, | |
844a3b63 PW |
783 | .opt_clks = dss_rfbi_opt_clks, |
784 | .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks), | |
785 | .flags = HWMOD_NO_IDLEST, | |
046465b7 KH |
786 | }; |
787 | ||
844a3b63 PW |
788 | static struct omap_hwmod_opt_clk dss_venc_opt_clks[] = { |
789 | /* required only on OMAP3430 */ | |
790 | { .role = "tv_dac_clk", .clk = "dss_96m_fck" }, | |
046465b7 KH |
791 | }; |
792 | ||
844a3b63 PW |
793 | static struct omap_hwmod omap3xxx_dss_venc_hwmod = { |
794 | .name = "dss_venc", | |
795 | .class = &omap2_venc_hwmod_class, | |
796 | .main_clk = "dss_tv_fck", | |
046465b7 KH |
797 | .prcm = { |
798 | .omap2 = { | |
046465b7 | 799 | .prcm_reg_id = 1, |
844a3b63 PW |
800 | .module_bit = OMAP3430_EN_DSS1_SHIFT, |
801 | .module_offs = OMAP3430_DSS_MOD, | |
046465b7 KH |
802 | }, |
803 | }, | |
844a3b63 PW |
804 | .opt_clks = dss_venc_opt_clks, |
805 | .opt_clks_cnt = ARRAY_SIZE(dss_venc_opt_clks), | |
806 | .flags = HWMOD_NO_IDLEST, | |
046465b7 KH |
807 | }; |
808 | ||
844a3b63 PW |
809 | /* I2C1 */ |
810 | static struct omap_i2c_dev_attr i2c1_dev_attr = { | |
811 | .fifo_depth = 8, /* bytes */ | |
972deb4f | 812 | .flags = OMAP_I2C_FLAG_BUS_SHIFT_2, |
046465b7 KH |
813 | }; |
814 | ||
844a3b63 PW |
815 | static struct omap_hwmod omap3xxx_i2c1_hwmod = { |
816 | .name = "i2c1", | |
817 | .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, | |
818 | .mpu_irqs = omap2_i2c1_mpu_irqs, | |
819 | .sdma_reqs = omap2_i2c1_sdma_reqs, | |
820 | .main_clk = "i2c1_fck", | |
046465b7 KH |
821 | .prcm = { |
822 | .omap2 = { | |
844a3b63 | 823 | .module_offs = CORE_MOD, |
046465b7 | 824 | .prcm_reg_id = 1, |
844a3b63 | 825 | .module_bit = OMAP3430_EN_I2C1_SHIFT, |
046465b7 | 826 | .idlest_reg_id = 1, |
844a3b63 | 827 | .idlest_idle_bit = OMAP3430_ST_I2C1_SHIFT, |
046465b7 KH |
828 | }, |
829 | }, | |
844a3b63 PW |
830 | .class = &i2c_class, |
831 | .dev_attr = &i2c1_dev_attr, | |
046465b7 KH |
832 | }; |
833 | ||
844a3b63 PW |
834 | /* I2C2 */ |
835 | static struct omap_i2c_dev_attr i2c2_dev_attr = { | |
836 | .fifo_depth = 8, /* bytes */ | |
972deb4f | 837 | .flags = OMAP_I2C_FLAG_BUS_SHIFT_2, |
046465b7 KH |
838 | }; |
839 | ||
844a3b63 PW |
840 | static struct omap_hwmod omap3xxx_i2c2_hwmod = { |
841 | .name = "i2c2", | |
842 | .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, | |
843 | .mpu_irqs = omap2_i2c2_mpu_irqs, | |
844 | .sdma_reqs = omap2_i2c2_sdma_reqs, | |
845 | .main_clk = "i2c2_fck", | |
046465b7 KH |
846 | .prcm = { |
847 | .omap2 = { | |
844a3b63 | 848 | .module_offs = CORE_MOD, |
046465b7 | 849 | .prcm_reg_id = 1, |
844a3b63 | 850 | .module_bit = OMAP3430_EN_I2C2_SHIFT, |
046465b7 | 851 | .idlest_reg_id = 1, |
844a3b63 | 852 | .idlest_idle_bit = OMAP3430_ST_I2C2_SHIFT, |
046465b7 KH |
853 | }, |
854 | }, | |
844a3b63 PW |
855 | .class = &i2c_class, |
856 | .dev_attr = &i2c2_dev_attr, | |
046465b7 KH |
857 | }; |
858 | ||
844a3b63 PW |
859 | /* I2C3 */ |
860 | static struct omap_i2c_dev_attr i2c3_dev_attr = { | |
861 | .fifo_depth = 64, /* bytes */ | |
972deb4f | 862 | .flags = OMAP_I2C_FLAG_BUS_SHIFT_2, |
844a3b63 | 863 | }; |
046465b7 | 864 | |
844a3b63 | 865 | static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = { |
7d7e1eba TL |
866 | { .irq = 61 + OMAP_INTC_START, }, |
867 | { .irq = -1 }, | |
046465b7 KH |
868 | }; |
869 | ||
844a3b63 | 870 | static struct omap_hwmod_dma_info i2c3_sdma_reqs[] = { |
0fd8824f JN |
871 | { .name = "tx", .dma_req = 25 }, |
872 | { .name = "rx", .dma_req = 26 }, | |
844a3b63 | 873 | { .dma_req = -1 } |
046465b7 KH |
874 | }; |
875 | ||
844a3b63 PW |
876 | static struct omap_hwmod omap3xxx_i2c3_hwmod = { |
877 | .name = "i2c3", | |
878 | .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, | |
879 | .mpu_irqs = i2c3_mpu_irqs, | |
880 | .sdma_reqs = i2c3_sdma_reqs, | |
881 | .main_clk = "i2c3_fck", | |
046465b7 KH |
882 | .prcm = { |
883 | .omap2 = { | |
844a3b63 | 884 | .module_offs = CORE_MOD, |
046465b7 | 885 | .prcm_reg_id = 1, |
844a3b63 | 886 | .module_bit = OMAP3430_EN_I2C3_SHIFT, |
046465b7 | 887 | .idlest_reg_id = 1, |
844a3b63 | 888 | .idlest_idle_bit = OMAP3430_ST_I2C3_SHIFT, |
046465b7 KH |
889 | }, |
890 | }, | |
844a3b63 PW |
891 | .class = &i2c_class, |
892 | .dev_attr = &i2c3_dev_attr, | |
4fe20e97 RN |
893 | }; |
894 | ||
844a3b63 PW |
895 | /* |
896 | * 'gpio' class | |
897 | * general purpose io module | |
898 | */ | |
4fe20e97 | 899 | |
844a3b63 PW |
900 | static struct omap_hwmod_class_sysconfig omap3xxx_gpio_sysc = { |
901 | .rev_offs = 0x0000, | |
902 | .sysc_offs = 0x0010, | |
903 | .syss_offs = 0x0014, | |
904 | .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | | |
905 | SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE | | |
906 | SYSS_HAS_RESET_STATUS), | |
907 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
908 | .sysc_fields = &omap_hwmod_sysc_type1, | |
4fe20e97 RN |
909 | }; |
910 | ||
844a3b63 PW |
911 | static struct omap_hwmod_class omap3xxx_gpio_hwmod_class = { |
912 | .name = "gpio", | |
913 | .sysc = &omap3xxx_gpio_sysc, | |
914 | .rev = 1, | |
4fe20e97 RN |
915 | }; |
916 | ||
844a3b63 PW |
917 | /* gpio_dev_attr */ |
918 | static struct omap_gpio_dev_attr gpio_dev_attr = { | |
919 | .bank_width = 32, | |
920 | .dbck_flag = true, | |
921 | }; | |
922 | ||
923 | /* gpio1 */ | |
924 | static struct omap_hwmod_opt_clk gpio1_opt_clks[] = { | |
925 | { .role = "dbclk", .clk = "gpio1_dbck", }, | |
926 | }; | |
927 | ||
928 | static struct omap_hwmod omap3xxx_gpio1_hwmod = { | |
929 | .name = "gpio1", | |
930 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | |
931 | .mpu_irqs = omap2_gpio1_irqs, | |
932 | .main_clk = "gpio1_ick", | |
933 | .opt_clks = gpio1_opt_clks, | |
934 | .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks), | |
4fe20e97 RN |
935 | .prcm = { |
936 | .omap2 = { | |
4fe20e97 | 937 | .prcm_reg_id = 1, |
844a3b63 PW |
938 | .module_bit = OMAP3430_EN_GPIO1_SHIFT, |
939 | .module_offs = WKUP_MOD, | |
4fe20e97 | 940 | .idlest_reg_id = 1, |
844a3b63 | 941 | .idlest_idle_bit = OMAP3430_ST_GPIO1_SHIFT, |
4fe20e97 RN |
942 | }, |
943 | }, | |
844a3b63 PW |
944 | .class = &omap3xxx_gpio_hwmod_class, |
945 | .dev_attr = &gpio_dev_attr, | |
4fe20e97 RN |
946 | }; |
947 | ||
844a3b63 PW |
948 | /* gpio2 */ |
949 | static struct omap_hwmod_opt_clk gpio2_opt_clks[] = { | |
950 | { .role = "dbclk", .clk = "gpio2_dbck", }, | |
4fe20e97 RN |
951 | }; |
952 | ||
844a3b63 PW |
953 | static struct omap_hwmod omap3xxx_gpio2_hwmod = { |
954 | .name = "gpio2", | |
955 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | |
956 | .mpu_irqs = omap2_gpio2_irqs, | |
957 | .main_clk = "gpio2_ick", | |
958 | .opt_clks = gpio2_opt_clks, | |
959 | .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks), | |
4fe20e97 RN |
960 | .prcm = { |
961 | .omap2 = { | |
4fe20e97 | 962 | .prcm_reg_id = 1, |
844a3b63 | 963 | .module_bit = OMAP3430_EN_GPIO2_SHIFT, |
ce722d26 | 964 | .module_offs = OMAP3430_PER_MOD, |
4fe20e97 | 965 | .idlest_reg_id = 1, |
844a3b63 | 966 | .idlest_idle_bit = OMAP3430_ST_GPIO2_SHIFT, |
4fe20e97 RN |
967 | }, |
968 | }, | |
844a3b63 PW |
969 | .class = &omap3xxx_gpio_hwmod_class, |
970 | .dev_attr = &gpio_dev_attr, | |
4fe20e97 RN |
971 | }; |
972 | ||
844a3b63 PW |
973 | /* gpio3 */ |
974 | static struct omap_hwmod_opt_clk gpio3_opt_clks[] = { | |
975 | { .role = "dbclk", .clk = "gpio3_dbck", }, | |
4fe20e97 RN |
976 | }; |
977 | ||
844a3b63 PW |
978 | static struct omap_hwmod omap3xxx_gpio3_hwmod = { |
979 | .name = "gpio3", | |
980 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | |
981 | .mpu_irqs = omap2_gpio3_irqs, | |
982 | .main_clk = "gpio3_ick", | |
983 | .opt_clks = gpio3_opt_clks, | |
984 | .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks), | |
4fe20e97 RN |
985 | .prcm = { |
986 | .omap2 = { | |
4fe20e97 | 987 | .prcm_reg_id = 1, |
844a3b63 | 988 | .module_bit = OMAP3430_EN_GPIO3_SHIFT, |
ce722d26 | 989 | .module_offs = OMAP3430_PER_MOD, |
4fe20e97 | 990 | .idlest_reg_id = 1, |
844a3b63 | 991 | .idlest_idle_bit = OMAP3430_ST_GPIO3_SHIFT, |
4fe20e97 RN |
992 | }, |
993 | }, | |
844a3b63 PW |
994 | .class = &omap3xxx_gpio_hwmod_class, |
995 | .dev_attr = &gpio_dev_attr, | |
70034d38 VC |
996 | }; |
997 | ||
844a3b63 PW |
998 | /* gpio4 */ |
999 | static struct omap_hwmod_opt_clk gpio4_opt_clks[] = { | |
1000 | { .role = "dbclk", .clk = "gpio4_dbck", }, | |
70034d38 VC |
1001 | }; |
1002 | ||
844a3b63 PW |
1003 | static struct omap_hwmod omap3xxx_gpio4_hwmod = { |
1004 | .name = "gpio4", | |
1005 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | |
1006 | .mpu_irqs = omap2_gpio4_irqs, | |
1007 | .main_clk = "gpio4_ick", | |
1008 | .opt_clks = gpio4_opt_clks, | |
1009 | .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks), | |
ce722d26 TG |
1010 | .prcm = { |
1011 | .omap2 = { | |
1012 | .prcm_reg_id = 1, | |
844a3b63 | 1013 | .module_bit = OMAP3430_EN_GPIO4_SHIFT, |
ce722d26 TG |
1014 | .module_offs = OMAP3430_PER_MOD, |
1015 | .idlest_reg_id = 1, | |
844a3b63 | 1016 | .idlest_idle_bit = OMAP3430_ST_GPIO4_SHIFT, |
ce722d26 | 1017 | }, |
70034d38 | 1018 | }, |
844a3b63 PW |
1019 | .class = &omap3xxx_gpio_hwmod_class, |
1020 | .dev_attr = &gpio_dev_attr, | |
70034d38 VC |
1021 | }; |
1022 | ||
844a3b63 PW |
1023 | /* gpio5 */ |
1024 | static struct omap_hwmod_irq_info omap3xxx_gpio5_irqs[] = { | |
7d7e1eba TL |
1025 | { .irq = 33 + OMAP_INTC_START, }, /* INT_34XX_GPIO_BANK5 */ |
1026 | { .irq = -1 }, | |
844a3b63 | 1027 | }; |
70034d38 | 1028 | |
844a3b63 PW |
1029 | static struct omap_hwmod_opt_clk gpio5_opt_clks[] = { |
1030 | { .role = "dbclk", .clk = "gpio5_dbck", }, | |
70034d38 VC |
1031 | }; |
1032 | ||
844a3b63 PW |
1033 | static struct omap_hwmod omap3xxx_gpio5_hwmod = { |
1034 | .name = "gpio5", | |
1035 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | |
1036 | .mpu_irqs = omap3xxx_gpio5_irqs, | |
1037 | .main_clk = "gpio5_ick", | |
1038 | .opt_clks = gpio5_opt_clks, | |
1039 | .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks), | |
ce722d26 TG |
1040 | .prcm = { |
1041 | .omap2 = { | |
1042 | .prcm_reg_id = 1, | |
844a3b63 PW |
1043 | .module_bit = OMAP3430_EN_GPIO5_SHIFT, |
1044 | .module_offs = OMAP3430_PER_MOD, | |
ce722d26 | 1045 | .idlest_reg_id = 1, |
844a3b63 | 1046 | .idlest_idle_bit = OMAP3430_ST_GPIO5_SHIFT, |
ce722d26 | 1047 | }, |
70034d38 | 1048 | }, |
844a3b63 PW |
1049 | .class = &omap3xxx_gpio_hwmod_class, |
1050 | .dev_attr = &gpio_dev_attr, | |
70034d38 VC |
1051 | }; |
1052 | ||
844a3b63 PW |
1053 | /* gpio6 */ |
1054 | static struct omap_hwmod_irq_info omap3xxx_gpio6_irqs[] = { | |
7d7e1eba TL |
1055 | { .irq = 34 + OMAP_INTC_START, }, /* INT_34XX_GPIO_BANK6 */ |
1056 | { .irq = -1 }, | |
844a3b63 | 1057 | }; |
70034d38 | 1058 | |
844a3b63 PW |
1059 | static struct omap_hwmod_opt_clk gpio6_opt_clks[] = { |
1060 | { .role = "dbclk", .clk = "gpio6_dbck", }, | |
70034d38 VC |
1061 | }; |
1062 | ||
844a3b63 PW |
1063 | static struct omap_hwmod omap3xxx_gpio6_hwmod = { |
1064 | .name = "gpio6", | |
1065 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | |
1066 | .mpu_irqs = omap3xxx_gpio6_irqs, | |
1067 | .main_clk = "gpio6_ick", | |
1068 | .opt_clks = gpio6_opt_clks, | |
1069 | .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks), | |
ce722d26 TG |
1070 | .prcm = { |
1071 | .omap2 = { | |
1072 | .prcm_reg_id = 1, | |
844a3b63 PW |
1073 | .module_bit = OMAP3430_EN_GPIO6_SHIFT, |
1074 | .module_offs = OMAP3430_PER_MOD, | |
ce722d26 | 1075 | .idlest_reg_id = 1, |
844a3b63 | 1076 | .idlest_idle_bit = OMAP3430_ST_GPIO6_SHIFT, |
ce722d26 TG |
1077 | }, |
1078 | }, | |
844a3b63 PW |
1079 | .class = &omap3xxx_gpio_hwmod_class, |
1080 | .dev_attr = &gpio_dev_attr, | |
ce722d26 TG |
1081 | }; |
1082 | ||
844a3b63 PW |
1083 | /* dma attributes */ |
1084 | static struct omap_dma_dev_attr dma_dev_attr = { | |
1085 | .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY | | |
1086 | IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY, | |
1087 | .lch_count = 32, | |
ce722d26 TG |
1088 | }; |
1089 | ||
844a3b63 PW |
1090 | static struct omap_hwmod_class_sysconfig omap3xxx_dma_sysc = { |
1091 | .rev_offs = 0x0000, | |
1092 | .sysc_offs = 0x002c, | |
1093 | .syss_offs = 0x0028, | |
1094 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | | |
1095 | SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY | | |
1096 | SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE | | |
1097 | SYSS_HAS_RESET_STATUS), | |
1098 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
1099 | MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), | |
1100 | .sysc_fields = &omap_hwmod_sysc_type1, | |
70034d38 VC |
1101 | }; |
1102 | ||
844a3b63 PW |
1103 | static struct omap_hwmod_class omap3xxx_dma_hwmod_class = { |
1104 | .name = "dma", | |
1105 | .sysc = &omap3xxx_dma_sysc, | |
70034d38 VC |
1106 | }; |
1107 | ||
844a3b63 PW |
1108 | /* dma_system */ |
1109 | static struct omap_hwmod omap3xxx_dma_system_hwmod = { | |
1110 | .name = "dma", | |
1111 | .class = &omap3xxx_dma_hwmod_class, | |
1112 | .mpu_irqs = omap2_dma_system_irqs, | |
1113 | .main_clk = "core_l3_ick", | |
1114 | .prcm = { | |
ce722d26 | 1115 | .omap2 = { |
844a3b63 PW |
1116 | .module_offs = CORE_MOD, |
1117 | .prcm_reg_id = 1, | |
1118 | .module_bit = OMAP3430_ST_SDMA_SHIFT, | |
1119 | .idlest_reg_id = 1, | |
1120 | .idlest_idle_bit = OMAP3430_ST_SDMA_SHIFT, | |
ce722d26 TG |
1121 | }, |
1122 | }, | |
844a3b63 PW |
1123 | .dev_attr = &dma_dev_attr, |
1124 | .flags = HWMOD_NO_IDLEST, | |
70034d38 VC |
1125 | }; |
1126 | ||
844a3b63 PW |
1127 | /* |
1128 | * 'mcbsp' class | |
1129 | * multi channel buffered serial port controller | |
1130 | */ | |
1131 | ||
1132 | static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sysc = { | |
1133 | .sysc_offs = 0x008c, | |
1134 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP | | |
1135 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), | |
1136 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
1137 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1138 | .clockact = 0x2, | |
70034d38 VC |
1139 | }; |
1140 | ||
844a3b63 PW |
1141 | static struct omap_hwmod_class omap3xxx_mcbsp_hwmod_class = { |
1142 | .name = "mcbsp", | |
1143 | .sysc = &omap3xxx_mcbsp_sysc, | |
1144 | .rev = MCBSP_CONFIG_TYPE3, | |
70034d38 VC |
1145 | }; |
1146 | ||
7039154b PU |
1147 | /* McBSP functional clock mapping */ |
1148 | static struct omap_hwmod_opt_clk mcbsp15_opt_clks[] = { | |
1149 | { .role = "pad_fck", .clk = "mcbsp_clks" }, | |
1150 | { .role = "prcm_fck", .clk = "core_96m_fck" }, | |
1151 | }; | |
1152 | ||
1153 | static struct omap_hwmod_opt_clk mcbsp234_opt_clks[] = { | |
1154 | { .role = "pad_fck", .clk = "mcbsp_clks" }, | |
1155 | { .role = "prcm_fck", .clk = "per_96m_fck" }, | |
1156 | }; | |
1157 | ||
844a3b63 PW |
1158 | /* mcbsp1 */ |
1159 | static struct omap_hwmod_irq_info omap3xxx_mcbsp1_irqs[] = { | |
7d7e1eba TL |
1160 | { .name = "common", .irq = 16 + OMAP_INTC_START, }, |
1161 | { .name = "tx", .irq = 59 + OMAP_INTC_START, }, | |
1162 | { .name = "rx", .irq = 60 + OMAP_INTC_START, }, | |
1163 | { .irq = -1 }, | |
844a3b63 | 1164 | }; |
6b667f88 | 1165 | |
844a3b63 PW |
1166 | static struct omap_hwmod omap3xxx_mcbsp1_hwmod = { |
1167 | .name = "mcbsp1", | |
1168 | .class = &omap3xxx_mcbsp_hwmod_class, | |
1169 | .mpu_irqs = omap3xxx_mcbsp1_irqs, | |
1170 | .sdma_reqs = omap2_mcbsp1_sdma_reqs, | |
1171 | .main_clk = "mcbsp1_fck", | |
1172 | .prcm = { | |
1173 | .omap2 = { | |
1174 | .prcm_reg_id = 1, | |
1175 | .module_bit = OMAP3430_EN_MCBSP1_SHIFT, | |
1176 | .module_offs = CORE_MOD, | |
1177 | .idlest_reg_id = 1, | |
1178 | .idlest_idle_bit = OMAP3430_ST_MCBSP1_SHIFT, | |
1179 | }, | |
1180 | }, | |
7039154b PU |
1181 | .opt_clks = mcbsp15_opt_clks, |
1182 | .opt_clks_cnt = ARRAY_SIZE(mcbsp15_opt_clks), | |
70034d38 VC |
1183 | }; |
1184 | ||
844a3b63 PW |
1185 | /* mcbsp2 */ |
1186 | static struct omap_hwmod_irq_info omap3xxx_mcbsp2_irqs[] = { | |
7d7e1eba TL |
1187 | { .name = "common", .irq = 17 + OMAP_INTC_START, }, |
1188 | { .name = "tx", .irq = 62 + OMAP_INTC_START, }, | |
1189 | { .name = "rx", .irq = 63 + OMAP_INTC_START, }, | |
1190 | { .irq = -1 }, | |
70034d38 VC |
1191 | }; |
1192 | ||
844a3b63 PW |
1193 | static struct omap_mcbsp_dev_attr omap34xx_mcbsp2_dev_attr = { |
1194 | .sidetone = "mcbsp2_sidetone", | |
70034d38 VC |
1195 | }; |
1196 | ||
844a3b63 PW |
1197 | static struct omap_hwmod omap3xxx_mcbsp2_hwmod = { |
1198 | .name = "mcbsp2", | |
1199 | .class = &omap3xxx_mcbsp_hwmod_class, | |
1200 | .mpu_irqs = omap3xxx_mcbsp2_irqs, | |
1201 | .sdma_reqs = omap2_mcbsp2_sdma_reqs, | |
1202 | .main_clk = "mcbsp2_fck", | |
70034d38 VC |
1203 | .prcm = { |
1204 | .omap2 = { | |
1205 | .prcm_reg_id = 1, | |
844a3b63 PW |
1206 | .module_bit = OMAP3430_EN_MCBSP2_SHIFT, |
1207 | .module_offs = OMAP3430_PER_MOD, | |
70034d38 | 1208 | .idlest_reg_id = 1, |
844a3b63 | 1209 | .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT, |
70034d38 VC |
1210 | }, |
1211 | }, | |
7039154b PU |
1212 | .opt_clks = mcbsp234_opt_clks, |
1213 | .opt_clks_cnt = ARRAY_SIZE(mcbsp234_opt_clks), | |
844a3b63 | 1214 | .dev_attr = &omap34xx_mcbsp2_dev_attr, |
70034d38 VC |
1215 | }; |
1216 | ||
844a3b63 PW |
1217 | /* mcbsp3 */ |
1218 | static struct omap_hwmod_irq_info omap3xxx_mcbsp3_irqs[] = { | |
7d7e1eba TL |
1219 | { .name = "common", .irq = 22 + OMAP_INTC_START, }, |
1220 | { .name = "tx", .irq = 89 + OMAP_INTC_START, }, | |
1221 | { .name = "rx", .irq = 90 + OMAP_INTC_START, }, | |
1222 | { .irq = -1 }, | |
844a3b63 PW |
1223 | }; |
1224 | ||
1225 | static struct omap_mcbsp_dev_attr omap34xx_mcbsp3_dev_attr = { | |
1226 | .sidetone = "mcbsp3_sidetone", | |
1227 | }; | |
1228 | ||
1229 | static struct omap_hwmod omap3xxx_mcbsp3_hwmod = { | |
1230 | .name = "mcbsp3", | |
1231 | .class = &omap3xxx_mcbsp_hwmod_class, | |
1232 | .mpu_irqs = omap3xxx_mcbsp3_irqs, | |
1233 | .sdma_reqs = omap2_mcbsp3_sdma_reqs, | |
1234 | .main_clk = "mcbsp3_fck", | |
70034d38 VC |
1235 | .prcm = { |
1236 | .omap2 = { | |
1237 | .prcm_reg_id = 1, | |
844a3b63 PW |
1238 | .module_bit = OMAP3430_EN_MCBSP3_SHIFT, |
1239 | .module_offs = OMAP3430_PER_MOD, | |
70034d38 | 1240 | .idlest_reg_id = 1, |
844a3b63 | 1241 | .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT, |
70034d38 VC |
1242 | }, |
1243 | }, | |
7039154b PU |
1244 | .opt_clks = mcbsp234_opt_clks, |
1245 | .opt_clks_cnt = ARRAY_SIZE(mcbsp234_opt_clks), | |
844a3b63 | 1246 | .dev_attr = &omap34xx_mcbsp3_dev_attr, |
70034d38 VC |
1247 | }; |
1248 | ||
844a3b63 PW |
1249 | /* mcbsp4 */ |
1250 | static struct omap_hwmod_irq_info omap3xxx_mcbsp4_irqs[] = { | |
7d7e1eba TL |
1251 | { .name = "common", .irq = 23 + OMAP_INTC_START, }, |
1252 | { .name = "tx", .irq = 54 + OMAP_INTC_START, }, | |
1253 | { .name = "rx", .irq = 55 + OMAP_INTC_START, }, | |
1254 | { .irq = -1 }, | |
844a3b63 PW |
1255 | }; |
1256 | ||
1257 | static struct omap_hwmod_dma_info omap3xxx_mcbsp4_sdma_chs[] = { | |
1258 | { .name = "rx", .dma_req = 20 }, | |
1259 | { .name = "tx", .dma_req = 19 }, | |
1260 | { .dma_req = -1 } | |
1261 | }; | |
1262 | ||
1263 | static struct omap_hwmod omap3xxx_mcbsp4_hwmod = { | |
1264 | .name = "mcbsp4", | |
1265 | .class = &omap3xxx_mcbsp_hwmod_class, | |
1266 | .mpu_irqs = omap3xxx_mcbsp4_irqs, | |
1267 | .sdma_reqs = omap3xxx_mcbsp4_sdma_chs, | |
1268 | .main_clk = "mcbsp4_fck", | |
70034d38 VC |
1269 | .prcm = { |
1270 | .omap2 = { | |
1271 | .prcm_reg_id = 1, | |
844a3b63 PW |
1272 | .module_bit = OMAP3430_EN_MCBSP4_SHIFT, |
1273 | .module_offs = OMAP3430_PER_MOD, | |
046465b7 | 1274 | .idlest_reg_id = 1, |
844a3b63 | 1275 | .idlest_idle_bit = OMAP3430_ST_MCBSP4_SHIFT, |
046465b7 KH |
1276 | }, |
1277 | }, | |
7039154b PU |
1278 | .opt_clks = mcbsp234_opt_clks, |
1279 | .opt_clks_cnt = ARRAY_SIZE(mcbsp234_opt_clks), | |
046465b7 KH |
1280 | }; |
1281 | ||
844a3b63 PW |
1282 | /* mcbsp5 */ |
1283 | static struct omap_hwmod_irq_info omap3xxx_mcbsp5_irqs[] = { | |
7d7e1eba TL |
1284 | { .name = "common", .irq = 27 + OMAP_INTC_START, }, |
1285 | { .name = "tx", .irq = 81 + OMAP_INTC_START, }, | |
1286 | { .name = "rx", .irq = 82 + OMAP_INTC_START, }, | |
1287 | { .irq = -1 }, | |
844a3b63 PW |
1288 | }; |
1289 | ||
1290 | static struct omap_hwmod_dma_info omap3xxx_mcbsp5_sdma_chs[] = { | |
1291 | { .name = "rx", .dma_req = 22 }, | |
1292 | { .name = "tx", .dma_req = 21 }, | |
1293 | { .dma_req = -1 } | |
1294 | }; | |
1295 | ||
1296 | static struct omap_hwmod omap3xxx_mcbsp5_hwmod = { | |
1297 | .name = "mcbsp5", | |
1298 | .class = &omap3xxx_mcbsp_hwmod_class, | |
1299 | .mpu_irqs = omap3xxx_mcbsp5_irqs, | |
1300 | .sdma_reqs = omap3xxx_mcbsp5_sdma_chs, | |
1301 | .main_clk = "mcbsp5_fck", | |
046465b7 KH |
1302 | .prcm = { |
1303 | .omap2 = { | |
046465b7 | 1304 | .prcm_reg_id = 1, |
844a3b63 PW |
1305 | .module_bit = OMAP3430_EN_MCBSP5_SHIFT, |
1306 | .module_offs = CORE_MOD, | |
70034d38 | 1307 | .idlest_reg_id = 1, |
844a3b63 | 1308 | .idlest_idle_bit = OMAP3430_ST_MCBSP5_SHIFT, |
70034d38 VC |
1309 | }, |
1310 | }, | |
7039154b PU |
1311 | .opt_clks = mcbsp15_opt_clks, |
1312 | .opt_clks_cnt = ARRAY_SIZE(mcbsp15_opt_clks), | |
70034d38 VC |
1313 | }; |
1314 | ||
844a3b63 PW |
1315 | /* 'mcbsp sidetone' class */ |
1316 | static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sidetone_sysc = { | |
1317 | .sysc_offs = 0x0010, | |
1318 | .sysc_flags = SYSC_HAS_AUTOIDLE, | |
1319 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1320 | }; | |
046465b7 | 1321 | |
844a3b63 PW |
1322 | static struct omap_hwmod_class omap3xxx_mcbsp_sidetone_hwmod_class = { |
1323 | .name = "mcbsp_sidetone", | |
1324 | .sysc = &omap3xxx_mcbsp_sidetone_sysc, | |
70034d38 VC |
1325 | }; |
1326 | ||
844a3b63 PW |
1327 | /* mcbsp2_sidetone */ |
1328 | static struct omap_hwmod_irq_info omap3xxx_mcbsp2_sidetone_irqs[] = { | |
7d7e1eba TL |
1329 | { .name = "irq", .irq = 4 + OMAP_INTC_START, }, |
1330 | { .irq = -1 }, | |
70034d38 VC |
1331 | }; |
1332 | ||
844a3b63 PW |
1333 | static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = { |
1334 | .name = "mcbsp2_sidetone", | |
1335 | .class = &omap3xxx_mcbsp_sidetone_hwmod_class, | |
1336 | .mpu_irqs = omap3xxx_mcbsp2_sidetone_irqs, | |
3b80c9be PU |
1337 | .main_clk = "mcbsp2_ick", |
1338 | .flags = HWMOD_NO_IDLEST, | |
4bf90f65 KM |
1339 | }; |
1340 | ||
844a3b63 PW |
1341 | /* mcbsp3_sidetone */ |
1342 | static struct omap_hwmod_irq_info omap3xxx_mcbsp3_sidetone_irqs[] = { | |
7d7e1eba TL |
1343 | { .name = "irq", .irq = 5 + OMAP_INTC_START, }, |
1344 | { .irq = -1 }, | |
4bf90f65 KM |
1345 | }; |
1346 | ||
844a3b63 PW |
1347 | static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = { |
1348 | .name = "mcbsp3_sidetone", | |
1349 | .class = &omap3xxx_mcbsp_sidetone_hwmod_class, | |
1350 | .mpu_irqs = omap3xxx_mcbsp3_sidetone_irqs, | |
3b80c9be PU |
1351 | .main_clk = "mcbsp3_ick", |
1352 | .flags = HWMOD_NO_IDLEST, | |
4bf90f65 KM |
1353 | }; |
1354 | ||
844a3b63 PW |
1355 | /* SR common */ |
1356 | static struct omap_hwmod_sysc_fields omap34xx_sr_sysc_fields = { | |
1357 | .clkact_shift = 20, | |
1358 | }; | |
4bf90f65 | 1359 | |
844a3b63 PW |
1360 | static struct omap_hwmod_class_sysconfig omap34xx_sr_sysc = { |
1361 | .sysc_offs = 0x24, | |
1362 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_NO_CACHE), | |
1363 | .clockact = CLOCKACT_TEST_ICLK, | |
1364 | .sysc_fields = &omap34xx_sr_sysc_fields, | |
4fe20e97 RN |
1365 | }; |
1366 | ||
844a3b63 PW |
1367 | static struct omap_hwmod_class omap34xx_smartreflex_hwmod_class = { |
1368 | .name = "smartreflex", | |
1369 | .sysc = &omap34xx_sr_sysc, | |
1370 | .rev = 1, | |
e04d9e1e SG |
1371 | }; |
1372 | ||
844a3b63 PW |
1373 | static struct omap_hwmod_sysc_fields omap36xx_sr_sysc_fields = { |
1374 | .sidle_shift = 24, | |
1375 | .enwkup_shift = 26, | |
1376 | }; | |
e04d9e1e | 1377 | |
844a3b63 PW |
1378 | static struct omap_hwmod_class_sysconfig omap36xx_sr_sysc = { |
1379 | .sysc_offs = 0x38, | |
1380 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
1381 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP | | |
1382 | SYSC_NO_CACHE), | |
1383 | .sysc_fields = &omap36xx_sr_sysc_fields, | |
1384 | }; | |
1385 | ||
1386 | static struct omap_hwmod_class omap36xx_smartreflex_hwmod_class = { | |
1387 | .name = "smartreflex", | |
1388 | .sysc = &omap36xx_sr_sysc, | |
1389 | .rev = 2, | |
1390 | }; | |
1391 | ||
1392 | /* SR1 */ | |
1393 | static struct omap_smartreflex_dev_attr sr1_dev_attr = { | |
1394 | .sensor_voltdm_name = "mpu_iva", | |
1395 | }; | |
1396 | ||
1397 | static struct omap_hwmod_irq_info omap3_smartreflex_mpu_irqs[] = { | |
7d7e1eba TL |
1398 | { .irq = 18 + OMAP_INTC_START, }, |
1399 | { .irq = -1 }, | |
844a3b63 PW |
1400 | }; |
1401 | ||
1402 | static struct omap_hwmod omap34xx_sr1_hwmod = { | |
1fcd3069 | 1403 | .name = "smartreflex_mpu_iva", |
844a3b63 PW |
1404 | .class = &omap34xx_smartreflex_hwmod_class, |
1405 | .main_clk = "sr1_fck", | |
1406 | .prcm = { | |
e04d9e1e | 1407 | .omap2 = { |
844a3b63 PW |
1408 | .prcm_reg_id = 1, |
1409 | .module_bit = OMAP3430_EN_SR1_SHIFT, | |
1410 | .module_offs = WKUP_MOD, | |
1411 | .idlest_reg_id = 1, | |
1412 | .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT, | |
1413 | }, | |
e04d9e1e | 1414 | }, |
844a3b63 PW |
1415 | .dev_attr = &sr1_dev_attr, |
1416 | .mpu_irqs = omap3_smartreflex_mpu_irqs, | |
1417 | .flags = HWMOD_SET_DEFAULT_CLOCKACT, | |
e04d9e1e SG |
1418 | }; |
1419 | ||
844a3b63 | 1420 | static struct omap_hwmod omap36xx_sr1_hwmod = { |
1fcd3069 | 1421 | .name = "smartreflex_mpu_iva", |
844a3b63 PW |
1422 | .class = &omap36xx_smartreflex_hwmod_class, |
1423 | .main_clk = "sr1_fck", | |
1424 | .prcm = { | |
e04d9e1e | 1425 | .omap2 = { |
844a3b63 PW |
1426 | .prcm_reg_id = 1, |
1427 | .module_bit = OMAP3430_EN_SR1_SHIFT, | |
1428 | .module_offs = WKUP_MOD, | |
1429 | .idlest_reg_id = 1, | |
1430 | .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT, | |
1431 | }, | |
e04d9e1e | 1432 | }, |
844a3b63 PW |
1433 | .dev_attr = &sr1_dev_attr, |
1434 | .mpu_irqs = omap3_smartreflex_mpu_irqs, | |
e04d9e1e SG |
1435 | }; |
1436 | ||
844a3b63 PW |
1437 | /* SR2 */ |
1438 | static struct omap_smartreflex_dev_attr sr2_dev_attr = { | |
1439 | .sensor_voltdm_name = "core", | |
e04d9e1e SG |
1440 | }; |
1441 | ||
844a3b63 | 1442 | static struct omap_hwmod_irq_info omap3_smartreflex_core_irqs[] = { |
7d7e1eba TL |
1443 | { .irq = 19 + OMAP_INTC_START, }, |
1444 | { .irq = -1 }, | |
844a3b63 PW |
1445 | }; |
1446 | ||
1447 | static struct omap_hwmod omap34xx_sr2_hwmod = { | |
1fcd3069 | 1448 | .name = "smartreflex_core", |
844a3b63 PW |
1449 | .class = &omap34xx_smartreflex_hwmod_class, |
1450 | .main_clk = "sr2_fck", | |
e04d9e1e SG |
1451 | .prcm = { |
1452 | .omap2 = { | |
1453 | .prcm_reg_id = 1, | |
844a3b63 PW |
1454 | .module_bit = OMAP3430_EN_SR2_SHIFT, |
1455 | .module_offs = WKUP_MOD, | |
e04d9e1e | 1456 | .idlest_reg_id = 1, |
844a3b63 | 1457 | .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT, |
e04d9e1e SG |
1458 | }, |
1459 | }, | |
844a3b63 PW |
1460 | .dev_attr = &sr2_dev_attr, |
1461 | .mpu_irqs = omap3_smartreflex_core_irqs, | |
1462 | .flags = HWMOD_SET_DEFAULT_CLOCKACT, | |
e04d9e1e SG |
1463 | }; |
1464 | ||
844a3b63 | 1465 | static struct omap_hwmod omap36xx_sr2_hwmod = { |
1fcd3069 | 1466 | .name = "smartreflex_core", |
844a3b63 PW |
1467 | .class = &omap36xx_smartreflex_hwmod_class, |
1468 | .main_clk = "sr2_fck", | |
e04d9e1e SG |
1469 | .prcm = { |
1470 | .omap2 = { | |
1471 | .prcm_reg_id = 1, | |
844a3b63 PW |
1472 | .module_bit = OMAP3430_EN_SR2_SHIFT, |
1473 | .module_offs = WKUP_MOD, | |
e04d9e1e | 1474 | .idlest_reg_id = 1, |
844a3b63 | 1475 | .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT, |
e04d9e1e SG |
1476 | }, |
1477 | }, | |
844a3b63 PW |
1478 | .dev_attr = &sr2_dev_attr, |
1479 | .mpu_irqs = omap3_smartreflex_core_irqs, | |
e04d9e1e SG |
1480 | }; |
1481 | ||
1ac6d46e | 1482 | /* |
844a3b63 PW |
1483 | * 'mailbox' class |
1484 | * mailbox module allowing communication between the on-chip processors | |
1485 | * using a queued mailbox-interrupt mechanism. | |
1ac6d46e TV |
1486 | */ |
1487 | ||
844a3b63 PW |
1488 | static struct omap_hwmod_class_sysconfig omap3xxx_mailbox_sysc = { |
1489 | .rev_offs = 0x000, | |
1490 | .sysc_offs = 0x010, | |
1491 | .syss_offs = 0x014, | |
1492 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | | |
1493 | SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), | |
1494 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
1ac6d46e TV |
1495 | .sysc_fields = &omap_hwmod_sysc_type1, |
1496 | }; | |
1497 | ||
844a3b63 PW |
1498 | static struct omap_hwmod_class omap3xxx_mailbox_hwmod_class = { |
1499 | .name = "mailbox", | |
1500 | .sysc = &omap3xxx_mailbox_sysc, | |
1ac6d46e TV |
1501 | }; |
1502 | ||
844a3b63 PW |
1503 | static struct omap_hwmod omap3xxx_mailbox_hwmod = { |
1504 | .name = "mailbox", | |
1505 | .class = &omap3xxx_mailbox_hwmod_class, | |
844a3b63 | 1506 | .main_clk = "mailboxes_ick", |
e04d9e1e SG |
1507 | .prcm = { |
1508 | .omap2 = { | |
1509 | .prcm_reg_id = 1, | |
844a3b63 PW |
1510 | .module_bit = OMAP3430_EN_MAILBOXES_SHIFT, |
1511 | .module_offs = CORE_MOD, | |
1512 | .idlest_reg_id = 1, | |
1513 | .idlest_idle_bit = OMAP3430_ST_MAILBOXES_SHIFT, | |
e04d9e1e SG |
1514 | }, |
1515 | }, | |
e04d9e1e SG |
1516 | }; |
1517 | ||
1518 | /* | |
844a3b63 PW |
1519 | * 'mcspi' class |
1520 | * multichannel serial port interface (mcspi) / master/slave synchronous serial | |
1521 | * bus | |
e04d9e1e SG |
1522 | */ |
1523 | ||
844a3b63 PW |
1524 | static struct omap_hwmod_class_sysconfig omap34xx_mcspi_sysc = { |
1525 | .rev_offs = 0x0000, | |
1526 | .sysc_offs = 0x0010, | |
1527 | .syss_offs = 0x0014, | |
1528 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | | |
1529 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | | |
1530 | SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), | |
1531 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
1532 | .sysc_fields = &omap_hwmod_sysc_type1, | |
e04d9e1e SG |
1533 | }; |
1534 | ||
844a3b63 PW |
1535 | static struct omap_hwmod_class omap34xx_mcspi_class = { |
1536 | .name = "mcspi", | |
1537 | .sysc = &omap34xx_mcspi_sysc, | |
1538 | .rev = OMAP3_MCSPI_REV, | |
affe360d | 1539 | }; |
1540 | ||
844a3b63 PW |
1541 | /* mcspi1 */ |
1542 | static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = { | |
1543 | .num_chipselect = 4, | |
e04d9e1e SG |
1544 | }; |
1545 | ||
844a3b63 PW |
1546 | static struct omap_hwmod omap34xx_mcspi1 = { |
1547 | .name = "mcspi1", | |
1548 | .mpu_irqs = omap2_mcspi1_mpu_irqs, | |
1549 | .sdma_reqs = omap2_mcspi1_sdma_reqs, | |
1550 | .main_clk = "mcspi1_fck", | |
1551 | .prcm = { | |
e04d9e1e | 1552 | .omap2 = { |
844a3b63 PW |
1553 | .module_offs = CORE_MOD, |
1554 | .prcm_reg_id = 1, | |
1555 | .module_bit = OMAP3430_EN_MCSPI1_SHIFT, | |
1556 | .idlest_reg_id = 1, | |
1557 | .idlest_idle_bit = OMAP3430_ST_MCSPI1_SHIFT, | |
1558 | }, | |
e04d9e1e | 1559 | }, |
844a3b63 PW |
1560 | .class = &omap34xx_mcspi_class, |
1561 | .dev_attr = &omap_mcspi1_dev_attr, | |
e04d9e1e SG |
1562 | }; |
1563 | ||
844a3b63 PW |
1564 | /* mcspi2 */ |
1565 | static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = { | |
1566 | .num_chipselect = 2, | |
6c3d7e34 TV |
1567 | }; |
1568 | ||
844a3b63 PW |
1569 | static struct omap_hwmod omap34xx_mcspi2 = { |
1570 | .name = "mcspi2", | |
1571 | .mpu_irqs = omap2_mcspi2_mpu_irqs, | |
1572 | .sdma_reqs = omap2_mcspi2_sdma_reqs, | |
1573 | .main_clk = "mcspi2_fck", | |
e04d9e1e SG |
1574 | .prcm = { |
1575 | .omap2 = { | |
844a3b63 | 1576 | .module_offs = CORE_MOD, |
e04d9e1e | 1577 | .prcm_reg_id = 1, |
844a3b63 PW |
1578 | .module_bit = OMAP3430_EN_MCSPI2_SHIFT, |
1579 | .idlest_reg_id = 1, | |
1580 | .idlest_idle_bit = OMAP3430_ST_MCSPI2_SHIFT, | |
e04d9e1e SG |
1581 | }, |
1582 | }, | |
844a3b63 PW |
1583 | .class = &omap34xx_mcspi_class, |
1584 | .dev_attr = &omap_mcspi2_dev_attr, | |
e04d9e1e SG |
1585 | }; |
1586 | ||
844a3b63 PW |
1587 | /* mcspi3 */ |
1588 | static struct omap_hwmod_irq_info omap34xx_mcspi3_mpu_irqs[] = { | |
7d7e1eba TL |
1589 | { .name = "irq", .irq = 91 + OMAP_INTC_START, }, /* 91 */ |
1590 | { .irq = -1 }, | |
844a3b63 PW |
1591 | }; |
1592 | ||
1593 | static struct omap_hwmod_dma_info omap34xx_mcspi3_sdma_reqs[] = { | |
1594 | { .name = "tx0", .dma_req = 15 }, | |
1595 | { .name = "rx0", .dma_req = 16 }, | |
1596 | { .name = "tx1", .dma_req = 23 }, | |
1597 | { .name = "rx1", .dma_req = 24 }, | |
1598 | { .dma_req = -1 } | |
e04d9e1e SG |
1599 | }; |
1600 | ||
844a3b63 PW |
1601 | static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = { |
1602 | .num_chipselect = 2, | |
6c3d7e34 TV |
1603 | }; |
1604 | ||
844a3b63 PW |
1605 | static struct omap_hwmod omap34xx_mcspi3 = { |
1606 | .name = "mcspi3", | |
1607 | .mpu_irqs = omap34xx_mcspi3_mpu_irqs, | |
1608 | .sdma_reqs = omap34xx_mcspi3_sdma_reqs, | |
1609 | .main_clk = "mcspi3_fck", | |
e04d9e1e SG |
1610 | .prcm = { |
1611 | .omap2 = { | |
844a3b63 | 1612 | .module_offs = CORE_MOD, |
e04d9e1e | 1613 | .prcm_reg_id = 1, |
844a3b63 PW |
1614 | .module_bit = OMAP3430_EN_MCSPI3_SHIFT, |
1615 | .idlest_reg_id = 1, | |
1616 | .idlest_idle_bit = OMAP3430_ST_MCSPI3_SHIFT, | |
e04d9e1e SG |
1617 | }, |
1618 | }, | |
844a3b63 PW |
1619 | .class = &omap34xx_mcspi_class, |
1620 | .dev_attr = &omap_mcspi3_dev_attr, | |
e04d9e1e SG |
1621 | }; |
1622 | ||
844a3b63 PW |
1623 | /* mcspi4 */ |
1624 | static struct omap_hwmod_irq_info omap34xx_mcspi4_mpu_irqs[] = { | |
7d7e1eba TL |
1625 | { .name = "irq", .irq = 48 + OMAP_INTC_START, }, |
1626 | { .irq = -1 }, | |
e04d9e1e SG |
1627 | }; |
1628 | ||
844a3b63 PW |
1629 | static struct omap_hwmod_dma_info omap34xx_mcspi4_sdma_reqs[] = { |
1630 | { .name = "tx0", .dma_req = 70 }, /* DMA_SPI4_TX0 */ | |
1631 | { .name = "rx0", .dma_req = 71 }, /* DMA_SPI4_RX0 */ | |
1632 | { .dma_req = -1 } | |
6c3d7e34 TV |
1633 | }; |
1634 | ||
844a3b63 PW |
1635 | static struct omap2_mcspi_dev_attr omap_mcspi4_dev_attr = { |
1636 | .num_chipselect = 1, | |
1637 | }; | |
1638 | ||
1639 | static struct omap_hwmod omap34xx_mcspi4 = { | |
1640 | .name = "mcspi4", | |
1641 | .mpu_irqs = omap34xx_mcspi4_mpu_irqs, | |
1642 | .sdma_reqs = omap34xx_mcspi4_sdma_reqs, | |
1643 | .main_clk = "mcspi4_fck", | |
e04d9e1e SG |
1644 | .prcm = { |
1645 | .omap2 = { | |
844a3b63 | 1646 | .module_offs = CORE_MOD, |
e04d9e1e | 1647 | .prcm_reg_id = 1, |
844a3b63 PW |
1648 | .module_bit = OMAP3430_EN_MCSPI4_SHIFT, |
1649 | .idlest_reg_id = 1, | |
1650 | .idlest_idle_bit = OMAP3430_ST_MCSPI4_SHIFT, | |
e04d9e1e SG |
1651 | }, |
1652 | }, | |
844a3b63 PW |
1653 | .class = &omap34xx_mcspi_class, |
1654 | .dev_attr = &omap_mcspi4_dev_attr, | |
e04d9e1e SG |
1655 | }; |
1656 | ||
844a3b63 PW |
1657 | /* usbhsotg */ |
1658 | static struct omap_hwmod_class_sysconfig omap3xxx_usbhsotg_sysc = { | |
1659 | .rev_offs = 0x0400, | |
1660 | .sysc_offs = 0x0404, | |
1661 | .syss_offs = 0x0408, | |
1662 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE| | |
1663 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | | |
1664 | SYSC_HAS_AUTOIDLE), | |
1665 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
1666 | MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), | |
1667 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1668 | }; | |
4fe20e97 | 1669 | |
844a3b63 PW |
1670 | static struct omap_hwmod_class usbotg_class = { |
1671 | .name = "usbotg", | |
1672 | .sysc = &omap3xxx_usbhsotg_sysc, | |
4fe20e97 RN |
1673 | }; |
1674 | ||
844a3b63 PW |
1675 | /* usb_otg_hs */ |
1676 | static struct omap_hwmod_irq_info omap3xxx_usbhsotg_mpu_irqs[] = { | |
1677 | ||
7d7e1eba TL |
1678 | { .name = "mc", .irq = 92 + OMAP_INTC_START, }, |
1679 | { .name = "dma", .irq = 93 + OMAP_INTC_START, }, | |
1680 | { .irq = -1 }, | |
844a3b63 PW |
1681 | }; |
1682 | ||
1683 | static struct omap_hwmod omap3xxx_usbhsotg_hwmod = { | |
1684 | .name = "usb_otg_hs", | |
1685 | .mpu_irqs = omap3xxx_usbhsotg_mpu_irqs, | |
1686 | .main_clk = "hsotgusb_ick", | |
4fe20e97 RN |
1687 | .prcm = { |
1688 | .omap2 = { | |
4fe20e97 | 1689 | .prcm_reg_id = 1, |
844a3b63 PW |
1690 | .module_bit = OMAP3430_EN_HSOTGUSB_SHIFT, |
1691 | .module_offs = CORE_MOD, | |
4fe20e97 | 1692 | .idlest_reg_id = 1, |
844a3b63 PW |
1693 | .idlest_idle_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT, |
1694 | .idlest_stdby_bit = OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT | |
4fe20e97 RN |
1695 | }, |
1696 | }, | |
844a3b63 PW |
1697 | .class = &usbotg_class, |
1698 | ||
1699 | /* | |
1700 | * Erratum ID: i479 idle_req / idle_ack mechanism potentially | |
1701 | * broken when autoidle is enabled | |
1702 | * workaround is to disable the autoidle bit at module level. | |
092bc089 GI |
1703 | * |
1704 | * Enabling the device in any other MIDLEMODE setting but force-idle | |
1705 | * causes core_pwrdm not enter idle states at least on OMAP3630. | |
1706 | * Note that musb has OTG_FORCESTDBY register that controls MSTANDBY | |
1707 | * signal when MIDLEMODE is set to force-idle. | |
844a3b63 | 1708 | */ |
6a08b11a TL |
1709 | .flags = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE | |
1710 | HWMOD_FORCE_MSTANDBY | HWMOD_RECONFIG_IO_CHAIN, | |
4fe20e97 RN |
1711 | }; |
1712 | ||
844a3b63 PW |
1713 | /* usb_otg_hs */ |
1714 | static struct omap_hwmod_irq_info am35xx_usbhsotg_mpu_irqs[] = { | |
7d7e1eba TL |
1715 | { .name = "mc", .irq = 71 + OMAP_INTC_START, }, |
1716 | { .irq = -1 }, | |
4fe20e97 RN |
1717 | }; |
1718 | ||
844a3b63 PW |
1719 | static struct omap_hwmod_class am35xx_usbotg_class = { |
1720 | .name = "am35xx_usbotg", | |
844a3b63 PW |
1721 | }; |
1722 | ||
1723 | static struct omap_hwmod am35xx_usbhsotg_hwmod = { | |
1724 | .name = "am35x_otg_hs", | |
1725 | .mpu_irqs = am35xx_usbhsotg_mpu_irqs, | |
89ea2583 | 1726 | .main_clk = "hsotgusb_fck", |
844a3b63 | 1727 | .class = &am35xx_usbotg_class, |
89ea2583 | 1728 | .flags = HWMOD_NO_IDLEST, |
4fe20e97 RN |
1729 | }; |
1730 | ||
844a3b63 PW |
1731 | /* MMC/SD/SDIO common */ |
1732 | static struct omap_hwmod_class_sysconfig omap34xx_mmc_sysc = { | |
1733 | .rev_offs = 0x1fc, | |
1734 | .sysc_offs = 0x10, | |
1735 | .syss_offs = 0x14, | |
1736 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | | |
1737 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | | |
1738 | SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), | |
1739 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
1740 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1741 | }; | |
4fe20e97 | 1742 | |
844a3b63 PW |
1743 | static struct omap_hwmod_class omap34xx_mmc_class = { |
1744 | .name = "mmc", | |
1745 | .sysc = &omap34xx_mmc_sysc, | |
4fe20e97 RN |
1746 | }; |
1747 | ||
844a3b63 PW |
1748 | /* MMC/SD/SDIO1 */ |
1749 | ||
1750 | static struct omap_hwmod_irq_info omap34xx_mmc1_mpu_irqs[] = { | |
7d7e1eba TL |
1751 | { .irq = 83 + OMAP_INTC_START, }, |
1752 | { .irq = -1 }, | |
4fe20e97 RN |
1753 | }; |
1754 | ||
844a3b63 PW |
1755 | static struct omap_hwmod_dma_info omap34xx_mmc1_sdma_reqs[] = { |
1756 | { .name = "tx", .dma_req = 61, }, | |
1757 | { .name = "rx", .dma_req = 62, }, | |
bc614958 | 1758 | { .dma_req = -1 } |
4fe20e97 RN |
1759 | }; |
1760 | ||
844a3b63 PW |
1761 | static struct omap_hwmod_opt_clk omap34xx_mmc1_opt_clks[] = { |
1762 | { .role = "dbck", .clk = "omap_32k_fck", }, | |
1763 | }; | |
1764 | ||
55143438 | 1765 | static struct omap_hsmmc_dev_attr mmc1_dev_attr = { |
844a3b63 PW |
1766 | .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT, |
1767 | }; | |
1768 | ||
1769 | /* See 35xx errata 2.1.1.128 in SPRZ278F */ | |
55143438 | 1770 | static struct omap_hsmmc_dev_attr mmc1_pre_es3_dev_attr = { |
844a3b63 PW |
1771 | .flags = (OMAP_HSMMC_SUPPORTS_DUAL_VOLT | |
1772 | OMAP_HSMMC_BROKEN_MULTIBLOCK_READ), | |
1773 | }; | |
1774 | ||
1775 | static struct omap_hwmod omap3xxx_pre_es3_mmc1_hwmod = { | |
1776 | .name = "mmc1", | |
1777 | .mpu_irqs = omap34xx_mmc1_mpu_irqs, | |
1778 | .sdma_reqs = omap34xx_mmc1_sdma_reqs, | |
1779 | .opt_clks = omap34xx_mmc1_opt_clks, | |
1780 | .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc1_opt_clks), | |
1781 | .main_clk = "mmchs1_fck", | |
4fe20e97 RN |
1782 | .prcm = { |
1783 | .omap2 = { | |
1784 | .module_offs = CORE_MOD, | |
1785 | .prcm_reg_id = 1, | |
844a3b63 | 1786 | .module_bit = OMAP3430_EN_MMC1_SHIFT, |
4fe20e97 | 1787 | .idlest_reg_id = 1, |
844a3b63 | 1788 | .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT, |
4fe20e97 RN |
1789 | }, |
1790 | }, | |
844a3b63 PW |
1791 | .dev_attr = &mmc1_pre_es3_dev_attr, |
1792 | .class = &omap34xx_mmc_class, | |
4fe20e97 RN |
1793 | }; |
1794 | ||
844a3b63 PW |
1795 | static struct omap_hwmod omap3xxx_es3plus_mmc1_hwmod = { |
1796 | .name = "mmc1", | |
1797 | .mpu_irqs = omap34xx_mmc1_mpu_irqs, | |
1798 | .sdma_reqs = omap34xx_mmc1_sdma_reqs, | |
1799 | .opt_clks = omap34xx_mmc1_opt_clks, | |
1800 | .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc1_opt_clks), | |
1801 | .main_clk = "mmchs1_fck", | |
1802 | .prcm = { | |
1803 | .omap2 = { | |
1804 | .module_offs = CORE_MOD, | |
1805 | .prcm_reg_id = 1, | |
1806 | .module_bit = OMAP3430_EN_MMC1_SHIFT, | |
1807 | .idlest_reg_id = 1, | |
1808 | .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT, | |
1809 | }, | |
70034d38 | 1810 | }, |
844a3b63 PW |
1811 | .dev_attr = &mmc1_dev_attr, |
1812 | .class = &omap34xx_mmc_class, | |
70034d38 VC |
1813 | }; |
1814 | ||
844a3b63 | 1815 | /* MMC/SD/SDIO2 */ |
70034d38 | 1816 | |
844a3b63 | 1817 | static struct omap_hwmod_irq_info omap34xx_mmc2_mpu_irqs[] = { |
7d7e1eba TL |
1818 | { .irq = 86 + OMAP_INTC_START, }, |
1819 | { .irq = -1 }, | |
70034d38 VC |
1820 | }; |
1821 | ||
844a3b63 PW |
1822 | static struct omap_hwmod_dma_info omap34xx_mmc2_sdma_reqs[] = { |
1823 | { .name = "tx", .dma_req = 47, }, | |
1824 | { .name = "rx", .dma_req = 48, }, | |
1825 | { .dma_req = -1 } | |
70034d38 VC |
1826 | }; |
1827 | ||
844a3b63 PW |
1828 | static struct omap_hwmod_opt_clk omap34xx_mmc2_opt_clks[] = { |
1829 | { .role = "dbck", .clk = "omap_32k_fck", }, | |
70034d38 VC |
1830 | }; |
1831 | ||
844a3b63 | 1832 | /* See 35xx errata 2.1.1.128 in SPRZ278F */ |
55143438 | 1833 | static struct omap_hsmmc_dev_attr mmc2_pre_es3_dev_attr = { |
844a3b63 | 1834 | .flags = OMAP_HSMMC_BROKEN_MULTIBLOCK_READ, |
70034d38 VC |
1835 | }; |
1836 | ||
844a3b63 PW |
1837 | static struct omap_hwmod omap3xxx_pre_es3_mmc2_hwmod = { |
1838 | .name = "mmc2", | |
1839 | .mpu_irqs = omap34xx_mmc2_mpu_irqs, | |
1840 | .sdma_reqs = omap34xx_mmc2_sdma_reqs, | |
1841 | .opt_clks = omap34xx_mmc2_opt_clks, | |
1842 | .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc2_opt_clks), | |
1843 | .main_clk = "mmchs2_fck", | |
1844 | .prcm = { | |
1845 | .omap2 = { | |
1846 | .module_offs = CORE_MOD, | |
1847 | .prcm_reg_id = 1, | |
1848 | .module_bit = OMAP3430_EN_MMC2_SHIFT, | |
1849 | .idlest_reg_id = 1, | |
1850 | .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT, | |
1851 | }, | |
70034d38 | 1852 | }, |
844a3b63 PW |
1853 | .dev_attr = &mmc2_pre_es3_dev_attr, |
1854 | .class = &omap34xx_mmc_class, | |
70034d38 VC |
1855 | }; |
1856 | ||
844a3b63 PW |
1857 | static struct omap_hwmod omap3xxx_es3plus_mmc2_hwmod = { |
1858 | .name = "mmc2", | |
1859 | .mpu_irqs = omap34xx_mmc2_mpu_irqs, | |
1860 | .sdma_reqs = omap34xx_mmc2_sdma_reqs, | |
1861 | .opt_clks = omap34xx_mmc2_opt_clks, | |
1862 | .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc2_opt_clks), | |
1863 | .main_clk = "mmchs2_fck", | |
1864 | .prcm = { | |
1865 | .omap2 = { | |
1866 | .module_offs = CORE_MOD, | |
1867 | .prcm_reg_id = 1, | |
1868 | .module_bit = OMAP3430_EN_MMC2_SHIFT, | |
1869 | .idlest_reg_id = 1, | |
1870 | .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT, | |
1871 | }, | |
1872 | }, | |
1873 | .class = &omap34xx_mmc_class, | |
70034d38 VC |
1874 | }; |
1875 | ||
844a3b63 PW |
1876 | /* MMC/SD/SDIO3 */ |
1877 | ||
1878 | static struct omap_hwmod_irq_info omap34xx_mmc3_mpu_irqs[] = { | |
7d7e1eba TL |
1879 | { .irq = 94 + OMAP_INTC_START, }, |
1880 | { .irq = -1 }, | |
70034d38 VC |
1881 | }; |
1882 | ||
844a3b63 PW |
1883 | static struct omap_hwmod_dma_info omap34xx_mmc3_sdma_reqs[] = { |
1884 | { .name = "tx", .dma_req = 77, }, | |
1885 | { .name = "rx", .dma_req = 78, }, | |
1886 | { .dma_req = -1 } | |
70034d38 VC |
1887 | }; |
1888 | ||
844a3b63 PW |
1889 | static struct omap_hwmod_opt_clk omap34xx_mmc3_opt_clks[] = { |
1890 | { .role = "dbck", .clk = "omap_32k_fck", }, | |
70034d38 VC |
1891 | }; |
1892 | ||
844a3b63 PW |
1893 | static struct omap_hwmod omap3xxx_mmc3_hwmod = { |
1894 | .name = "mmc3", | |
1895 | .mpu_irqs = omap34xx_mmc3_mpu_irqs, | |
1896 | .sdma_reqs = omap34xx_mmc3_sdma_reqs, | |
1897 | .opt_clks = omap34xx_mmc3_opt_clks, | |
1898 | .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc3_opt_clks), | |
1899 | .main_clk = "mmchs3_fck", | |
1900 | .prcm = { | |
1901 | .omap2 = { | |
1902 | .prcm_reg_id = 1, | |
1903 | .module_bit = OMAP3430_EN_MMC3_SHIFT, | |
1904 | .idlest_reg_id = 1, | |
1905 | .idlest_idle_bit = OMAP3430_ST_MMC3_SHIFT, | |
1906 | }, | |
1907 | }, | |
1908 | .class = &omap34xx_mmc_class, | |
70034d38 VC |
1909 | }; |
1910 | ||
1911 | /* | |
844a3b63 PW |
1912 | * 'usb_host_hs' class |
1913 | * high-speed multi-port usb host controller | |
70034d38 VC |
1914 | */ |
1915 | ||
844a3b63 | 1916 | static struct omap_hwmod_class_sysconfig omap3xxx_usb_host_hs_sysc = { |
70034d38 VC |
1917 | .rev_offs = 0x0000, |
1918 | .sysc_offs = 0x0010, | |
1919 | .syss_offs = 0x0014, | |
844a3b63 PW |
1920 | .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY | |
1921 | SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP | | |
7f4d3641 RQ |
1922 | SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE | |
1923 | SYSS_HAS_RESET_STATUS), | |
844a3b63 PW |
1924 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | |
1925 | MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), | |
1926 | .sysc_fields = &omap_hwmod_sysc_type1, | |
70034d38 VC |
1927 | }; |
1928 | ||
844a3b63 PW |
1929 | static struct omap_hwmod_class omap3xxx_usb_host_hs_hwmod_class = { |
1930 | .name = "usb_host_hs", | |
1931 | .sysc = &omap3xxx_usb_host_hs_sysc, | |
70034d38 VC |
1932 | }; |
1933 | ||
844a3b63 | 1934 | static struct omap_hwmod_irq_info omap3xxx_usb_host_hs_irqs[] = { |
7d7e1eba TL |
1935 | { .name = "ohci-irq", .irq = 76 + OMAP_INTC_START, }, |
1936 | { .name = "ehci-irq", .irq = 77 + OMAP_INTC_START, }, | |
1937 | { .irq = -1 }, | |
70034d38 VC |
1938 | }; |
1939 | ||
844a3b63 PW |
1940 | static struct omap_hwmod omap3xxx_usb_host_hs_hwmod = { |
1941 | .name = "usb_host_hs", | |
1942 | .class = &omap3xxx_usb_host_hs_hwmod_class, | |
c6c56697 | 1943 | .clkdm_name = "usbhost_clkdm", |
844a3b63 PW |
1944 | .mpu_irqs = omap3xxx_usb_host_hs_irqs, |
1945 | .main_clk = "usbhost_48m_fck", | |
1946 | .prcm = { | |
70034d38 | 1947 | .omap2 = { |
844a3b63 | 1948 | .module_offs = OMAP3430ES2_USBHOST_MOD, |
70034d38 | 1949 | .prcm_reg_id = 1, |
844a3b63 | 1950 | .module_bit = OMAP3430ES2_EN_USBHOST1_SHIFT, |
70034d38 | 1951 | .idlest_reg_id = 1, |
844a3b63 PW |
1952 | .idlest_idle_bit = OMAP3430ES2_ST_USBHOST_IDLE_SHIFT, |
1953 | .idlest_stdby_bit = OMAP3430ES2_ST_USBHOST_STDBY_SHIFT, | |
70034d38 VC |
1954 | }, |
1955 | }, | |
70034d38 | 1956 | |
844a3b63 PW |
1957 | /* |
1958 | * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock | |
1959 | * id: i660 | |
1960 | * | |
1961 | * Description: | |
1962 | * In the following configuration : | |
1963 | * - USBHOST module is set to smart-idle mode | |
1964 | * - PRCM asserts idle_req to the USBHOST module ( This typically | |
1965 | * happens when the system is going to a low power mode : all ports | |
1966 | * have been suspended, the master part of the USBHOST module has | |
1967 | * entered the standby state, and SW has cut the functional clocks) | |
1968 | * - an USBHOST interrupt occurs before the module is able to answer | |
1969 | * idle_ack, typically a remote wakeup IRQ. | |
1970 | * Then the USB HOST module will enter a deadlock situation where it | |
1971 | * is no more accessible nor functional. | |
1972 | * | |
1973 | * Workaround: | |
1974 | * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE | |
1975 | */ | |
1976 | ||
1977 | /* | |
1978 | * Errata: USB host EHCI may stall when entering smart-standby mode | |
1979 | * Id: i571 | |
1980 | * | |
1981 | * Description: | |
1982 | * When the USBHOST module is set to smart-standby mode, and when it is | |
1983 | * ready to enter the standby state (i.e. all ports are suspended and | |
1984 | * all attached devices are in suspend mode), then it can wrongly assert | |
1985 | * the Mstandby signal too early while there are still some residual OCP | |
1986 | * transactions ongoing. If this condition occurs, the internal state | |
1987 | * machine may go to an undefined state and the USB link may be stuck | |
1988 | * upon the next resume. | |
1989 | * | |
1990 | * Workaround: | |
1991 | * Don't use smart standby; use only force standby, | |
1992 | * hence HWMOD_SWSUP_MSTANDBY | |
1993 | */ | |
1994 | ||
7f4d3641 | 1995 | .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY, |
70034d38 VC |
1996 | }; |
1997 | ||
844a3b63 PW |
1998 | /* |
1999 | * 'usb_tll_hs' class | |
2000 | * usb_tll_hs module is the adapter on the usb_host_hs ports | |
2001 | */ | |
2002 | static struct omap_hwmod_class_sysconfig omap3xxx_usb_tll_hs_sysc = { | |
2003 | .rev_offs = 0x0000, | |
2004 | .sysc_offs = 0x0010, | |
2005 | .syss_offs = 0x0014, | |
2006 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | | |
2007 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | | |
2008 | SYSC_HAS_AUTOIDLE), | |
2009 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
2010 | .sysc_fields = &omap_hwmod_sysc_type1, | |
70034d38 VC |
2011 | }; |
2012 | ||
844a3b63 PW |
2013 | static struct omap_hwmod_class omap3xxx_usb_tll_hs_hwmod_class = { |
2014 | .name = "usb_tll_hs", | |
2015 | .sysc = &omap3xxx_usb_tll_hs_sysc, | |
70034d38 VC |
2016 | }; |
2017 | ||
844a3b63 | 2018 | static struct omap_hwmod_irq_info omap3xxx_usb_tll_hs_irqs[] = { |
7d7e1eba TL |
2019 | { .name = "tll-irq", .irq = 78 + OMAP_INTC_START, }, |
2020 | { .irq = -1 }, | |
70034d38 VC |
2021 | }; |
2022 | ||
844a3b63 PW |
2023 | static struct omap_hwmod omap3xxx_usb_tll_hs_hwmod = { |
2024 | .name = "usb_tll_hs", | |
2025 | .class = &omap3xxx_usb_tll_hs_hwmod_class, | |
c6c56697 | 2026 | .clkdm_name = "core_l4_clkdm", |
844a3b63 PW |
2027 | .mpu_irqs = omap3xxx_usb_tll_hs_irqs, |
2028 | .main_clk = "usbtll_fck", | |
2029 | .prcm = { | |
70034d38 | 2030 | .omap2 = { |
844a3b63 PW |
2031 | .module_offs = CORE_MOD, |
2032 | .prcm_reg_id = 3, | |
2033 | .module_bit = OMAP3430ES2_EN_USBTLL_SHIFT, | |
2034 | .idlest_reg_id = 3, | |
2035 | .idlest_idle_bit = OMAP3430ES2_ST_USBTLL_SHIFT, | |
70034d38 VC |
2036 | }, |
2037 | }, | |
70034d38 VC |
2038 | }; |
2039 | ||
45a4bb06 PW |
2040 | static struct omap_hwmod omap3xxx_hdq1w_hwmod = { |
2041 | .name = "hdq1w", | |
2042 | .mpu_irqs = omap2_hdq1w_mpu_irqs, | |
2043 | .main_clk = "hdq_fck", | |
2044 | .prcm = { | |
2045 | .omap2 = { | |
2046 | .module_offs = CORE_MOD, | |
2047 | .prcm_reg_id = 1, | |
2048 | .module_bit = OMAP3430_EN_HDQ_SHIFT, | |
2049 | .idlest_reg_id = 1, | |
2050 | .idlest_idle_bit = OMAP3430_ST_HDQ_SHIFT, | |
2051 | }, | |
2052 | }, | |
2053 | .class = &omap2_hdq1w_class, | |
2054 | }; | |
2055 | ||
8f993a01 TK |
2056 | /* SAD2D */ |
2057 | static struct omap_hwmod_rst_info omap3xxx_sad2d_resets[] = { | |
2058 | { .name = "rst_modem_pwron_sw", .rst_shift = 0 }, | |
2059 | { .name = "rst_modem_sw", .rst_shift = 1 }, | |
2060 | }; | |
2061 | ||
2062 | static struct omap_hwmod_class omap3xxx_sad2d_class = { | |
2063 | .name = "sad2d", | |
2064 | }; | |
2065 | ||
2066 | static struct omap_hwmod omap3xxx_sad2d_hwmod = { | |
2067 | .name = "sad2d", | |
2068 | .rst_lines = omap3xxx_sad2d_resets, | |
2069 | .rst_lines_cnt = ARRAY_SIZE(omap3xxx_sad2d_resets), | |
2070 | .main_clk = "sad2d_ick", | |
2071 | .prcm = { | |
2072 | .omap2 = { | |
2073 | .module_offs = CORE_MOD, | |
2074 | .prcm_reg_id = 1, | |
2075 | .module_bit = OMAP3430_EN_SAD2D_SHIFT, | |
2076 | .idlest_reg_id = 1, | |
2077 | .idlest_idle_bit = OMAP3430_ST_SAD2D_SHIFT, | |
2078 | }, | |
2079 | }, | |
2080 | .class = &omap3xxx_sad2d_class, | |
2081 | }; | |
2082 | ||
c8d82ff6 VH |
2083 | /* |
2084 | * '32K sync counter' class | |
2085 | * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock | |
2086 | */ | |
2087 | static struct omap_hwmod_class_sysconfig omap3xxx_counter_sysc = { | |
2088 | .rev_offs = 0x0000, | |
2089 | .sysc_offs = 0x0004, | |
2090 | .sysc_flags = SYSC_HAS_SIDLEMODE, | |
2091 | .idlemodes = (SIDLE_FORCE | SIDLE_NO), | |
2092 | .sysc_fields = &omap_hwmod_sysc_type1, | |
2093 | }; | |
2094 | ||
2095 | static struct omap_hwmod_class omap3xxx_counter_hwmod_class = { | |
2096 | .name = "counter", | |
2097 | .sysc = &omap3xxx_counter_sysc, | |
2098 | }; | |
2099 | ||
2100 | static struct omap_hwmod omap3xxx_counter_32k_hwmod = { | |
2101 | .name = "counter_32k", | |
2102 | .class = &omap3xxx_counter_hwmod_class, | |
2103 | .clkdm_name = "wkup_clkdm", | |
2104 | .flags = HWMOD_SWSUP_SIDLE, | |
2105 | .main_clk = "wkup_32k_fck", | |
2106 | .prcm = { | |
2107 | .omap2 = { | |
2108 | .module_offs = WKUP_MOD, | |
2109 | .prcm_reg_id = 1, | |
2110 | .module_bit = OMAP3430_ST_32KSYNC_SHIFT, | |
2111 | .idlest_reg_id = 1, | |
2112 | .idlest_idle_bit = OMAP3430_ST_32KSYNC_SHIFT, | |
2113 | }, | |
2114 | }, | |
2115 | }; | |
2116 | ||
49484a60 AM |
2117 | /* |
2118 | * 'gpmc' class | |
2119 | * general purpose memory controller | |
2120 | */ | |
2121 | ||
2122 | static struct omap_hwmod_class_sysconfig omap3xxx_gpmc_sysc = { | |
2123 | .rev_offs = 0x0000, | |
2124 | .sysc_offs = 0x0010, | |
2125 | .syss_offs = 0x0014, | |
2126 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE | | |
2127 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), | |
2128 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
2129 | .sysc_fields = &omap_hwmod_sysc_type1, | |
2130 | }; | |
2131 | ||
2132 | static struct omap_hwmod_class omap3xxx_gpmc_hwmod_class = { | |
2133 | .name = "gpmc", | |
2134 | .sysc = &omap3xxx_gpmc_sysc, | |
2135 | }; | |
2136 | ||
2137 | static struct omap_hwmod_irq_info omap3xxx_gpmc_irqs[] = { | |
6d4c8830 | 2138 | { .irq = 20 + OMAP_INTC_START, }, |
49484a60 AM |
2139 | { .irq = -1 } |
2140 | }; | |
2141 | ||
2142 | static struct omap_hwmod omap3xxx_gpmc_hwmod = { | |
2143 | .name = "gpmc", | |
2144 | .class = &omap3xxx_gpmc_hwmod_class, | |
2145 | .clkdm_name = "core_l3_clkdm", | |
2146 | .mpu_irqs = omap3xxx_gpmc_irqs, | |
2147 | .main_clk = "gpmc_fck", | |
63aa945b TL |
2148 | /* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */ |
2149 | .flags = HWMOD_NO_IDLEST | DEBUG_OMAP_GPMC_HWMOD_FLAGS, | |
49484a60 AM |
2150 | }; |
2151 | ||
844a3b63 PW |
2152 | /* |
2153 | * interfaces | |
2154 | */ | |
2155 | ||
2156 | /* L3 -> L4_CORE interface */ | |
2157 | static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = { | |
2158 | .master = &omap3xxx_l3_main_hwmod, | |
2159 | .slave = &omap3xxx_l4_core_hwmod, | |
2160 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
70034d38 VC |
2161 | }; |
2162 | ||
844a3b63 PW |
2163 | /* L3 -> L4_PER interface */ |
2164 | static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per = { | |
2165 | .master = &omap3xxx_l3_main_hwmod, | |
2166 | .slave = &omap3xxx_l4_per_hwmod, | |
2167 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
70034d38 VC |
2168 | }; |
2169 | ||
844a3b63 PW |
2170 | static struct omap_hwmod_addr_space omap3xxx_l3_main_addrs[] = { |
2171 | { | |
2172 | .pa_start = 0x68000000, | |
2173 | .pa_end = 0x6800ffff, | |
2174 | .flags = ADDR_TYPE_RT, | |
70034d38 | 2175 | }, |
844a3b63 | 2176 | { } |
70034d38 VC |
2177 | }; |
2178 | ||
844a3b63 PW |
2179 | /* MPU -> L3 interface */ |
2180 | static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = { | |
2181 | .master = &omap3xxx_mpu_hwmod, | |
2182 | .slave = &omap3xxx_l3_main_hwmod, | |
2183 | .addr = omap3xxx_l3_main_addrs, | |
2184 | .user = OCP_USER_MPU, | |
70034d38 VC |
2185 | }; |
2186 | ||
c7dad45f JH |
2187 | static struct omap_hwmod_addr_space omap3xxx_l4_emu_addrs[] = { |
2188 | { | |
2189 | .pa_start = 0x54000000, | |
2190 | .pa_end = 0x547fffff, | |
2191 | .flags = ADDR_TYPE_RT, | |
2192 | }, | |
2193 | { } | |
2194 | }; | |
2195 | ||
2196 | /* l3 -> debugss */ | |
2197 | static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_debugss = { | |
2198 | .master = &omap3xxx_l3_main_hwmod, | |
2199 | .slave = &omap3xxx_debugss_hwmod, | |
76a5d9bf | 2200 | .addr = omap3xxx_l4_emu_addrs, |
c7dad45f JH |
2201 | .user = OCP_USER_MPU, |
2202 | }; | |
2203 | ||
844a3b63 PW |
2204 | /* DSS -> l3 */ |
2205 | static struct omap_hwmod_ocp_if omap3430es1_dss__l3 = { | |
2206 | .master = &omap3430es1_dss_core_hwmod, | |
2207 | .slave = &omap3xxx_l3_main_hwmod, | |
2208 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
70034d38 VC |
2209 | }; |
2210 | ||
844a3b63 PW |
2211 | static struct omap_hwmod_ocp_if omap3xxx_dss__l3 = { |
2212 | .master = &omap3xxx_dss_core_hwmod, | |
2213 | .slave = &omap3xxx_l3_main_hwmod, | |
2214 | .fw = { | |
70034d38 | 2215 | .omap2 = { |
844a3b63 PW |
2216 | .l3_perm_bit = OMAP3_L3_CORE_FW_INIT_ID_DSS, |
2217 | .flags = OMAP_FIREWALL_L3, | |
2218 | } | |
70034d38 | 2219 | }, |
844a3b63 | 2220 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
70034d38 VC |
2221 | }; |
2222 | ||
844a3b63 PW |
2223 | /* l3_core -> usbhsotg interface */ |
2224 | static struct omap_hwmod_ocp_if omap3xxx_usbhsotg__l3 = { | |
2225 | .master = &omap3xxx_usbhsotg_hwmod, | |
01438ab6 MK |
2226 | .slave = &omap3xxx_l3_main_hwmod, |
2227 | .clk = "core_l3_ick", | |
844a3b63 | 2228 | .user = OCP_USER_MPU, |
01438ab6 MK |
2229 | }; |
2230 | ||
844a3b63 PW |
2231 | /* l3_core -> am35xx_usbhsotg interface */ |
2232 | static struct omap_hwmod_ocp_if am35xx_usbhsotg__l3 = { | |
2233 | .master = &am35xx_usbhsotg_hwmod, | |
2234 | .slave = &omap3xxx_l3_main_hwmod, | |
89ea2583 | 2235 | .clk = "hsotgusb_ick", |
844a3b63 | 2236 | .user = OCP_USER_MPU, |
01438ab6 | 2237 | }; |
89ea2583 | 2238 | |
8f993a01 TK |
2239 | /* l3_core -> sad2d interface */ |
2240 | static struct omap_hwmod_ocp_if omap3xxx_sad2d__l3 = { | |
2241 | .master = &omap3xxx_sad2d_hwmod, | |
2242 | .slave = &omap3xxx_l3_main_hwmod, | |
2243 | .clk = "core_l3_ick", | |
2244 | .user = OCP_USER_MPU, | |
2245 | }; | |
2246 | ||
844a3b63 PW |
2247 | /* L4_CORE -> L4_WKUP interface */ |
2248 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = { | |
2249 | .master = &omap3xxx_l4_core_hwmod, | |
2250 | .slave = &omap3xxx_l4_wkup_hwmod, | |
2251 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
01438ab6 MK |
2252 | }; |
2253 | ||
844a3b63 PW |
2254 | /* L4 CORE -> MMC1 interface */ |
2255 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__pre_es3_mmc1 = { | |
01438ab6 | 2256 | .master = &omap3xxx_l4_core_hwmod, |
844a3b63 PW |
2257 | .slave = &omap3xxx_pre_es3_mmc1_hwmod, |
2258 | .clk = "mmchs1_ick", | |
2259 | .addr = omap2430_mmc1_addr_space, | |
01438ab6 | 2260 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
844a3b63 | 2261 | .flags = OMAP_FIREWALL_L4 |
01438ab6 MK |
2262 | }; |
2263 | ||
844a3b63 PW |
2264 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__es3plus_mmc1 = { |
2265 | .master = &omap3xxx_l4_core_hwmod, | |
2266 | .slave = &omap3xxx_es3plus_mmc1_hwmod, | |
2267 | .clk = "mmchs1_ick", | |
2268 | .addr = omap2430_mmc1_addr_space, | |
2269 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2270 | .flags = OMAP_FIREWALL_L4 | |
01438ab6 MK |
2271 | }; |
2272 | ||
844a3b63 PW |
2273 | /* L4 CORE -> MMC2 interface */ |
2274 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__pre_es3_mmc2 = { | |
2275 | .master = &omap3xxx_l4_core_hwmod, | |
2276 | .slave = &omap3xxx_pre_es3_mmc2_hwmod, | |
2277 | .clk = "mmchs2_ick", | |
2278 | .addr = omap2430_mmc2_addr_space, | |
2279 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2280 | .flags = OMAP_FIREWALL_L4 | |
2281 | }; | |
70034d38 | 2282 | |
844a3b63 PW |
2283 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__es3plus_mmc2 = { |
2284 | .master = &omap3xxx_l4_core_hwmod, | |
2285 | .slave = &omap3xxx_es3plus_mmc2_hwmod, | |
2286 | .clk = "mmchs2_ick", | |
2287 | .addr = omap2430_mmc2_addr_space, | |
2288 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2289 | .flags = OMAP_FIREWALL_L4 | |
70034d38 VC |
2290 | }; |
2291 | ||
844a3b63 PW |
2292 | /* L4 CORE -> MMC3 interface */ |
2293 | static struct omap_hwmod_addr_space omap3xxx_mmc3_addr_space[] = { | |
2294 | { | |
2295 | .pa_start = 0x480ad000, | |
2296 | .pa_end = 0x480ad1ff, | |
2297 | .flags = ADDR_TYPE_RT, | |
2298 | }, | |
2299 | { } | |
70034d38 VC |
2300 | }; |
2301 | ||
844a3b63 PW |
2302 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc3 = { |
2303 | .master = &omap3xxx_l4_core_hwmod, | |
2304 | .slave = &omap3xxx_mmc3_hwmod, | |
2305 | .clk = "mmchs3_ick", | |
2306 | .addr = omap3xxx_mmc3_addr_space, | |
2307 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2308 | .flags = OMAP_FIREWALL_L4 | |
70034d38 VC |
2309 | }; |
2310 | ||
844a3b63 PW |
2311 | /* L4 CORE -> UART1 interface */ |
2312 | static struct omap_hwmod_addr_space omap3xxx_uart1_addr_space[] = { | |
dc48e5fc | 2313 | { |
844a3b63 PW |
2314 | .pa_start = OMAP3_UART1_BASE, |
2315 | .pa_end = OMAP3_UART1_BASE + SZ_8K - 1, | |
2316 | .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, | |
dc48e5fc | 2317 | }, |
78183f3f | 2318 | { } |
70034d38 VC |
2319 | }; |
2320 | ||
844a3b63 | 2321 | static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = { |
dc48e5fc | 2322 | .master = &omap3xxx_l4_core_hwmod, |
844a3b63 PW |
2323 | .slave = &omap3xxx_uart1_hwmod, |
2324 | .clk = "uart1_ick", | |
2325 | .addr = omap3xxx_uart1_addr_space, | |
dc48e5fc | 2326 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
70034d38 VC |
2327 | }; |
2328 | ||
844a3b63 PW |
2329 | /* L4 CORE -> UART2 interface */ |
2330 | static struct omap_hwmod_addr_space omap3xxx_uart2_addr_space[] = { | |
2331 | { | |
2332 | .pa_start = OMAP3_UART2_BASE, | |
2333 | .pa_end = OMAP3_UART2_BASE + SZ_1K - 1, | |
2334 | .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, | |
70034d38 | 2335 | }, |
844a3b63 | 2336 | { } |
70034d38 VC |
2337 | }; |
2338 | ||
844a3b63 PW |
2339 | static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = { |
2340 | .master = &omap3xxx_l4_core_hwmod, | |
2341 | .slave = &omap3xxx_uart2_hwmod, | |
2342 | .clk = "uart2_ick", | |
2343 | .addr = omap3xxx_uart2_addr_space, | |
2344 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
70034d38 VC |
2345 | }; |
2346 | ||
844a3b63 PW |
2347 | /* L4 PER -> UART3 interface */ |
2348 | static struct omap_hwmod_addr_space omap3xxx_uart3_addr_space[] = { | |
dc48e5fc | 2349 | { |
844a3b63 PW |
2350 | .pa_start = OMAP3_UART3_BASE, |
2351 | .pa_end = OMAP3_UART3_BASE + SZ_1K - 1, | |
2352 | .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, | |
70034d38 | 2353 | }, |
78183f3f | 2354 | { } |
70034d38 VC |
2355 | }; |
2356 | ||
844a3b63 | 2357 | static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = { |
dc48e5fc | 2358 | .master = &omap3xxx_l4_per_hwmod, |
844a3b63 PW |
2359 | .slave = &omap3xxx_uart3_hwmod, |
2360 | .clk = "uart3_ick", | |
2361 | .addr = omap3xxx_uart3_addr_space, | |
dc48e5fc | 2362 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
70034d38 VC |
2363 | }; |
2364 | ||
844a3b63 PW |
2365 | /* L4 PER -> UART4 interface */ |
2366 | static struct omap_hwmod_addr_space omap36xx_uart4_addr_space[] = { | |
2367 | { | |
2368 | .pa_start = OMAP3_UART4_BASE, | |
2369 | .pa_end = OMAP3_UART4_BASE + SZ_1K - 1, | |
2370 | .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, | |
70034d38 | 2371 | }, |
844a3b63 | 2372 | { } |
70034d38 VC |
2373 | }; |
2374 | ||
844a3b63 PW |
2375 | static struct omap_hwmod_ocp_if omap36xx_l4_per__uart4 = { |
2376 | .master = &omap3xxx_l4_per_hwmod, | |
2377 | .slave = &omap36xx_uart4_hwmod, | |
2378 | .clk = "uart4_ick", | |
2379 | .addr = omap36xx_uart4_addr_space, | |
2380 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
70034d38 VC |
2381 | }; |
2382 | ||
844a3b63 PW |
2383 | /* AM35xx: L4 CORE -> UART4 interface */ |
2384 | static struct omap_hwmod_addr_space am35xx_uart4_addr_space[] = { | |
dc48e5fc | 2385 | { |
844a3b63 PW |
2386 | .pa_start = OMAP3_UART4_AM35XX_BASE, |
2387 | .pa_end = OMAP3_UART4_AM35XX_BASE + SZ_1K - 1, | |
2388 | .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, | |
dc48e5fc | 2389 | }, |
bf765237 | 2390 | { } |
70034d38 VC |
2391 | }; |
2392 | ||
844a3b63 PW |
2393 | static struct omap_hwmod_ocp_if am35xx_l4_core__uart4 = { |
2394 | .master = &omap3xxx_l4_core_hwmod, | |
2395 | .slave = &am35xx_uart4_hwmod, | |
2396 | .clk = "uart4_ick", | |
2397 | .addr = am35xx_uart4_addr_space, | |
dc48e5fc C |
2398 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
2399 | }; | |
2400 | ||
844a3b63 PW |
2401 | /* L4 CORE -> I2C1 interface */ |
2402 | static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = { | |
2403 | .master = &omap3xxx_l4_core_hwmod, | |
2404 | .slave = &omap3xxx_i2c1_hwmod, | |
2405 | .clk = "i2c1_ick", | |
2406 | .addr = omap2_i2c1_addr_space, | |
2407 | .fw = { | |
2408 | .omap2 = { | |
2409 | .l4_fw_region = OMAP3_L4_CORE_FW_I2C1_REGION, | |
2410 | .l4_prot_group = 7, | |
2411 | .flags = OMAP_FIREWALL_L4, | |
2412 | } | |
2413 | }, | |
2414 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
8b1906f1 KVA |
2415 | }; |
2416 | ||
844a3b63 PW |
2417 | /* L4 CORE -> I2C2 interface */ |
2418 | static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = { | |
2419 | .master = &omap3xxx_l4_core_hwmod, | |
2420 | .slave = &omap3xxx_i2c2_hwmod, | |
2421 | .clk = "i2c2_ick", | |
2422 | .addr = omap2_i2c2_addr_space, | |
2423 | .fw = { | |
70034d38 | 2424 | .omap2 = { |
844a3b63 PW |
2425 | .l4_fw_region = OMAP3_L4_CORE_FW_I2C2_REGION, |
2426 | .l4_prot_group = 7, | |
2427 | .flags = OMAP_FIREWALL_L4, | |
2428 | } | |
70034d38 | 2429 | }, |
844a3b63 | 2430 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
70034d38 VC |
2431 | }; |
2432 | ||
844a3b63 PW |
2433 | /* L4 CORE -> I2C3 interface */ |
2434 | static struct omap_hwmod_addr_space omap3xxx_i2c3_addr_space[] = { | |
2435 | { | |
2436 | .pa_start = 0x48060000, | |
2437 | .pa_end = 0x48060000 + SZ_128 - 1, | |
2438 | .flags = ADDR_TYPE_RT, | |
2439 | }, | |
2440 | { } | |
70034d38 VC |
2441 | }; |
2442 | ||
844a3b63 PW |
2443 | static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = { |
2444 | .master = &omap3xxx_l4_core_hwmod, | |
2445 | .slave = &omap3xxx_i2c3_hwmod, | |
2446 | .clk = "i2c3_ick", | |
2447 | .addr = omap3xxx_i2c3_addr_space, | |
2448 | .fw = { | |
2449 | .omap2 = { | |
2450 | .l4_fw_region = OMAP3_L4_CORE_FW_I2C3_REGION, | |
2451 | .l4_prot_group = 7, | |
2452 | .flags = OMAP_FIREWALL_L4, | |
2453 | } | |
2454 | }, | |
2455 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
70034d38 VC |
2456 | }; |
2457 | ||
844a3b63 PW |
2458 | /* L4 CORE -> SR1 interface */ |
2459 | static struct omap_hwmod_addr_space omap3_sr1_addr_space[] = { | |
dc48e5fc | 2460 | { |
844a3b63 PW |
2461 | .pa_start = OMAP34XX_SR1_BASE, |
2462 | .pa_end = OMAP34XX_SR1_BASE + SZ_1K - 1, | |
2463 | .flags = ADDR_TYPE_RT, | |
dc48e5fc | 2464 | }, |
78183f3f | 2465 | { } |
70034d38 VC |
2466 | }; |
2467 | ||
844a3b63 PW |
2468 | static struct omap_hwmod_ocp_if omap34xx_l4_core__sr1 = { |
2469 | .master = &omap3xxx_l4_core_hwmod, | |
2470 | .slave = &omap34xx_sr1_hwmod, | |
2471 | .clk = "sr_l4_ick", | |
2472 | .addr = omap3_sr1_addr_space, | |
2473 | .user = OCP_USER_MPU, | |
70034d38 VC |
2474 | }; |
2475 | ||
844a3b63 PW |
2476 | static struct omap_hwmod_ocp_if omap36xx_l4_core__sr1 = { |
2477 | .master = &omap3xxx_l4_core_hwmod, | |
2478 | .slave = &omap36xx_sr1_hwmod, | |
2479 | .clk = "sr_l4_ick", | |
2480 | .addr = omap3_sr1_addr_space, | |
2481 | .user = OCP_USER_MPU, | |
2482 | }; | |
2483 | ||
2484 | /* L4 CORE -> SR1 interface */ | |
2485 | static struct omap_hwmod_addr_space omap3_sr2_addr_space[] = { | |
2486 | { | |
2487 | .pa_start = OMAP34XX_SR2_BASE, | |
2488 | .pa_end = OMAP34XX_SR2_BASE + SZ_1K - 1, | |
2489 | .flags = ADDR_TYPE_RT, | |
70034d38 | 2490 | }, |
844a3b63 | 2491 | { } |
70034d38 VC |
2492 | }; |
2493 | ||
844a3b63 PW |
2494 | static struct omap_hwmod_ocp_if omap34xx_l4_core__sr2 = { |
2495 | .master = &omap3xxx_l4_core_hwmod, | |
2496 | .slave = &omap34xx_sr2_hwmod, | |
2497 | .clk = "sr_l4_ick", | |
2498 | .addr = omap3_sr2_addr_space, | |
2499 | .user = OCP_USER_MPU, | |
70034d38 VC |
2500 | }; |
2501 | ||
844a3b63 PW |
2502 | static struct omap_hwmod_ocp_if omap36xx_l4_core__sr2 = { |
2503 | .master = &omap3xxx_l4_core_hwmod, | |
2504 | .slave = &omap36xx_sr2_hwmod, | |
2505 | .clk = "sr_l4_ick", | |
2506 | .addr = omap3_sr2_addr_space, | |
2507 | .user = OCP_USER_MPU, | |
70034d38 VC |
2508 | }; |
2509 | ||
844a3b63 | 2510 | static struct omap_hwmod_addr_space omap3xxx_usbhsotg_addrs[] = { |
dc48e5fc | 2511 | { |
844a3b63 PW |
2512 | .pa_start = OMAP34XX_HSUSB_OTG_BASE, |
2513 | .pa_end = OMAP34XX_HSUSB_OTG_BASE + SZ_4K - 1, | |
dc48e5fc C |
2514 | .flags = ADDR_TYPE_RT |
2515 | }, | |
78183f3f | 2516 | { } |
70034d38 VC |
2517 | }; |
2518 | ||
844a3b63 PW |
2519 | /* l4_core -> usbhsotg */ |
2520 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__usbhsotg = { | |
dc48e5fc | 2521 | .master = &omap3xxx_l4_core_hwmod, |
844a3b63 PW |
2522 | .slave = &omap3xxx_usbhsotg_hwmod, |
2523 | .clk = "l4_ick", | |
2524 | .addr = omap3xxx_usbhsotg_addrs, | |
2525 | .user = OCP_USER_MPU, | |
dc48e5fc C |
2526 | }; |
2527 | ||
844a3b63 PW |
2528 | static struct omap_hwmod_addr_space am35xx_usbhsotg_addrs[] = { |
2529 | { | |
2530 | .pa_start = AM35XX_IPSS_USBOTGSS_BASE, | |
2531 | .pa_end = AM35XX_IPSS_USBOTGSS_BASE + SZ_4K - 1, | |
2532 | .flags = ADDR_TYPE_RT | |
70034d38 | 2533 | }, |
844a3b63 | 2534 | { } |
70034d38 VC |
2535 | }; |
2536 | ||
844a3b63 PW |
2537 | /* l4_core -> usbhsotg */ |
2538 | static struct omap_hwmod_ocp_if am35xx_l4_core__usbhsotg = { | |
2539 | .master = &omap3xxx_l4_core_hwmod, | |
2540 | .slave = &am35xx_usbhsotg_hwmod, | |
89ea2583 | 2541 | .clk = "hsotgusb_ick", |
844a3b63 PW |
2542 | .addr = am35xx_usbhsotg_addrs, |
2543 | .user = OCP_USER_MPU, | |
01438ab6 MK |
2544 | }; |
2545 | ||
844a3b63 PW |
2546 | /* L4_WKUP -> L4_SEC interface */ |
2547 | static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__l4_sec = { | |
2548 | .master = &omap3xxx_l4_wkup_hwmod, | |
2549 | .slave = &omap3xxx_l4_sec_hwmod, | |
2550 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
01438ab6 MK |
2551 | }; |
2552 | ||
844a3b63 PW |
2553 | /* IVA2 <- L3 interface */ |
2554 | static struct omap_hwmod_ocp_if omap3xxx_l3__iva = { | |
2555 | .master = &omap3xxx_l3_main_hwmod, | |
2556 | .slave = &omap3xxx_iva_hwmod, | |
064931ab | 2557 | .clk = "core_l3_ick", |
844a3b63 | 2558 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
01438ab6 MK |
2559 | }; |
2560 | ||
844a3b63 | 2561 | static struct omap_hwmod_addr_space omap3xxx_timer1_addrs[] = { |
dc48e5fc | 2562 | { |
844a3b63 PW |
2563 | .pa_start = 0x48318000, |
2564 | .pa_end = 0x48318000 + SZ_1K - 1, | |
dc48e5fc C |
2565 | .flags = ADDR_TYPE_RT |
2566 | }, | |
78183f3f | 2567 | { } |
01438ab6 MK |
2568 | }; |
2569 | ||
844a3b63 PW |
2570 | /* l4_wkup -> timer1 */ |
2571 | static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__timer1 = { | |
2572 | .master = &omap3xxx_l4_wkup_hwmod, | |
2573 | .slave = &omap3xxx_timer1_hwmod, | |
2574 | .clk = "gpt1_ick", | |
2575 | .addr = omap3xxx_timer1_addrs, | |
2576 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
01438ab6 MK |
2577 | }; |
2578 | ||
844a3b63 PW |
2579 | static struct omap_hwmod_addr_space omap3xxx_timer2_addrs[] = { |
2580 | { | |
2581 | .pa_start = 0x49032000, | |
2582 | .pa_end = 0x49032000 + SZ_1K - 1, | |
2583 | .flags = ADDR_TYPE_RT | |
01438ab6 | 2584 | }, |
844a3b63 | 2585 | { } |
01438ab6 MK |
2586 | }; |
2587 | ||
844a3b63 PW |
2588 | /* l4_per -> timer2 */ |
2589 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer2 = { | |
2590 | .master = &omap3xxx_l4_per_hwmod, | |
2591 | .slave = &omap3xxx_timer2_hwmod, | |
2592 | .clk = "gpt2_ick", | |
2593 | .addr = omap3xxx_timer2_addrs, | |
2594 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
01438ab6 MK |
2595 | }; |
2596 | ||
844a3b63 | 2597 | static struct omap_hwmod_addr_space omap3xxx_timer3_addrs[] = { |
dc48e5fc | 2598 | { |
844a3b63 PW |
2599 | .pa_start = 0x49034000, |
2600 | .pa_end = 0x49034000 + SZ_1K - 1, | |
dc48e5fc C |
2601 | .flags = ADDR_TYPE_RT |
2602 | }, | |
78183f3f | 2603 | { } |
01438ab6 MK |
2604 | }; |
2605 | ||
844a3b63 PW |
2606 | /* l4_per -> timer3 */ |
2607 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer3 = { | |
dc48e5fc | 2608 | .master = &omap3xxx_l4_per_hwmod, |
844a3b63 PW |
2609 | .slave = &omap3xxx_timer3_hwmod, |
2610 | .clk = "gpt3_ick", | |
2611 | .addr = omap3xxx_timer3_addrs, | |
2612 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
01438ab6 MK |
2613 | }; |
2614 | ||
844a3b63 PW |
2615 | static struct omap_hwmod_addr_space omap3xxx_timer4_addrs[] = { |
2616 | { | |
2617 | .pa_start = 0x49036000, | |
2618 | .pa_end = 0x49036000 + SZ_1K - 1, | |
2619 | .flags = ADDR_TYPE_RT | |
01438ab6 | 2620 | }, |
844a3b63 | 2621 | { } |
01438ab6 MK |
2622 | }; |
2623 | ||
844a3b63 PW |
2624 | /* l4_per -> timer4 */ |
2625 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer4 = { | |
2626 | .master = &omap3xxx_l4_per_hwmod, | |
2627 | .slave = &omap3xxx_timer4_hwmod, | |
2628 | .clk = "gpt4_ick", | |
2629 | .addr = omap3xxx_timer4_addrs, | |
2630 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
d3442726 TG |
2631 | }; |
2632 | ||
844a3b63 PW |
2633 | static struct omap_hwmod_addr_space omap3xxx_timer5_addrs[] = { |
2634 | { | |
2635 | .pa_start = 0x49038000, | |
2636 | .pa_end = 0x49038000 + SZ_1K - 1, | |
2637 | .flags = ADDR_TYPE_RT | |
2638 | }, | |
2639 | { } | |
d3442726 TG |
2640 | }; |
2641 | ||
844a3b63 PW |
2642 | /* l4_per -> timer5 */ |
2643 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer5 = { | |
2644 | .master = &omap3xxx_l4_per_hwmod, | |
2645 | .slave = &omap3xxx_timer5_hwmod, | |
2646 | .clk = "gpt5_ick", | |
2647 | .addr = omap3xxx_timer5_addrs, | |
2648 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
d3442726 TG |
2649 | }; |
2650 | ||
844a3b63 PW |
2651 | static struct omap_hwmod_addr_space omap3xxx_timer6_addrs[] = { |
2652 | { | |
2653 | .pa_start = 0x4903A000, | |
2654 | .pa_end = 0x4903A000 + SZ_1K - 1, | |
2655 | .flags = ADDR_TYPE_RT | |
2656 | }, | |
2657 | { } | |
cea6b942 SG |
2658 | }; |
2659 | ||
844a3b63 PW |
2660 | /* l4_per -> timer6 */ |
2661 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer6 = { | |
2662 | .master = &omap3xxx_l4_per_hwmod, | |
2663 | .slave = &omap3xxx_timer6_hwmod, | |
2664 | .clk = "gpt6_ick", | |
2665 | .addr = omap3xxx_timer6_addrs, | |
2666 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
d3442726 TG |
2667 | }; |
2668 | ||
844a3b63 PW |
2669 | static struct omap_hwmod_addr_space omap3xxx_timer7_addrs[] = { |
2670 | { | |
2671 | .pa_start = 0x4903C000, | |
2672 | .pa_end = 0x4903C000 + SZ_1K - 1, | |
2673 | .flags = ADDR_TYPE_RT | |
d3442726 | 2674 | }, |
844a3b63 | 2675 | { } |
d3442726 TG |
2676 | }; |
2677 | ||
844a3b63 PW |
2678 | /* l4_per -> timer7 */ |
2679 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer7 = { | |
2680 | .master = &omap3xxx_l4_per_hwmod, | |
2681 | .slave = &omap3xxx_timer7_hwmod, | |
2682 | .clk = "gpt7_ick", | |
2683 | .addr = omap3xxx_timer7_addrs, | |
2684 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
cea6b942 SG |
2685 | }; |
2686 | ||
844a3b63 PW |
2687 | static struct omap_hwmod_addr_space omap3xxx_timer8_addrs[] = { |
2688 | { | |
2689 | .pa_start = 0x4903E000, | |
2690 | .pa_end = 0x4903E000 + SZ_1K - 1, | |
2691 | .flags = ADDR_TYPE_RT | |
d3442726 | 2692 | }, |
844a3b63 | 2693 | { } |
d3442726 TG |
2694 | }; |
2695 | ||
844a3b63 PW |
2696 | /* l4_per -> timer8 */ |
2697 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer8 = { | |
2698 | .master = &omap3xxx_l4_per_hwmod, | |
2699 | .slave = &omap3xxx_timer8_hwmod, | |
2700 | .clk = "gpt8_ick", | |
2701 | .addr = omap3xxx_timer8_addrs, | |
2702 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
d3442726 TG |
2703 | }; |
2704 | ||
844a3b63 PW |
2705 | static struct omap_hwmod_addr_space omap3xxx_timer9_addrs[] = { |
2706 | { | |
2707 | .pa_start = 0x49040000, | |
2708 | .pa_end = 0x49040000 + SZ_1K - 1, | |
2709 | .flags = ADDR_TYPE_RT | |
2710 | }, | |
2711 | { } | |
2712 | }; | |
0f9dfdd3 | 2713 | |
844a3b63 PW |
2714 | /* l4_per -> timer9 */ |
2715 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer9 = { | |
2716 | .master = &omap3xxx_l4_per_hwmod, | |
2717 | .slave = &omap3xxx_timer9_hwmod, | |
2718 | .clk = "gpt9_ick", | |
2719 | .addr = omap3xxx_timer9_addrs, | |
2720 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
0f9dfdd3 FC |
2721 | }; |
2722 | ||
844a3b63 PW |
2723 | /* l4_core -> timer10 */ |
2724 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer10 = { | |
2725 | .master = &omap3xxx_l4_core_hwmod, | |
2726 | .slave = &omap3xxx_timer10_hwmod, | |
2727 | .clk = "gpt10_ick", | |
2728 | .addr = omap2_timer10_addrs, | |
2729 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
0f9dfdd3 FC |
2730 | }; |
2731 | ||
844a3b63 PW |
2732 | /* l4_core -> timer11 */ |
2733 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer11 = { | |
2734 | .master = &omap3xxx_l4_core_hwmod, | |
2735 | .slave = &omap3xxx_timer11_hwmod, | |
2736 | .clk = "gpt11_ick", | |
2737 | .addr = omap2_timer11_addrs, | |
2738 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
0f9dfdd3 FC |
2739 | }; |
2740 | ||
844a3b63 | 2741 | static struct omap_hwmod_addr_space omap3xxx_timer12_addrs[] = { |
0f9dfdd3 | 2742 | { |
844a3b63 PW |
2743 | .pa_start = 0x48304000, |
2744 | .pa_end = 0x48304000 + SZ_1K - 1, | |
2745 | .flags = ADDR_TYPE_RT | |
0f9dfdd3 | 2746 | }, |
78183f3f | 2747 | { } |
0f9dfdd3 FC |
2748 | }; |
2749 | ||
844a3b63 PW |
2750 | /* l4_core -> timer12 */ |
2751 | static struct omap_hwmod_ocp_if omap3xxx_l4_sec__timer12 = { | |
2752 | .master = &omap3xxx_l4_sec_hwmod, | |
2753 | .slave = &omap3xxx_timer12_hwmod, | |
2754 | .clk = "gpt12_ick", | |
2755 | .addr = omap3xxx_timer12_addrs, | |
0f9dfdd3 FC |
2756 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
2757 | }; | |
2758 | ||
844a3b63 PW |
2759 | /* l4_wkup -> wd_timer2 */ |
2760 | static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs[] = { | |
2761 | { | |
2762 | .pa_start = 0x48314000, | |
2763 | .pa_end = 0x4831407f, | |
2764 | .flags = ADDR_TYPE_RT | |
0f9dfdd3 | 2765 | }, |
844a3b63 | 2766 | { } |
0f9dfdd3 FC |
2767 | }; |
2768 | ||
844a3b63 PW |
2769 | static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = { |
2770 | .master = &omap3xxx_l4_wkup_hwmod, | |
2771 | .slave = &omap3xxx_wd_timer2_hwmod, | |
2772 | .clk = "wdt2_ick", | |
2773 | .addr = omap3xxx_wd_timer2_addrs, | |
2774 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2775 | }; | |
2776 | ||
2777 | /* l4_core -> dss */ | |
2778 | static struct omap_hwmod_ocp_if omap3430es1_l4_core__dss = { | |
0f616a4e | 2779 | .master = &omap3xxx_l4_core_hwmod, |
844a3b63 PW |
2780 | .slave = &omap3430es1_dss_core_hwmod, |
2781 | .clk = "dss_ick", | |
2782 | .addr = omap2_dss_addrs, | |
2783 | .fw = { | |
2784 | .omap2 = { | |
2785 | .l4_fw_region = OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION, | |
2786 | .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, | |
2787 | .flags = OMAP_FIREWALL_L4, | |
2788 | } | |
2789 | }, | |
0f616a4e C |
2790 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
2791 | }; | |
2792 | ||
844a3b63 | 2793 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss = { |
0f616a4e | 2794 | .master = &omap3xxx_l4_core_hwmod, |
844a3b63 PW |
2795 | .slave = &omap3xxx_dss_core_hwmod, |
2796 | .clk = "dss_ick", | |
2797 | .addr = omap2_dss_addrs, | |
2798 | .fw = { | |
2799 | .omap2 = { | |
2800 | .l4_fw_region = OMAP3_L4_CORE_FW_DSS_CORE_REGION, | |
2801 | .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, | |
2802 | .flags = OMAP_FIREWALL_L4, | |
2803 | } | |
2804 | }, | |
0f616a4e C |
2805 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
2806 | }; | |
2807 | ||
844a3b63 PW |
2808 | /* l4_core -> dss_dispc */ |
2809 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = { | |
0f616a4e | 2810 | .master = &omap3xxx_l4_core_hwmod, |
844a3b63 PW |
2811 | .slave = &omap3xxx_dss_dispc_hwmod, |
2812 | .clk = "dss_ick", | |
2813 | .addr = omap2_dss_dispc_addrs, | |
2814 | .fw = { | |
2815 | .omap2 = { | |
2816 | .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DISPC_REGION, | |
2817 | .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, | |
2818 | .flags = OMAP_FIREWALL_L4, | |
2819 | } | |
2820 | }, | |
0f616a4e C |
2821 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
2822 | }; | |
2823 | ||
844a3b63 | 2824 | static struct omap_hwmod_addr_space omap3xxx_dss_dsi1_addrs[] = { |
0f616a4e | 2825 | { |
844a3b63 PW |
2826 | .pa_start = 0x4804FC00, |
2827 | .pa_end = 0x4804FFFF, | |
2828 | .flags = ADDR_TYPE_RT | |
0f616a4e | 2829 | }, |
78183f3f | 2830 | { } |
0f616a4e C |
2831 | }; |
2832 | ||
844a3b63 PW |
2833 | /* l4_core -> dss_dsi1 */ |
2834 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dsi1 = { | |
0f616a4e | 2835 | .master = &omap3xxx_l4_core_hwmod, |
844a3b63 PW |
2836 | .slave = &omap3xxx_dss_dsi1_hwmod, |
2837 | .clk = "dss_ick", | |
2838 | .addr = omap3xxx_dss_dsi1_addrs, | |
2839 | .fw = { | |
2840 | .omap2 = { | |
2841 | .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DSI_REGION, | |
2842 | .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, | |
2843 | .flags = OMAP_FIREWALL_L4, | |
2844 | } | |
2845 | }, | |
0f616a4e C |
2846 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
2847 | }; | |
2848 | ||
844a3b63 PW |
2849 | /* l4_core -> dss_rfbi */ |
2850 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_rfbi = { | |
2851 | .master = &omap3xxx_l4_core_hwmod, | |
2852 | .slave = &omap3xxx_dss_rfbi_hwmod, | |
2853 | .clk = "dss_ick", | |
2854 | .addr = omap2_dss_rfbi_addrs, | |
2855 | .fw = { | |
0f616a4e | 2856 | .omap2 = { |
844a3b63 PW |
2857 | .l4_fw_region = OMAP3_L4_CORE_FW_DSS_RFBI_REGION, |
2858 | .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP , | |
2859 | .flags = OMAP_FIREWALL_L4, | |
2860 | } | |
0f616a4e | 2861 | }, |
844a3b63 | 2862 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
0f616a4e C |
2863 | }; |
2864 | ||
844a3b63 PW |
2865 | /* l4_core -> dss_venc */ |
2866 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = { | |
2867 | .master = &omap3xxx_l4_core_hwmod, | |
2868 | .slave = &omap3xxx_dss_venc_hwmod, | |
2869 | .clk = "dss_ick", | |
2870 | .addr = omap2_dss_venc_addrs, | |
2871 | .fw = { | |
70034d38 | 2872 | .omap2 = { |
844a3b63 PW |
2873 | .l4_fw_region = OMAP3_L4_CORE_FW_DSS_VENC_REGION, |
2874 | .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, | |
2875 | .flags = OMAP_FIREWALL_L4, | |
2876 | } | |
70034d38 | 2877 | }, |
844a3b63 PW |
2878 | .flags = OCPIF_SWSUP_IDLE, |
2879 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
70034d38 VC |
2880 | }; |
2881 | ||
844a3b63 PW |
2882 | /* l4_wkup -> gpio1 */ |
2883 | static struct omap_hwmod_addr_space omap3xxx_gpio1_addrs[] = { | |
2884 | { | |
2885 | .pa_start = 0x48310000, | |
2886 | .pa_end = 0x483101ff, | |
2887 | .flags = ADDR_TYPE_RT | |
2888 | }, | |
2889 | { } | |
70034d38 VC |
2890 | }; |
2891 | ||
844a3b63 PW |
2892 | static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gpio1 = { |
2893 | .master = &omap3xxx_l4_wkup_hwmod, | |
2894 | .slave = &omap3xxx_gpio1_hwmod, | |
2895 | .addr = omap3xxx_gpio1_addrs, | |
2896 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
0f616a4e C |
2897 | }; |
2898 | ||
844a3b63 PW |
2899 | /* l4_per -> gpio2 */ |
2900 | static struct omap_hwmod_addr_space omap3xxx_gpio2_addrs[] = { | |
2901 | { | |
2902 | .pa_start = 0x49050000, | |
2903 | .pa_end = 0x490501ff, | |
2904 | .flags = ADDR_TYPE_RT | |
70034d38 | 2905 | }, |
844a3b63 | 2906 | { } |
70034d38 VC |
2907 | }; |
2908 | ||
844a3b63 PW |
2909 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio2 = { |
2910 | .master = &omap3xxx_l4_per_hwmod, | |
2911 | .slave = &omap3xxx_gpio2_hwmod, | |
2912 | .addr = omap3xxx_gpio2_addrs, | |
2913 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
70034d38 VC |
2914 | }; |
2915 | ||
844a3b63 PW |
2916 | /* l4_per -> gpio3 */ |
2917 | static struct omap_hwmod_addr_space omap3xxx_gpio3_addrs[] = { | |
2918 | { | |
2919 | .pa_start = 0x49052000, | |
2920 | .pa_end = 0x490521ff, | |
2921 | .flags = ADDR_TYPE_RT | |
2922 | }, | |
2923 | { } | |
70034d38 VC |
2924 | }; |
2925 | ||
844a3b63 PW |
2926 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = { |
2927 | .master = &omap3xxx_l4_per_hwmod, | |
2928 | .slave = &omap3xxx_gpio3_hwmod, | |
2929 | .addr = omap3xxx_gpio3_addrs, | |
2930 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
0f616a4e C |
2931 | }; |
2932 | ||
5486474c PW |
2933 | /* |
2934 | * 'mmu' class | |
2935 | * The memory management unit performs virtual to physical address translation | |
2936 | * for its requestors. | |
2937 | */ | |
2938 | ||
2939 | static struct omap_hwmod_class_sysconfig mmu_sysc = { | |
2940 | .rev_offs = 0x000, | |
2941 | .sysc_offs = 0x010, | |
2942 | .syss_offs = 0x014, | |
2943 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | | |
2944 | SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), | |
2945 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
2946 | .sysc_fields = &omap_hwmod_sysc_type1, | |
2947 | }; | |
2948 | ||
2949 | static struct omap_hwmod_class omap3xxx_mmu_hwmod_class = { | |
2950 | .name = "mmu", | |
2951 | .sysc = &mmu_sysc, | |
2952 | }; | |
2953 | ||
2954 | /* mmu isp */ | |
5486474c | 2955 | static struct omap_hwmod omap3xxx_mmu_isp_hwmod; |
5486474c PW |
2956 | |
2957 | /* l4_core -> mmu isp */ | |
2958 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmu_isp = { | |
2959 | .master = &omap3xxx_l4_core_hwmod, | |
2960 | .slave = &omap3xxx_mmu_isp_hwmod, | |
5486474c PW |
2961 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
2962 | }; | |
2963 | ||
2964 | static struct omap_hwmod omap3xxx_mmu_isp_hwmod = { | |
2965 | .name = "mmu_isp", | |
2966 | .class = &omap3xxx_mmu_hwmod_class, | |
5486474c | 2967 | .main_clk = "cam_ick", |
5486474c PW |
2968 | .flags = HWMOD_NO_IDLEST, |
2969 | }; | |
2970 | ||
5486474c PW |
2971 | /* mmu iva */ |
2972 | ||
5486474c | 2973 | static struct omap_hwmod omap3xxx_mmu_iva_hwmod; |
5486474c PW |
2974 | |
2975 | static struct omap_hwmod_rst_info omap3xxx_mmu_iva_resets[] = { | |
2976 | { .name = "mmu", .rst_shift = 1, .st_shift = 9 }, | |
2977 | }; | |
2978 | ||
5486474c PW |
2979 | /* l3_main -> iva mmu */ |
2980 | static struct omap_hwmod_ocp_if omap3xxx_l3_main__mmu_iva = { | |
2981 | .master = &omap3xxx_l3_main_hwmod, | |
2982 | .slave = &omap3xxx_mmu_iva_hwmod, | |
5486474c PW |
2983 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
2984 | }; | |
2985 | ||
2986 | static struct omap_hwmod omap3xxx_mmu_iva_hwmod = { | |
2987 | .name = "mmu_iva", | |
2988 | .class = &omap3xxx_mmu_hwmod_class, | |
200a274f | 2989 | .clkdm_name = "iva2_clkdm", |
5486474c PW |
2990 | .rst_lines = omap3xxx_mmu_iva_resets, |
2991 | .rst_lines_cnt = ARRAY_SIZE(omap3xxx_mmu_iva_resets), | |
2992 | .main_clk = "iva2_ck", | |
2993 | .prcm = { | |
2994 | .omap2 = { | |
2995 | .module_offs = OMAP3430_IVA2_MOD, | |
200a274f SA |
2996 | .module_bit = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT, |
2997 | .idlest_reg_id = 1, | |
2998 | .idlest_idle_bit = OMAP3430_ST_IVA2_SHIFT, | |
5486474c PW |
2999 | }, |
3000 | }, | |
5486474c PW |
3001 | .flags = HWMOD_NO_IDLEST, |
3002 | }; | |
3003 | ||
844a3b63 PW |
3004 | /* l4_per -> gpio4 */ |
3005 | static struct omap_hwmod_addr_space omap3xxx_gpio4_addrs[] = { | |
3006 | { | |
3007 | .pa_start = 0x49054000, | |
3008 | .pa_end = 0x490541ff, | |
3009 | .flags = ADDR_TYPE_RT | |
70034d38 | 3010 | }, |
844a3b63 | 3011 | { } |
70034d38 VC |
3012 | }; |
3013 | ||
844a3b63 PW |
3014 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio4 = { |
3015 | .master = &omap3xxx_l4_per_hwmod, | |
3016 | .slave = &omap3xxx_gpio4_hwmod, | |
3017 | .addr = omap3xxx_gpio4_addrs, | |
3018 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
01438ab6 MK |
3019 | }; |
3020 | ||
844a3b63 PW |
3021 | /* l4_per -> gpio5 */ |
3022 | static struct omap_hwmod_addr_space omap3xxx_gpio5_addrs[] = { | |
3023 | { | |
3024 | .pa_start = 0x49056000, | |
3025 | .pa_end = 0x490561ff, | |
3026 | .flags = ADDR_TYPE_RT | |
3027 | }, | |
3028 | { } | |
01438ab6 MK |
3029 | }; |
3030 | ||
844a3b63 PW |
3031 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio5 = { |
3032 | .master = &omap3xxx_l4_per_hwmod, | |
3033 | .slave = &omap3xxx_gpio5_hwmod, | |
3034 | .addr = omap3xxx_gpio5_addrs, | |
3035 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
01438ab6 MK |
3036 | }; |
3037 | ||
844a3b63 PW |
3038 | /* l4_per -> gpio6 */ |
3039 | static struct omap_hwmod_addr_space omap3xxx_gpio6_addrs[] = { | |
3040 | { | |
3041 | .pa_start = 0x49058000, | |
3042 | .pa_end = 0x490581ff, | |
3043 | .flags = ADDR_TYPE_RT | |
01438ab6 | 3044 | }, |
844a3b63 | 3045 | { } |
01438ab6 MK |
3046 | }; |
3047 | ||
844a3b63 PW |
3048 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6 = { |
3049 | .master = &omap3xxx_l4_per_hwmod, | |
3050 | .slave = &omap3xxx_gpio6_hwmod, | |
3051 | .addr = omap3xxx_gpio6_addrs, | |
3052 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
01438ab6 MK |
3053 | }; |
3054 | ||
844a3b63 PW |
3055 | /* dma_system -> L3 */ |
3056 | static struct omap_hwmod_ocp_if omap3xxx_dma_system__l3 = { | |
3057 | .master = &omap3xxx_dma_system_hwmod, | |
3058 | .slave = &omap3xxx_l3_main_hwmod, | |
3059 | .clk = "core_l3_ick", | |
3060 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
01438ab6 MK |
3061 | }; |
3062 | ||
844a3b63 PW |
3063 | static struct omap_hwmod_addr_space omap3xxx_dma_system_addrs[] = { |
3064 | { | |
3065 | .pa_start = 0x48056000, | |
3066 | .pa_end = 0x48056fff, | |
3067 | .flags = ADDR_TYPE_RT | |
01438ab6 | 3068 | }, |
844a3b63 | 3069 | { } |
01438ab6 MK |
3070 | }; |
3071 | ||
844a3b63 PW |
3072 | /* l4_cfg -> dma_system */ |
3073 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__dma_system = { | |
3074 | .master = &omap3xxx_l4_core_hwmod, | |
3075 | .slave = &omap3xxx_dma_system_hwmod, | |
3076 | .clk = "core_l4_ick", | |
3077 | .addr = omap3xxx_dma_system_addrs, | |
3078 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
d3442726 TG |
3079 | }; |
3080 | ||
844a3b63 PW |
3081 | static struct omap_hwmod_addr_space omap3xxx_mcbsp1_addrs[] = { |
3082 | { | |
3083 | .name = "mpu", | |
3084 | .pa_start = 0x48074000, | |
3085 | .pa_end = 0x480740ff, | |
3086 | .flags = ADDR_TYPE_RT | |
3087 | }, | |
3088 | { } | |
d3442726 TG |
3089 | }; |
3090 | ||
844a3b63 PW |
3091 | /* l4_core -> mcbsp1 */ |
3092 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp1 = { | |
3093 | .master = &omap3xxx_l4_core_hwmod, | |
3094 | .slave = &omap3xxx_mcbsp1_hwmod, | |
3095 | .clk = "mcbsp1_ick", | |
3096 | .addr = omap3xxx_mcbsp1_addrs, | |
3097 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
d3442726 TG |
3098 | }; |
3099 | ||
844a3b63 PW |
3100 | static struct omap_hwmod_addr_space omap3xxx_mcbsp2_addrs[] = { |
3101 | { | |
3102 | .name = "mpu", | |
3103 | .pa_start = 0x49022000, | |
3104 | .pa_end = 0x490220ff, | |
3105 | .flags = ADDR_TYPE_RT | |
3106 | }, | |
3107 | { } | |
d3442726 TG |
3108 | }; |
3109 | ||
844a3b63 PW |
3110 | /* l4_per -> mcbsp2 */ |
3111 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2 = { | |
3112 | .master = &omap3xxx_l4_per_hwmod, | |
3113 | .slave = &omap3xxx_mcbsp2_hwmod, | |
3114 | .clk = "mcbsp2_ick", | |
3115 | .addr = omap3xxx_mcbsp2_addrs, | |
3116 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
d3442726 TG |
3117 | }; |
3118 | ||
844a3b63 PW |
3119 | static struct omap_hwmod_addr_space omap3xxx_mcbsp3_addrs[] = { |
3120 | { | |
3121 | .name = "mpu", | |
3122 | .pa_start = 0x49024000, | |
3123 | .pa_end = 0x490240ff, | |
3124 | .flags = ADDR_TYPE_RT | |
3125 | }, | |
3126 | { } | |
d3442726 TG |
3127 | }; |
3128 | ||
844a3b63 PW |
3129 | /* l4_per -> mcbsp3 */ |
3130 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3 = { | |
3131 | .master = &omap3xxx_l4_per_hwmod, | |
3132 | .slave = &omap3xxx_mcbsp3_hwmod, | |
3133 | .clk = "mcbsp3_ick", | |
3134 | .addr = omap3xxx_mcbsp3_addrs, | |
3135 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
a52e2ab6 PW |
3136 | }; |
3137 | ||
844a3b63 PW |
3138 | static struct omap_hwmod_addr_space omap3xxx_mcbsp4_addrs[] = { |
3139 | { | |
3140 | .name = "mpu", | |
3141 | .pa_start = 0x49026000, | |
3142 | .pa_end = 0x490260ff, | |
3143 | .flags = ADDR_TYPE_RT | |
a52e2ab6 | 3144 | }, |
844a3b63 | 3145 | { } |
a52e2ab6 PW |
3146 | }; |
3147 | ||
844a3b63 PW |
3148 | /* l4_per -> mcbsp4 */ |
3149 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp4 = { | |
3150 | .master = &omap3xxx_l4_per_hwmod, | |
3151 | .slave = &omap3xxx_mcbsp4_hwmod, | |
3152 | .clk = "mcbsp4_ick", | |
3153 | .addr = omap3xxx_mcbsp4_addrs, | |
3154 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
d3442726 TG |
3155 | }; |
3156 | ||
844a3b63 PW |
3157 | static struct omap_hwmod_addr_space omap3xxx_mcbsp5_addrs[] = { |
3158 | { | |
3159 | .name = "mpu", | |
3160 | .pa_start = 0x48096000, | |
3161 | .pa_end = 0x480960ff, | |
3162 | .flags = ADDR_TYPE_RT | |
3163 | }, | |
3164 | { } | |
3165 | }; | |
b163605e | 3166 | |
844a3b63 PW |
3167 | /* l4_core -> mcbsp5 */ |
3168 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp5 = { | |
3169 | .master = &omap3xxx_l4_core_hwmod, | |
3170 | .slave = &omap3xxx_mcbsp5_hwmod, | |
3171 | .clk = "mcbsp5_ick", | |
3172 | .addr = omap3xxx_mcbsp5_addrs, | |
3173 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
d3442726 TG |
3174 | }; |
3175 | ||
844a3b63 PW |
3176 | static struct omap_hwmod_addr_space omap3xxx_mcbsp2_sidetone_addrs[] = { |
3177 | { | |
3178 | .name = "sidetone", | |
3179 | .pa_start = 0x49028000, | |
3180 | .pa_end = 0x490280ff, | |
3181 | .flags = ADDR_TYPE_RT | |
3182 | }, | |
3183 | { } | |
d3442726 TG |
3184 | }; |
3185 | ||
844a3b63 PW |
3186 | /* l4_per -> mcbsp2_sidetone */ |
3187 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2_sidetone = { | |
3188 | .master = &omap3xxx_l4_per_hwmod, | |
3189 | .slave = &omap3xxx_mcbsp2_sidetone_hwmod, | |
3190 | .clk = "mcbsp2_ick", | |
3191 | .addr = omap3xxx_mcbsp2_sidetone_addrs, | |
3192 | .user = OCP_USER_MPU, | |
b163605e PW |
3193 | }; |
3194 | ||
844a3b63 PW |
3195 | static struct omap_hwmod_addr_space omap3xxx_mcbsp3_sidetone_addrs[] = { |
3196 | { | |
3197 | .name = "sidetone", | |
3198 | .pa_start = 0x4902A000, | |
3199 | .pa_end = 0x4902A0ff, | |
3200 | .flags = ADDR_TYPE_RT | |
3201 | }, | |
3202 | { } | |
a52e2ab6 PW |
3203 | }; |
3204 | ||
844a3b63 PW |
3205 | /* l4_per -> mcbsp3_sidetone */ |
3206 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3_sidetone = { | |
3207 | .master = &omap3xxx_l4_per_hwmod, | |
3208 | .slave = &omap3xxx_mcbsp3_sidetone_hwmod, | |
3209 | .clk = "mcbsp3_ick", | |
3210 | .addr = omap3xxx_mcbsp3_sidetone_addrs, | |
3211 | .user = OCP_USER_MPU, | |
a52e2ab6 PW |
3212 | }; |
3213 | ||
844a3b63 PW |
3214 | /* l4_core -> mailbox */ |
3215 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__mailbox = { | |
3216 | .master = &omap3xxx_l4_core_hwmod, | |
3217 | .slave = &omap3xxx_mailbox_hwmod, | |
844a3b63 PW |
3218 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
3219 | }; | |
b163605e | 3220 | |
844a3b63 PW |
3221 | /* l4 core -> mcspi1 interface */ |
3222 | static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi1 = { | |
3223 | .master = &omap3xxx_l4_core_hwmod, | |
3224 | .slave = &omap34xx_mcspi1, | |
3225 | .clk = "mcspi1_ick", | |
3226 | .addr = omap2_mcspi1_addr_space, | |
3227 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
b163605e PW |
3228 | }; |
3229 | ||
844a3b63 PW |
3230 | /* l4 core -> mcspi2 interface */ |
3231 | static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi2 = { | |
3232 | .master = &omap3xxx_l4_core_hwmod, | |
3233 | .slave = &omap34xx_mcspi2, | |
3234 | .clk = "mcspi2_ick", | |
3235 | .addr = omap2_mcspi2_addr_space, | |
3236 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
b163605e PW |
3237 | }; |
3238 | ||
844a3b63 PW |
3239 | /* l4 core -> mcspi3 interface */ |
3240 | static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi3 = { | |
3241 | .master = &omap3xxx_l4_core_hwmod, | |
3242 | .slave = &omap34xx_mcspi3, | |
3243 | .clk = "mcspi3_ick", | |
3244 | .addr = omap2430_mcspi3_addr_space, | |
3245 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
b163605e PW |
3246 | }; |
3247 | ||
844a3b63 PW |
3248 | /* l4 core -> mcspi4 interface */ |
3249 | static struct omap_hwmod_addr_space omap34xx_mcspi4_addr_space[] = { | |
3250 | { | |
3251 | .pa_start = 0x480ba000, | |
3252 | .pa_end = 0x480ba0ff, | |
3253 | .flags = ADDR_TYPE_RT, | |
d3442726 | 3254 | }, |
844a3b63 PW |
3255 | { } |
3256 | }; | |
3257 | ||
3258 | static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4 = { | |
3259 | .master = &omap3xxx_l4_core_hwmod, | |
3260 | .slave = &omap34xx_mcspi4, | |
3261 | .clk = "mcspi4_ick", | |
3262 | .addr = omap34xx_mcspi4_addr_space, | |
3263 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
d3442726 TG |
3264 | }; |
3265 | ||
de231388 KM |
3266 | static struct omap_hwmod_ocp_if omap3xxx_usb_host_hs__l3_main_2 = { |
3267 | .master = &omap3xxx_usb_host_hs_hwmod, | |
3268 | .slave = &omap3xxx_l3_main_hwmod, | |
3269 | .clk = "core_l3_ick", | |
3270 | .user = OCP_USER_MPU, | |
3271 | }; | |
3272 | ||
de231388 KM |
3273 | static struct omap_hwmod_addr_space omap3xxx_usb_host_hs_addrs[] = { |
3274 | { | |
3275 | .name = "uhh", | |
3276 | .pa_start = 0x48064000, | |
3277 | .pa_end = 0x480643ff, | |
3278 | .flags = ADDR_TYPE_RT | |
3279 | }, | |
3280 | { | |
3281 | .name = "ohci", | |
3282 | .pa_start = 0x48064400, | |
3283 | .pa_end = 0x480647ff, | |
3284 | }, | |
3285 | { | |
3286 | .name = "ehci", | |
3287 | .pa_start = 0x48064800, | |
3288 | .pa_end = 0x48064cff, | |
3289 | }, | |
3290 | {} | |
3291 | }; | |
3292 | ||
3293 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_host_hs = { | |
3294 | .master = &omap3xxx_l4_core_hwmod, | |
3295 | .slave = &omap3xxx_usb_host_hs_hwmod, | |
3296 | .clk = "usbhost_ick", | |
3297 | .addr = omap3xxx_usb_host_hs_addrs, | |
3298 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3299 | }; | |
3300 | ||
de231388 KM |
3301 | static struct omap_hwmod_addr_space omap3xxx_usb_tll_hs_addrs[] = { |
3302 | { | |
3303 | .name = "tll", | |
3304 | .pa_start = 0x48062000, | |
3305 | .pa_end = 0x48062fff, | |
3306 | .flags = ADDR_TYPE_RT | |
3307 | }, | |
3308 | {} | |
3309 | }; | |
3310 | ||
3311 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_tll_hs = { | |
3312 | .master = &omap3xxx_l4_core_hwmod, | |
3313 | .slave = &omap3xxx_usb_tll_hs_hwmod, | |
3314 | .clk = "usbtll_ick", | |
3315 | .addr = omap3xxx_usb_tll_hs_addrs, | |
3316 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3317 | }; | |
3318 | ||
45a4bb06 PW |
3319 | /* l4_core -> hdq1w interface */ |
3320 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__hdq1w = { | |
3321 | .master = &omap3xxx_l4_core_hwmod, | |
3322 | .slave = &omap3xxx_hdq1w_hwmod, | |
3323 | .clk = "hdq_ick", | |
3324 | .addr = omap2_hdq1w_addr_space, | |
3325 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3326 | .flags = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE, | |
3327 | }; | |
3328 | ||
c8d82ff6 VH |
3329 | /* l4_wkup -> 32ksync_counter */ |
3330 | static struct omap_hwmod_addr_space omap3xxx_counter_32k_addrs[] = { | |
3331 | { | |
3332 | .pa_start = 0x48320000, | |
3333 | .pa_end = 0x4832001f, | |
3334 | .flags = ADDR_TYPE_RT | |
3335 | }, | |
3336 | { } | |
3337 | }; | |
3338 | ||
49484a60 AM |
3339 | static struct omap_hwmod_addr_space omap3xxx_gpmc_addrs[] = { |
3340 | { | |
3341 | .pa_start = 0x6e000000, | |
3342 | .pa_end = 0x6e000fff, | |
3343 | .flags = ADDR_TYPE_RT | |
3344 | }, | |
3345 | { } | |
3346 | }; | |
3347 | ||
c8d82ff6 VH |
3348 | static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__counter_32k = { |
3349 | .master = &omap3xxx_l4_wkup_hwmod, | |
3350 | .slave = &omap3xxx_counter_32k_hwmod, | |
3351 | .clk = "omap_32ksync_ick", | |
3352 | .addr = omap3xxx_counter_32k_addrs, | |
3353 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3354 | }; | |
3355 | ||
31ba8808 MG |
3356 | /* am35xx has Davinci MDIO & EMAC */ |
3357 | static struct omap_hwmod_class am35xx_mdio_class = { | |
3358 | .name = "davinci_mdio", | |
3359 | }; | |
3360 | ||
3361 | static struct omap_hwmod am35xx_mdio_hwmod = { | |
3362 | .name = "davinci_mdio", | |
3363 | .class = &am35xx_mdio_class, | |
3364 | .flags = HWMOD_NO_IDLEST, | |
3365 | }; | |
3366 | ||
3367 | /* | |
3368 | * XXX Should be connected to an IPSS hwmod, not the L3 directly; | |
3369 | * but this will probably require some additional hwmod core support, | |
3370 | * so is left as a future to-do item. | |
3371 | */ | |
3372 | static struct omap_hwmod_ocp_if am35xx_mdio__l3 = { | |
3373 | .master = &am35xx_mdio_hwmod, | |
3374 | .slave = &omap3xxx_l3_main_hwmod, | |
3375 | .clk = "emac_fck", | |
3376 | .user = OCP_USER_MPU, | |
3377 | }; | |
3378 | ||
31ba8808 MG |
3379 | /* l4_core -> davinci mdio */ |
3380 | /* | |
3381 | * XXX Should be connected to an IPSS hwmod, not the L4_CORE directly; | |
3382 | * but this will probably require some additional hwmod core support, | |
3383 | * so is left as a future to-do item. | |
3384 | */ | |
3385 | static struct omap_hwmod_ocp_if am35xx_l4_core__mdio = { | |
3386 | .master = &omap3xxx_l4_core_hwmod, | |
3387 | .slave = &am35xx_mdio_hwmod, | |
3388 | .clk = "emac_fck", | |
31ba8808 MG |
3389 | .user = OCP_USER_MPU, |
3390 | }; | |
3391 | ||
31ba8808 MG |
3392 | static struct omap_hwmod_class am35xx_emac_class = { |
3393 | .name = "davinci_emac", | |
3394 | }; | |
3395 | ||
3396 | static struct omap_hwmod am35xx_emac_hwmod = { | |
3397 | .name = "davinci_emac", | |
31ba8808 | 3398 | .class = &am35xx_emac_class, |
814a18a5 PW |
3399 | /* |
3400 | * According to Mark Greer, the MPU will not return from WFI | |
3401 | * when the EMAC signals an interrupt. | |
3402 | * http://www.spinics.net/lists/arm-kernel/msg174734.html | |
3403 | */ | |
3404 | .flags = (HWMOD_NO_IDLEST | HWMOD_BLOCK_WFI), | |
31ba8808 MG |
3405 | }; |
3406 | ||
3407 | /* l3_core -> davinci emac interface */ | |
3408 | /* | |
3409 | * XXX Should be connected to an IPSS hwmod, not the L3 directly; | |
3410 | * but this will probably require some additional hwmod core support, | |
3411 | * so is left as a future to-do item. | |
3412 | */ | |
3413 | static struct omap_hwmod_ocp_if am35xx_emac__l3 = { | |
3414 | .master = &am35xx_emac_hwmod, | |
3415 | .slave = &omap3xxx_l3_main_hwmod, | |
3416 | .clk = "emac_ick", | |
3417 | .user = OCP_USER_MPU, | |
3418 | }; | |
3419 | ||
31ba8808 MG |
3420 | /* l4_core -> davinci emac */ |
3421 | /* | |
3422 | * XXX Should be connected to an IPSS hwmod, not the L4_CORE directly; | |
3423 | * but this will probably require some additional hwmod core support, | |
3424 | * so is left as a future to-do item. | |
3425 | */ | |
3426 | static struct omap_hwmod_ocp_if am35xx_l4_core__emac = { | |
3427 | .master = &omap3xxx_l4_core_hwmod, | |
3428 | .slave = &am35xx_emac_hwmod, | |
3429 | .clk = "emac_ick", | |
31ba8808 MG |
3430 | .user = OCP_USER_MPU, |
3431 | }; | |
3432 | ||
49484a60 AM |
3433 | static struct omap_hwmod_ocp_if omap3xxx_l3_main__gpmc = { |
3434 | .master = &omap3xxx_l3_main_hwmod, | |
3435 | .slave = &omap3xxx_gpmc_hwmod, | |
3436 | .clk = "core_l3_ick", | |
3437 | .addr = omap3xxx_gpmc_addrs, | |
3438 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3439 | }; | |
3440 | ||
26f88e6e MG |
3441 | /* l4_core -> SHAM2 (SHA1/MD5) (similar to omap24xx) */ |
3442 | static struct omap_hwmod_sysc_fields omap3_sham_sysc_fields = { | |
3443 | .sidle_shift = 4, | |
3444 | .srst_shift = 1, | |
3445 | .autoidle_shift = 0, | |
3446 | }; | |
3447 | ||
3448 | static struct omap_hwmod_class_sysconfig omap3_sham_sysc = { | |
3449 | .rev_offs = 0x5c, | |
3450 | .sysc_offs = 0x60, | |
3451 | .syss_offs = 0x64, | |
3452 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | | |
3453 | SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), | |
3454 | .sysc_fields = &omap3_sham_sysc_fields, | |
3455 | }; | |
3456 | ||
3457 | static struct omap_hwmod_class omap3xxx_sham_class = { | |
3458 | .name = "sham", | |
3459 | .sysc = &omap3_sham_sysc, | |
3460 | }; | |
3461 | ||
3462 | static struct omap_hwmod_irq_info omap3_sham_mpu_irqs[] = { | |
3463 | { .irq = 49 + OMAP_INTC_START, }, | |
3464 | { .irq = -1 } | |
3465 | }; | |
3466 | ||
3467 | static struct omap_hwmod_dma_info omap3_sham_sdma_reqs[] = { | |
0fd8824f | 3468 | { .name = "rx", .dma_req = 69, }, |
26f88e6e MG |
3469 | { .dma_req = -1 } |
3470 | }; | |
3471 | ||
3472 | static struct omap_hwmod omap3xxx_sham_hwmod = { | |
3473 | .name = "sham", | |
3474 | .mpu_irqs = omap3_sham_mpu_irqs, | |
3475 | .sdma_reqs = omap3_sham_sdma_reqs, | |
3476 | .main_clk = "sha12_ick", | |
3477 | .prcm = { | |
3478 | .omap2 = { | |
3479 | .module_offs = CORE_MOD, | |
3480 | .prcm_reg_id = 1, | |
3481 | .module_bit = OMAP3430_EN_SHA12_SHIFT, | |
3482 | .idlest_reg_id = 1, | |
3483 | .idlest_idle_bit = OMAP3430_ST_SHA12_SHIFT, | |
3484 | }, | |
3485 | }, | |
3486 | .class = &omap3xxx_sham_class, | |
3487 | }; | |
3488 | ||
3489 | static struct omap_hwmod_addr_space omap3xxx_sham_addrs[] = { | |
3490 | { | |
3491 | .pa_start = 0x480c3000, | |
3492 | .pa_end = 0x480c3000 + 0x64 - 1, | |
3493 | .flags = ADDR_TYPE_RT | |
3494 | }, | |
3495 | { } | |
3496 | }; | |
3497 | ||
3498 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__sham = { | |
3499 | .master = &omap3xxx_l4_core_hwmod, | |
3500 | .slave = &omap3xxx_sham_hwmod, | |
3501 | .clk = "sha12_ick", | |
3502 | .addr = omap3xxx_sham_addrs, | |
3503 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3504 | }; | |
3505 | ||
14ae5564 MG |
3506 | /* l4_core -> AES */ |
3507 | static struct omap_hwmod_sysc_fields omap3xxx_aes_sysc_fields = { | |
3508 | .sidle_shift = 6, | |
3509 | .srst_shift = 1, | |
3510 | .autoidle_shift = 0, | |
3511 | }; | |
3512 | ||
3513 | static struct omap_hwmod_class_sysconfig omap3_aes_sysc = { | |
3514 | .rev_offs = 0x44, | |
3515 | .sysc_offs = 0x48, | |
3516 | .syss_offs = 0x4c, | |
3517 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | | |
3518 | SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), | |
3519 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
3520 | .sysc_fields = &omap3xxx_aes_sysc_fields, | |
3521 | }; | |
3522 | ||
3523 | static struct omap_hwmod_class omap3xxx_aes_class = { | |
3524 | .name = "aes", | |
3525 | .sysc = &omap3_aes_sysc, | |
3526 | }; | |
3527 | ||
3528 | static struct omap_hwmod_dma_info omap3_aes_sdma_reqs[] = { | |
0fd8824f JN |
3529 | { .name = "tx", .dma_req = 65, }, |
3530 | { .name = "rx", .dma_req = 66, }, | |
14ae5564 MG |
3531 | { .dma_req = -1 } |
3532 | }; | |
3533 | ||
3534 | static struct omap_hwmod omap3xxx_aes_hwmod = { | |
3535 | .name = "aes", | |
3536 | .sdma_reqs = omap3_aes_sdma_reqs, | |
3537 | .main_clk = "aes2_ick", | |
3538 | .prcm = { | |
3539 | .omap2 = { | |
3540 | .module_offs = CORE_MOD, | |
3541 | .prcm_reg_id = 1, | |
3542 | .module_bit = OMAP3430_EN_AES2_SHIFT, | |
3543 | .idlest_reg_id = 1, | |
3544 | .idlest_idle_bit = OMAP3430_ST_AES2_SHIFT, | |
3545 | }, | |
3546 | }, | |
3547 | .class = &omap3xxx_aes_class, | |
3548 | }; | |
3549 | ||
3550 | static struct omap_hwmod_addr_space omap3xxx_aes_addrs[] = { | |
3551 | { | |
3552 | .pa_start = 0x480c5000, | |
3553 | .pa_end = 0x480c5000 + 0x50 - 1, | |
3554 | .flags = ADDR_TYPE_RT | |
3555 | }, | |
3556 | { } | |
3557 | }; | |
3558 | ||
3559 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__aes = { | |
3560 | .master = &omap3xxx_l4_core_hwmod, | |
3561 | .slave = &omap3xxx_aes_hwmod, | |
3562 | .clk = "aes2_ick", | |
3563 | .addr = omap3xxx_aes_addrs, | |
3564 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3565 | }; | |
3566 | ||
398917ce SR |
3567 | /* |
3568 | * 'ssi' class | |
3569 | * synchronous serial interface (multichannel and full-duplex serial if) | |
3570 | */ | |
3571 | ||
3572 | static struct omap_hwmod_class_sysconfig omap34xx_ssi_sysc = { | |
3573 | .rev_offs = 0x0000, | |
3574 | .sysc_offs = 0x0010, | |
3575 | .syss_offs = 0x0014, | |
dc94fabf TL |
3576 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_MIDLEMODE | |
3577 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), | |
3578 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
398917ce SR |
3579 | .sysc_fields = &omap_hwmod_sysc_type1, |
3580 | }; | |
3581 | ||
77112076 | 3582 | static struct omap_hwmod_class omap3xxx_ssi_hwmod_class = { |
398917ce SR |
3583 | .name = "ssi", |
3584 | .sysc = &omap34xx_ssi_sysc, | |
3585 | }; | |
3586 | ||
77112076 | 3587 | static struct omap_hwmod omap3xxx_ssi_hwmod = { |
398917ce | 3588 | .name = "ssi", |
77112076 | 3589 | .class = &omap3xxx_ssi_hwmod_class, |
398917ce SR |
3590 | .clkdm_name = "core_l4_clkdm", |
3591 | .main_clk = "ssi_ssr_fck", | |
3592 | .prcm = { | |
3593 | .omap2 = { | |
3594 | .prcm_reg_id = 1, | |
3595 | .module_bit = OMAP3430_EN_SSI_SHIFT, | |
3596 | .module_offs = CORE_MOD, | |
3597 | .idlest_reg_id = 1, | |
3598 | .idlest_idle_bit = OMAP3430ES2_ST_SSI_IDLE_SHIFT, | |
3599 | }, | |
3600 | }, | |
3601 | }; | |
3602 | ||
3603 | /* L4 CORE -> SSI */ | |
77112076 | 3604 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__ssi = { |
398917ce | 3605 | .master = &omap3xxx_l4_core_hwmod, |
77112076 | 3606 | .slave = &omap3xxx_ssi_hwmod, |
398917ce SR |
3607 | .clk = "ssi_ick", |
3608 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3609 | }; | |
3610 | ||
0a78c5c5 PW |
3611 | static struct omap_hwmod_ocp_if *omap3xxx_hwmod_ocp_ifs[] __initdata = { |
3612 | &omap3xxx_l3_main__l4_core, | |
3613 | &omap3xxx_l3_main__l4_per, | |
3614 | &omap3xxx_mpu__l3_main, | |
c7dad45f | 3615 | &omap3xxx_l3_main__l4_debugss, |
0a78c5c5 PW |
3616 | &omap3xxx_l4_core__l4_wkup, |
3617 | &omap3xxx_l4_core__mmc3, | |
3618 | &omap3_l4_core__uart1, | |
3619 | &omap3_l4_core__uart2, | |
3620 | &omap3_l4_per__uart3, | |
3621 | &omap3_l4_core__i2c1, | |
3622 | &omap3_l4_core__i2c2, | |
3623 | &omap3_l4_core__i2c3, | |
3624 | &omap3xxx_l4_wkup__l4_sec, | |
3625 | &omap3xxx_l4_wkup__timer1, | |
3626 | &omap3xxx_l4_per__timer2, | |
3627 | &omap3xxx_l4_per__timer3, | |
3628 | &omap3xxx_l4_per__timer4, | |
3629 | &omap3xxx_l4_per__timer5, | |
3630 | &omap3xxx_l4_per__timer6, | |
3631 | &omap3xxx_l4_per__timer7, | |
3632 | &omap3xxx_l4_per__timer8, | |
3633 | &omap3xxx_l4_per__timer9, | |
3634 | &omap3xxx_l4_core__timer10, | |
3635 | &omap3xxx_l4_core__timer11, | |
3636 | &omap3xxx_l4_wkup__wd_timer2, | |
3637 | &omap3xxx_l4_wkup__gpio1, | |
3638 | &omap3xxx_l4_per__gpio2, | |
3639 | &omap3xxx_l4_per__gpio3, | |
3640 | &omap3xxx_l4_per__gpio4, | |
3641 | &omap3xxx_l4_per__gpio5, | |
3642 | &omap3xxx_l4_per__gpio6, | |
3643 | &omap3xxx_dma_system__l3, | |
3644 | &omap3xxx_l4_core__dma_system, | |
3645 | &omap3xxx_l4_core__mcbsp1, | |
3646 | &omap3xxx_l4_per__mcbsp2, | |
3647 | &omap3xxx_l4_per__mcbsp3, | |
3648 | &omap3xxx_l4_per__mcbsp4, | |
3649 | &omap3xxx_l4_core__mcbsp5, | |
3650 | &omap3xxx_l4_per__mcbsp2_sidetone, | |
3651 | &omap3xxx_l4_per__mcbsp3_sidetone, | |
3652 | &omap34xx_l4_core__mcspi1, | |
3653 | &omap34xx_l4_core__mcspi2, | |
3654 | &omap34xx_l4_core__mcspi3, | |
3655 | &omap34xx_l4_core__mcspi4, | |
c8d82ff6 | 3656 | &omap3xxx_l4_wkup__counter_32k, |
49484a60 | 3657 | &omap3xxx_l3_main__gpmc, |
d6504acd PW |
3658 | NULL, |
3659 | }; | |
3660 | ||
0a78c5c5 | 3661 | /* GP-only hwmod links */ |
26f88e6e MG |
3662 | static struct omap_hwmod_ocp_if *omap34xx_gp_hwmod_ocp_ifs[] __initdata = { |
3663 | &omap3xxx_l4_sec__timer12, | |
26f88e6e MG |
3664 | NULL |
3665 | }; | |
3666 | ||
3667 | static struct omap_hwmod_ocp_if *omap36xx_gp_hwmod_ocp_ifs[] __initdata = { | |
0a78c5c5 | 3668 | &omap3xxx_l4_sec__timer12, |
26f88e6e MG |
3669 | NULL |
3670 | }; | |
3671 | ||
3672 | static struct omap_hwmod_ocp_if *am35xx_gp_hwmod_ocp_ifs[] __initdata = { | |
3673 | &omap3xxx_l4_sec__timer12, | |
a55a7445 PR |
3674 | NULL |
3675 | }; | |
3676 | ||
3677 | /* crypto hwmod links */ | |
3678 | static struct omap_hwmod_ocp_if *omap34xx_sham_hwmod_ocp_ifs[] __initdata = { | |
3679 | &omap3xxx_l4_core__sham, | |
3680 | NULL | |
3681 | }; | |
3682 | ||
3683 | static struct omap_hwmod_ocp_if *omap34xx_aes_hwmod_ocp_ifs[] __initdata = { | |
3684 | &omap3xxx_l4_core__aes, | |
3685 | NULL | |
3686 | }; | |
3687 | ||
3688 | static struct omap_hwmod_ocp_if *omap36xx_sham_hwmod_ocp_ifs[] __initdata = { | |
3689 | &omap3xxx_l4_core__sham, | |
3690 | NULL | |
3691 | }; | |
3692 | ||
3693 | static struct omap_hwmod_ocp_if *omap36xx_aes_hwmod_ocp_ifs[] __initdata = { | |
3694 | &omap3xxx_l4_core__aes, | |
3695 | NULL | |
3696 | }; | |
3697 | ||
3698 | /* | |
3699 | * Apparently the SHA/MD5 and AES accelerator IP blocks are | |
3700 | * only present on some AM35xx chips, and no one knows which | |
3701 | * ones. See | |
3702 | * http://www.spinics.net/lists/arm-kernel/msg215466.html So | |
3703 | * if you need these IP blocks on an AM35xx, try uncommenting | |
3704 | * the following lines. | |
3705 | */ | |
3706 | static struct omap_hwmod_ocp_if *am35xx_sham_hwmod_ocp_ifs[] __initdata = { | |
26f88e6e | 3707 | /* &omap3xxx_l4_core__sham, */ |
a55a7445 PR |
3708 | NULL |
3709 | }; | |
3710 | ||
3711 | static struct omap_hwmod_ocp_if *am35xx_aes_hwmod_ocp_ifs[] __initdata = { | |
14ae5564 | 3712 | /* &omap3xxx_l4_core__aes, */ |
91a36bdb AK |
3713 | NULL |
3714 | }; | |
3715 | ||
0a78c5c5 PW |
3716 | /* 3430ES1-only hwmod links */ |
3717 | static struct omap_hwmod_ocp_if *omap3430es1_hwmod_ocp_ifs[] __initdata = { | |
3718 | &omap3430es1_dss__l3, | |
3719 | &omap3430es1_l4_core__dss, | |
d6504acd PW |
3720 | NULL |
3721 | }; | |
3722 | ||
0a78c5c5 PW |
3723 | /* 3430ES2+-only hwmod links */ |
3724 | static struct omap_hwmod_ocp_if *omap3430es2plus_hwmod_ocp_ifs[] __initdata = { | |
3725 | &omap3xxx_dss__l3, | |
3726 | &omap3xxx_l4_core__dss, | |
3727 | &omap3xxx_usbhsotg__l3, | |
3728 | &omap3xxx_l4_core__usbhsotg, | |
3729 | &omap3xxx_usb_host_hs__l3_main_2, | |
3730 | &omap3xxx_l4_core__usb_host_hs, | |
3731 | &omap3xxx_l4_core__usb_tll_hs, | |
d6504acd PW |
3732 | NULL |
3733 | }; | |
870ea2b8 | 3734 | |
0a78c5c5 PW |
3735 | /* <= 3430ES3-only hwmod links */ |
3736 | static struct omap_hwmod_ocp_if *omap3430_pre_es3_hwmod_ocp_ifs[] __initdata = { | |
3737 | &omap3xxx_l4_core__pre_es3_mmc1, | |
3738 | &omap3xxx_l4_core__pre_es3_mmc2, | |
a52e2ab6 PW |
3739 | NULL |
3740 | }; | |
3741 | ||
0a78c5c5 PW |
3742 | /* 3430ES3+-only hwmod links */ |
3743 | static struct omap_hwmod_ocp_if *omap3430_es3plus_hwmod_ocp_ifs[] __initdata = { | |
3744 | &omap3xxx_l4_core__es3plus_mmc1, | |
3745 | &omap3xxx_l4_core__es3plus_mmc2, | |
a52e2ab6 PW |
3746 | NULL |
3747 | }; | |
3748 | ||
0a78c5c5 PW |
3749 | /* 34xx-only hwmod links (all ES revisions) */ |
3750 | static struct omap_hwmod_ocp_if *omap34xx_hwmod_ocp_ifs[] __initdata = { | |
3751 | &omap3xxx_l3__iva, | |
3752 | &omap34xx_l4_core__sr1, | |
3753 | &omap34xx_l4_core__sr2, | |
3754 | &omap3xxx_l4_core__mailbox, | |
45a4bb06 | 3755 | &omap3xxx_l4_core__hdq1w, |
8f993a01 | 3756 | &omap3xxx_sad2d__l3, |
5486474c | 3757 | &omap3xxx_l4_core__mmu_isp, |
5486474c | 3758 | &omap3xxx_l3_main__mmu_iva, |
77112076 | 3759 | &omap3xxx_l4_core__ssi, |
d6504acd PW |
3760 | NULL |
3761 | }; | |
273ff8c3 | 3762 | |
0a78c5c5 PW |
3763 | /* 36xx-only hwmod links (all ES revisions) */ |
3764 | static struct omap_hwmod_ocp_if *omap36xx_hwmod_ocp_ifs[] __initdata = { | |
3765 | &omap3xxx_l3__iva, | |
3766 | &omap36xx_l4_per__uart4, | |
3767 | &omap3xxx_dss__l3, | |
3768 | &omap3xxx_l4_core__dss, | |
3769 | &omap36xx_l4_core__sr1, | |
3770 | &omap36xx_l4_core__sr2, | |
3771 | &omap3xxx_usbhsotg__l3, | |
3772 | &omap3xxx_l4_core__usbhsotg, | |
3773 | &omap3xxx_l4_core__mailbox, | |
3774 | &omap3xxx_usb_host_hs__l3_main_2, | |
3775 | &omap3xxx_l4_core__usb_host_hs, | |
3776 | &omap3xxx_l4_core__usb_tll_hs, | |
3777 | &omap3xxx_l4_core__es3plus_mmc1, | |
3778 | &omap3xxx_l4_core__es3plus_mmc2, | |
45a4bb06 | 3779 | &omap3xxx_l4_core__hdq1w, |
8f993a01 | 3780 | &omap3xxx_sad2d__l3, |
5486474c | 3781 | &omap3xxx_l4_core__mmu_isp, |
5486474c | 3782 | &omap3xxx_l3_main__mmu_iva, |
77112076 | 3783 | &omap3xxx_l4_core__ssi, |
d6504acd PW |
3784 | NULL |
3785 | }; | |
3786 | ||
0a78c5c5 PW |
3787 | static struct omap_hwmod_ocp_if *am35xx_hwmod_ocp_ifs[] __initdata = { |
3788 | &omap3xxx_dss__l3, | |
3789 | &omap3xxx_l4_core__dss, | |
3790 | &am35xx_usbhsotg__l3, | |
3791 | &am35xx_l4_core__usbhsotg, | |
3792 | &am35xx_l4_core__uart4, | |
3793 | &omap3xxx_usb_host_hs__l3_main_2, | |
3794 | &omap3xxx_l4_core__usb_host_hs, | |
3795 | &omap3xxx_l4_core__usb_tll_hs, | |
3796 | &omap3xxx_l4_core__es3plus_mmc1, | |
3797 | &omap3xxx_l4_core__es3plus_mmc2, | |
b1a923d0 | 3798 | &omap3xxx_l4_core__hdq1w, |
31ba8808 MG |
3799 | &am35xx_mdio__l3, |
3800 | &am35xx_l4_core__mdio, | |
3801 | &am35xx_emac__l3, | |
3802 | &am35xx_l4_core__emac, | |
d6504acd | 3803 | NULL |
7359154e PW |
3804 | }; |
3805 | ||
0a78c5c5 PW |
3806 | static struct omap_hwmod_ocp_if *omap3xxx_dss_hwmod_ocp_ifs[] __initdata = { |
3807 | &omap3xxx_l4_core__dss_dispc, | |
3808 | &omap3xxx_l4_core__dss_dsi1, | |
3809 | &omap3xxx_l4_core__dss_rfbi, | |
3810 | &omap3xxx_l4_core__dss_venc, | |
1d2f56c8 IY |
3811 | NULL |
3812 | }; | |
3813 | ||
a55a7445 PR |
3814 | /** |
3815 | * omap3xxx_hwmod_is_hs_ip_block_usable - is a security IP block accessible? | |
3816 | * @bus: struct device_node * for the top-level OMAP DT data | |
3817 | * @dev_name: device name used in the DT file | |
3818 | * | |
3819 | * Determine whether a "secure" IP block @dev_name is usable by Linux. | |
3820 | * There doesn't appear to be a 100% reliable way to determine this, | |
3821 | * so we rely on heuristics. If @bus is null, meaning there's no DT | |
3822 | * data, then we only assume the IP block is accessible if the OMAP is | |
3823 | * fused as a 'general-purpose' SoC. If however DT data is present, | |
3824 | * test to see if the IP block is described in the DT data and set to | |
3825 | * 'status = "okay"'. If so then we assume the ODM has configured the | |
3826 | * OMAP firewalls to allow access to the IP block. | |
3827 | * | |
3828 | * Return: 0 if device named @dev_name is not likely to be accessible, | |
3829 | * or 1 if it is likely to be accessible. | |
3830 | */ | |
3831 | static int __init omap3xxx_hwmod_is_hs_ip_block_usable(struct device_node *bus, | |
3832 | const char *dev_name) | |
3833 | { | |
3834 | if (!bus) | |
3835 | return (omap_type() == OMAP2_DEVICE_TYPE_GP) ? 1 : 0; | |
3836 | ||
3837 | if (of_device_is_available(of_find_node_by_name(bus, dev_name))) | |
3838 | return 1; | |
3839 | ||
3840 | return 0; | |
3841 | } | |
3842 | ||
7359154e PW |
3843 | int __init omap3xxx_hwmod_init(void) |
3844 | { | |
d6504acd | 3845 | int r; |
a55a7445 PR |
3846 | struct omap_hwmod_ocp_if **h = NULL, **h_gp = NULL, **h_sham = NULL; |
3847 | struct omap_hwmod_ocp_if **h_aes = NULL; | |
3848 | struct device_node *bus = NULL; | |
d6504acd PW |
3849 | unsigned int rev; |
3850 | ||
9ebfd285 KH |
3851 | omap_hwmod_init(); |
3852 | ||
0a78c5c5 PW |
3853 | /* Register hwmod links common to all OMAP3 */ |
3854 | r = omap_hwmod_register_links(omap3xxx_hwmod_ocp_ifs); | |
ace90216 | 3855 | if (r < 0) |
d6504acd PW |
3856 | return r; |
3857 | ||
3858 | rev = omap_rev(); | |
3859 | ||
3860 | /* | |
0a78c5c5 | 3861 | * Register hwmod links common to individual OMAP3 families, all |
d6504acd PW |
3862 | * silicon revisions (e.g., 34xx, or AM3505/3517, or 36xx) |
3863 | * All possible revisions should be included in this conditional. | |
3864 | */ | |
3865 | if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 || | |
3866 | rev == OMAP3430_REV_ES2_1 || rev == OMAP3430_REV_ES3_0 || | |
3867 | rev == OMAP3430_REV_ES3_1 || rev == OMAP3430_REV_ES3_1_2) { | |
0a78c5c5 | 3868 | h = omap34xx_hwmod_ocp_ifs; |
26f88e6e | 3869 | h_gp = omap34xx_gp_hwmod_ocp_ifs; |
a55a7445 PR |
3870 | h_sham = omap34xx_sham_hwmod_ocp_ifs; |
3871 | h_aes = omap34xx_aes_hwmod_ocp_ifs; | |
68a88b98 | 3872 | } else if (rev == AM35XX_REV_ES1_0 || rev == AM35XX_REV_ES1_1) { |
0a78c5c5 | 3873 | h = am35xx_hwmod_ocp_ifs; |
26f88e6e | 3874 | h_gp = am35xx_gp_hwmod_ocp_ifs; |
a55a7445 PR |
3875 | h_sham = am35xx_sham_hwmod_ocp_ifs; |
3876 | h_aes = am35xx_aes_hwmod_ocp_ifs; | |
d6504acd PW |
3877 | } else if (rev == OMAP3630_REV_ES1_0 || rev == OMAP3630_REV_ES1_1 || |
3878 | rev == OMAP3630_REV_ES1_2) { | |
0a78c5c5 | 3879 | h = omap36xx_hwmod_ocp_ifs; |
26f88e6e | 3880 | h_gp = omap36xx_gp_hwmod_ocp_ifs; |
a55a7445 PR |
3881 | h_sham = omap36xx_sham_hwmod_ocp_ifs; |
3882 | h_aes = omap36xx_aes_hwmod_ocp_ifs; | |
d6504acd PW |
3883 | } else { |
3884 | WARN(1, "OMAP3 hwmod family init: unknown chip type\n"); | |
3885 | return -EINVAL; | |
c09fcc43 | 3886 | } |
d6504acd | 3887 | |
0a78c5c5 | 3888 | r = omap_hwmod_register_links(h); |
ace90216 | 3889 | if (r < 0) |
d6504acd PW |
3890 | return r; |
3891 | ||
26f88e6e MG |
3892 | /* Register GP-only hwmod links. */ |
3893 | if (h_gp && omap_type() == OMAP2_DEVICE_TYPE_GP) { | |
3894 | r = omap_hwmod_register_links(h_gp); | |
3895 | if (r < 0) | |
3896 | return r; | |
3897 | } | |
3898 | ||
a55a7445 PR |
3899 | /* |
3900 | * Register crypto hwmod links only if they are not disabled in DT. | |
3901 | * If DT information is missing, enable them only for GP devices. | |
3902 | */ | |
3903 | ||
3904 | if (of_have_populated_dt()) | |
3905 | bus = of_find_node_by_name(NULL, "ocp"); | |
3906 | ||
3907 | if (h_sham && omap3xxx_hwmod_is_hs_ip_block_usable(bus, "sham")) { | |
3908 | r = omap_hwmod_register_links(h_sham); | |
3909 | if (r < 0) | |
3910 | return r; | |
3911 | } | |
3912 | ||
3913 | if (h_aes && omap3xxx_hwmod_is_hs_ip_block_usable(bus, "aes")) { | |
3914 | r = omap_hwmod_register_links(h_aes); | |
3915 | if (r < 0) | |
3916 | return r; | |
3917 | } | |
26f88e6e | 3918 | |
d6504acd | 3919 | /* |
0a78c5c5 | 3920 | * Register hwmod links specific to certain ES levels of a |
d6504acd PW |
3921 | * particular family of silicon (e.g., 34xx ES1.0) |
3922 | */ | |
3923 | h = NULL; | |
3924 | if (rev == OMAP3430_REV_ES1_0) { | |
0a78c5c5 | 3925 | h = omap3430es1_hwmod_ocp_ifs; |
d6504acd PW |
3926 | } else if (rev == OMAP3430_REV_ES2_0 || rev == OMAP3430_REV_ES2_1 || |
3927 | rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 || | |
3928 | rev == OMAP3430_REV_ES3_1_2) { | |
0a78c5c5 | 3929 | h = omap3430es2plus_hwmod_ocp_ifs; |
c09fcc43 | 3930 | } |
d6504acd | 3931 | |
a52e2ab6 | 3932 | if (h) { |
0a78c5c5 | 3933 | r = omap_hwmod_register_links(h); |
a52e2ab6 PW |
3934 | if (r < 0) |
3935 | return r; | |
3936 | } | |
3937 | ||
3938 | h = NULL; | |
3939 | if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 || | |
3940 | rev == OMAP3430_REV_ES2_1) { | |
0a78c5c5 | 3941 | h = omap3430_pre_es3_hwmod_ocp_ifs; |
a52e2ab6 PW |
3942 | } else if (rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 || |
3943 | rev == OMAP3430_REV_ES3_1_2) { | |
0a78c5c5 | 3944 | h = omap3430_es3plus_hwmod_ocp_ifs; |
c09fcc43 | 3945 | } |
a52e2ab6 | 3946 | |
d6504acd | 3947 | if (h) |
0a78c5c5 | 3948 | r = omap_hwmod_register_links(h); |
1d2f56c8 IY |
3949 | if (r < 0) |
3950 | return r; | |
3951 | ||
3952 | /* | |
3953 | * DSS code presumes that dss_core hwmod is handled first, | |
3954 | * _before_ any other DSS related hwmods so register common | |
0a78c5c5 PW |
3955 | * DSS hwmod links last to ensure that dss_core is already |
3956 | * registered. Otherwise some change things may happen, for | |
3957 | * ex. if dispc is handled before dss_core and DSS is enabled | |
3958 | * in bootloader DISPC will be reset with outputs enabled | |
3959 | * which sometimes leads to unrecoverable L3 error. XXX The | |
3960 | * long-term fix to this is to ensure hwmods are set up in | |
3961 | * dependency order in the hwmod core code. | |
1d2f56c8 | 3962 | */ |
0a78c5c5 | 3963 | r = omap_hwmod_register_links(omap3xxx_dss_hwmod_ocp_ifs); |
d6504acd PW |
3964 | |
3965 | return r; | |
7359154e | 3966 | } |