projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| ee8c9571 | 1 | /* |
| ee8c9571 CM |
2 | * Copyright (C) 2007 ARM Limited |
| 3 | * | |
| 4 | * This program is free software; you can redistribute it and/or modify | |
| 5 | * it under the terms of the GNU General Public License version 2 as | |
| 6 | * published by the Free Software Foundation. | |
| 7 | * | |
| 8 | * This program is distributed in the hope that it will be useful, | |
| 9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 11 | * GNU General Public License for more details. | |
| 12 | * | |
| 13 | * You should have received a copy of the GNU General Public License | |
| 14 | * along with this program; if not, write to the Free Software | |
| 15 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, | |
| 16 | * MA 02110-1301, USA. | |
| 17 | */ | |
| 18 | ||
| 19 | #ifndef __MACH_IRQS_EB_H | |
| 20 | #define __MACH_IRQS_EB_H | |
| 21 | ||
| 38d2cfcc | 22 | #define IRQ_LOCALTIMER 29 |
| ee8c9571 CM |
23 | #define IRQ_EB_GIC_START 32 |
| 24 | ||
| 25 | /* | |
| 26 | * RealView EB interrupt sources | |
| 27 | */ | |
| 28 | #define IRQ_EB_WDOG (IRQ_EB_GIC_START + 0) /* Watchdog timer */ | |
| 29 | #define IRQ_EB_SOFT (IRQ_EB_GIC_START + 1) /* Software interrupt */ | |
| 30 | #define IRQ_EB_COMMRx (IRQ_EB_GIC_START + 2) /* Debug Comm Rx interrupt */ | |
| 31 | #define IRQ_EB_COMMTx (IRQ_EB_GIC_START + 3) /* Debug Comm Tx interrupt */ | |
| 32 | #define IRQ_EB_TIMER0_1 (IRQ_EB_GIC_START + 4) /* Timer 0 and 1 */ | |
| 33 | #define IRQ_EB_TIMER2_3 (IRQ_EB_GIC_START + 5) /* Timer 2 and 3 */ | |
| 34 | #define IRQ_EB_GPIO0 (IRQ_EB_GIC_START + 6) /* GPIO 0 */ | |
| 35 | #define IRQ_EB_GPIO1 (IRQ_EB_GIC_START + 7) /* GPIO 1 */ | |
| 36 | #define IRQ_EB_GPIO2 (IRQ_EB_GIC_START + 8) /* GPIO 2 */ | |
| 37 | /* 9 reserved */ | |
| 38 | #define IRQ_EB_RTC (IRQ_EB_GIC_START + 10) /* Real Time Clock */ | |
| 39 | #define IRQ_EB_SSP (IRQ_EB_GIC_START + 11) /* Synchronous Serial Port */ | |
| 40 | #define IRQ_EB_UART0 (IRQ_EB_GIC_START + 12) /* UART 0 on development chip */ | |
| 41 | #define IRQ_EB_UART1 (IRQ_EB_GIC_START + 13) /* UART 1 on development chip */ | |
| 42 | #define IRQ_EB_UART2 (IRQ_EB_GIC_START + 14) /* UART 2 on development chip */ | |
| 43 | #define IRQ_EB_UART3 (IRQ_EB_GIC_START + 15) /* UART 3 on development chip */ | |
| 44 | #define IRQ_EB_SCI (IRQ_EB_GIC_START + 16) /* Smart Card Interface */ | |
| 45 | #define IRQ_EB_MMCI0A (IRQ_EB_GIC_START + 17) /* Multimedia Card 0A */ | |
| 46 | #define IRQ_EB_MMCI0B (IRQ_EB_GIC_START + 18) /* Multimedia Card 0B */ | |
| 47 | #define IRQ_EB_AACI (IRQ_EB_GIC_START + 19) /* Audio Codec */ | |
| 48 | #define IRQ_EB_KMI0 (IRQ_EB_GIC_START + 20) /* Keyboard/Mouse port 0 */ | |
| 49 | #define IRQ_EB_KMI1 (IRQ_EB_GIC_START + 21) /* Keyboard/Mouse port 1 */ | |
| 50 | #define IRQ_EB_CHARLCD (IRQ_EB_GIC_START + 22) /* Character LCD */ | |
| 51 | #define IRQ_EB_CLCD (IRQ_EB_GIC_START + 23) /* CLCD controller */ | |
| 52 | #define IRQ_EB_DMA (IRQ_EB_GIC_START + 24) /* DMA controller */ | |
| 53 | #define IRQ_EB_PWRFAIL (IRQ_EB_GIC_START + 25) /* Power failure */ | |
| 54 | #define IRQ_EB_PISMO (IRQ_EB_GIC_START + 26) /* PISMO interface */ | |
| 55 | #define IRQ_EB_DoC (IRQ_EB_GIC_START + 27) /* Disk on Chip memory controller */ | |
| 56 | #define IRQ_EB_ETH (IRQ_EB_GIC_START + 28) /* Ethernet controller */ | |
| 57 | #define IRQ_EB_USB (IRQ_EB_GIC_START + 29) /* USB controller */ | |
| 58 | #define IRQ_EB_TSPEN (IRQ_EB_GIC_START + 30) /* Touchscreen pen */ | |
| 59 | #define IRQ_EB_TSKPAD (IRQ_EB_GIC_START + 31) /* Touchscreen keypad */ | |
| 60 | ||
| 61 | /* | |
| 62 | * RealView EB + ARM11MPCore interrupt sources (primary GIC on the core tile) | |
| 63 | */ | |
| 64 | #define IRQ_EB11MP_AACI (IRQ_EB_GIC_START + 0) | |
| 65 | #define IRQ_EB11MP_TIMER0_1 (IRQ_EB_GIC_START + 1) | |
| 66 | #define IRQ_EB11MP_TIMER2_3 (IRQ_EB_GIC_START + 2) | |
| 67 | #define IRQ_EB11MP_USB (IRQ_EB_GIC_START + 3) | |
| 68 | #define IRQ_EB11MP_UART0 (IRQ_EB_GIC_START + 4) | |
| 69 | #define IRQ_EB11MP_UART1 (IRQ_EB_GIC_START + 5) | |
| 70 | #define IRQ_EB11MP_RTC (IRQ_EB_GIC_START + 6) | |
| 71 | #define IRQ_EB11MP_KMI0 (IRQ_EB_GIC_START + 7) | |
| 72 | #define IRQ_EB11MP_KMI1 (IRQ_EB_GIC_START + 8) | |
| 73 | #define IRQ_EB11MP_ETH (IRQ_EB_GIC_START + 9) | |
| 74 | #define IRQ_EB11MP_EB_IRQ1 (IRQ_EB_GIC_START + 10) /* main GIC */ | |
| 75 | #define IRQ_EB11MP_EB_IRQ2 (IRQ_EB_GIC_START + 11) /* tile GIC */ | |
| 76 | #define IRQ_EB11MP_EB_FIQ1 (IRQ_EB_GIC_START + 12) /* main GIC */ | |
| 77 | #define IRQ_EB11MP_EB_FIQ2 (IRQ_EB_GIC_START + 13) /* tile GIC */ | |
| 78 | #define IRQ_EB11MP_MMCI0A (IRQ_EB_GIC_START + 14) | |
| 79 | #define IRQ_EB11MP_MMCI0B (IRQ_EB_GIC_START + 15) | |
| 80 | ||
| 81 | #define IRQ_EB11MP_PMU_CPU0 (IRQ_EB_GIC_START + 17) | |
| 82 | #define IRQ_EB11MP_PMU_CPU1 (IRQ_EB_GIC_START + 18) | |
| 83 | #define IRQ_EB11MP_PMU_CPU2 (IRQ_EB_GIC_START + 19) | |
| 84 | #define IRQ_EB11MP_PMU_CPU3 (IRQ_EB_GIC_START + 20) | |
| 85 | #define IRQ_EB11MP_PMU_SCU0 (IRQ_EB_GIC_START + 21) | |
| 86 | #define IRQ_EB11MP_PMU_SCU1 (IRQ_EB_GIC_START + 22) | |
| 87 | #define IRQ_EB11MP_PMU_SCU2 (IRQ_EB_GIC_START + 23) | |
| 88 | #define IRQ_EB11MP_PMU_SCU3 (IRQ_EB_GIC_START + 24) | |
| 89 | #define IRQ_EB11MP_PMU_SCU4 (IRQ_EB_GIC_START + 25) | |
| 90 | #define IRQ_EB11MP_PMU_SCU5 (IRQ_EB_GIC_START + 26) | |
| 91 | #define IRQ_EB11MP_PMU_SCU6 (IRQ_EB_GIC_START + 27) | |
| 92 | #define IRQ_EB11MP_PMU_SCU7 (IRQ_EB_GIC_START + 28) | |
| 93 | ||
| 94 | #define IRQ_EB11MP_L220_EVENT (IRQ_EB_GIC_START + 29) | |
| 95 | #define IRQ_EB11MP_L220_SLAVE (IRQ_EB_GIC_START + 30) | |
| 96 | #define IRQ_EB11MP_L220_DECODE (IRQ_EB_GIC_START + 31) | |
| 97 | ||
| c997e519 MZ |
98 | /* |
| 99 | * The 11MPcore tile leaves the following unconnected. | |
| 100 | */ | |
| 101 | #define IRQ_EB11MP_UART2 0 | |
| 102 | #define IRQ_EB11MP_UART3 0 | |
| 103 | #define IRQ_EB11MP_CLCD 0 | |
| 104 | #define IRQ_EB11MP_DMA 0 | |
| 105 | #define IRQ_EB11MP_WDOG 0 | |
| 106 | #define IRQ_EB11MP_GPIO0 0 | |
| 107 | #define IRQ_EB11MP_GPIO1 0 | |
| 108 | #define IRQ_EB11MP_GPIO2 0 | |
| 109 | #define IRQ_EB11MP_SCI 0 | |
| 110 | #define IRQ_EB11MP_SSP 0 | |
| ee8c9571 CM |
111 | |
| 112 | #define NR_GIC_EB11MP 2 | |
| 113 | ||
| ee8c9571 | 114 | #endif /* __MACH_IRQS_EB_H */ |