projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| ee8c9571 | 1 | /* |
| ee8c9571 CM |
2 | * Copyright (C) 2009 ARM Limited |
| 3 | * | |
| 4 | * This program is free software; you can redistribute it and/or modify | |
| 5 | * it under the terms of the GNU General Public License version 2 as | |
| 6 | * published by the Free Software Foundation. | |
| 7 | * | |
| 8 | * This program is distributed in the hope that it will be useful, | |
| 9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 11 | * GNU General Public License for more details. | |
| 12 | * | |
| 13 | * You should have received a copy of the GNU General Public License | |
| 14 | * along with this program; if not, write to the Free Software | |
| 15 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
| 16 | */ | |
| 17 | ||
| 18 | #ifndef __MACH_IRQS_PBX_H | |
| 19 | #define __MACH_IRQS_PBX_H | |
| 20 | ||
| 38d2cfcc | 21 | #define IRQ_LOCALTIMER 29 |
| ee8c9571 CM |
22 | #define IRQ_PBX_GIC_START 32 |
| 23 | ||
| ee8c9571 CM |
24 | /* |
| 25 | * PBX on-board gic irq sources | |
| 26 | */ | |
| 27 | #define IRQ_PBX_WATCHDOG (IRQ_PBX_GIC_START + 0) /* Watchdog timer */ | |
| 28 | #define IRQ_PBX_SOFT (IRQ_PBX_GIC_START + 1) /* Software interrupt */ | |
| 29 | #define IRQ_PBX_COMMRx (IRQ_PBX_GIC_START + 2) /* Debug Comm Rx interrupt */ | |
| 30 | #define IRQ_PBX_COMMTx (IRQ_PBX_GIC_START + 3) /* Debug Comm Tx interrupt */ | |
| 31 | #define IRQ_PBX_TIMER0_1 (IRQ_PBX_GIC_START + 4) /* Timer 0/1 (default timer) */ | |
| 32 | #define IRQ_PBX_TIMER2_3 (IRQ_PBX_GIC_START + 5) /* Timer 2/3 */ | |
| 33 | #define IRQ_PBX_GPIO0 (IRQ_PBX_GIC_START + 6) /* GPIO 0 */ | |
| 34 | #define IRQ_PBX_GPIO1 (IRQ_PBX_GIC_START + 7) /* GPIO 1 */ | |
| 35 | #define IRQ_PBX_GPIO2 (IRQ_PBX_GIC_START + 8) /* GPIO 2 */ | |
| 36 | /* 9 reserved */ | |
| 37 | #define IRQ_PBX_RTC (IRQ_PBX_GIC_START + 10) /* Real Time Clock */ | |
| 38 | #define IRQ_PBX_SSP (IRQ_PBX_GIC_START + 11) /* Synchronous Serial Port */ | |
| 39 | #define IRQ_PBX_UART0 (IRQ_PBX_GIC_START + 12) /* UART 0 on development chip */ | |
| 40 | #define IRQ_PBX_UART1 (IRQ_PBX_GIC_START + 13) /* UART 1 on development chip */ | |
| 41 | #define IRQ_PBX_UART2 (IRQ_PBX_GIC_START + 14) /* UART 2 on development chip */ | |
| 42 | #define IRQ_PBX_UART3 (IRQ_PBX_GIC_START + 15) /* UART 3 on development chip */ | |
| 43 | #define IRQ_PBX_SCI (IRQ_PBX_GIC_START + 16) /* Smart Card Interface */ | |
| 44 | #define IRQ_PBX_MMCI0A (IRQ_PBX_GIC_START + 17) /* Multimedia Card 0A */ | |
| 45 | #define IRQ_PBX_MMCI0B (IRQ_PBX_GIC_START + 18) /* Multimedia Card 0B */ | |
| 46 | #define IRQ_PBX_AACI (IRQ_PBX_GIC_START + 19) /* Audio Codec */ | |
| 47 | #define IRQ_PBX_KMI0 (IRQ_PBX_GIC_START + 20) /* Keyboard/Mouse port 0 */ | |
| 48 | #define IRQ_PBX_KMI1 (IRQ_PBX_GIC_START + 21) /* Keyboard/Mouse port 1 */ | |
| 49 | #define IRQ_PBX_CHARLCD (IRQ_PBX_GIC_START + 22) /* Character LCD */ | |
| 50 | #define IRQ_PBX_CLCD (IRQ_PBX_GIC_START + 23) /* CLCD controller */ | |
| 51 | #define IRQ_PBX_DMAC (IRQ_PBX_GIC_START + 24) /* DMA controller */ | |
| 52 | #define IRQ_PBX_PWRFAIL (IRQ_PBX_GIC_START + 25) /* Power failure */ | |
| 53 | #define IRQ_PBX_PISMO (IRQ_PBX_GIC_START + 26) /* PISMO interface */ | |
| 54 | #define IRQ_PBX_DoC (IRQ_PBX_GIC_START + 27) /* Disk on Chip memory controller */ | |
| 55 | #define IRQ_PBX_ETH (IRQ_PBX_GIC_START + 28) /* Ethernet controller */ | |
| 56 | #define IRQ_PBX_USB (IRQ_PBX_GIC_START + 29) /* USB controller */ | |
| 57 | #define IRQ_PBX_TSPEN (IRQ_PBX_GIC_START + 30) /* Touchscreen pen */ | |
| 58 | #define IRQ_PBX_TSKPAD (IRQ_PBX_GIC_START + 31) /* Touchscreen keypad */ | |
| 59 | ||
| 60 | #define IRQ_PBX_PMU_SCU0 (IRQ_PBX_GIC_START + 32) /* SCU PMU Interrupts (11mp) */ | |
| 61 | #define IRQ_PBX_PMU_SCU1 (IRQ_PBX_GIC_START + 33) | |
| 62 | #define IRQ_PBX_PMU_SCU2 (IRQ_PBX_GIC_START + 34) | |
| 63 | #define IRQ_PBX_PMU_SCU3 (IRQ_PBX_GIC_START + 35) | |
| 64 | #define IRQ_PBX_PMU_SCU4 (IRQ_PBX_GIC_START + 36) | |
| 65 | #define IRQ_PBX_PMU_SCU5 (IRQ_PBX_GIC_START + 37) | |
| 66 | #define IRQ_PBX_PMU_SCU6 (IRQ_PBX_GIC_START + 38) | |
| 67 | #define IRQ_PBX_PMU_SCU7 (IRQ_PBX_GIC_START + 39) | |
| 68 | ||
| 69 | #define IRQ_PBX_WATCHDOG1 (IRQ_PBX_GIC_START + 40) /* Watchdog1 timer */ | |
| 70 | #define IRQ_PBX_TIMER4_5 (IRQ_PBX_GIC_START + 41) /* Timer 0/1 (default timer) */ | |
| 71 | #define IRQ_PBX_TIMER6_7 (IRQ_PBX_GIC_START + 42) /* Timer 2/3 */ | |
| 72 | /* ... */ | |
| 3081e43b WD |
73 | #define IRQ_PBX_PMU_CPU0 (IRQ_PBX_GIC_START + 44) /* CPU PMU Interrupts */ |
| 74 | #define IRQ_PBX_PMU_CPU1 (IRQ_PBX_GIC_START + 45) | |
| 75 | #define IRQ_PBX_PMU_CPU2 (IRQ_PBX_GIC_START + 46) | |
| 76 | #define IRQ_PBX_PMU_CPU3 (IRQ_PBX_GIC_START + 47) | |
| ee8c9571 CM |
77 | |
| 78 | /* ... */ | |
| 79 | #define IRQ_PBX_PCI0 (IRQ_PBX_GIC_START + 50) | |
| 80 | #define IRQ_PBX_PCI1 (IRQ_PBX_GIC_START + 51) | |
| 81 | #define IRQ_PBX_PCI2 (IRQ_PBX_GIC_START + 52) | |
| 82 | #define IRQ_PBX_PCI3 (IRQ_PBX_GIC_START + 53) | |
| 83 | ||
| 84 | #define IRQ_PBX_SMC -1 | |
| 85 | #define IRQ_PBX_SCTL -1 | |
| 86 | ||
| ee8c9571 | 87 | #endif /* __MACH_IRQS_PBX_H */ |