projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 9c1ec8e1 CZ |
1 | /* |
| 2 | * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd | |
| 3 | * Author: Tony Xie <tony.xie@rock-chips.com> | |
| 4 | * | |
| 5 | * This program is free software; you can redistribute it and/or modify it | |
| 6 | * under the terms and conditions of the GNU General Public License, | |
| 7 | * version 2, as published by the Free Software Foundation. | |
| 8 | * | |
| 9 | * This program is distributed in the hope it will be useful, but WITHOUT | |
| 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
| 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
| 12 | * more details. | |
| 13 | */ | |
| 14 | ||
| 15 | #ifndef __MACH_ROCKCHIP_PM_H | |
| 16 | #define __MACH_ROCKCHIP_PM_H | |
| 17 | ||
| 18 | extern unsigned long rkpm_bootdata_cpusp; | |
| 19 | extern unsigned long rkpm_bootdata_cpu_code; | |
| 20 | extern unsigned long rkpm_bootdata_l2ctlr_f; | |
| 21 | extern unsigned long rkpm_bootdata_l2ctlr; | |
| 22 | extern unsigned long rkpm_bootdata_ddr_code; | |
| 23 | extern unsigned long rkpm_bootdata_ddr_data; | |
| 24 | extern unsigned long rk3288_bootram_sz; | |
| 25 | ||
| 26 | void rockchip_slp_cpu_resume(void); | |
| c8823e7a | 27 | #ifdef CONFIG_PM_SLEEP |
| 9c1ec8e1 | 28 | void __init rockchip_suspend_init(void); |
| c8823e7a AB |
29 | #else |
| 30 | static inline void rockchip_suspend_init(void) | |
| 31 | { | |
| 32 | } | |
| 33 | #endif | |
| 9c1ec8e1 CZ |
34 | |
| 35 | /****** following is rk3288 defined **********/ | |
| 36 | #define RK3288_PMU_WAKEUP_CFG0 0x00 | |
| 37 | #define RK3288_PMU_WAKEUP_CFG1 0x04 | |
| 38 | #define RK3288_PMU_PWRMODE_CON 0x18 | |
| 39 | #define RK3288_PMU_OSC_CNT 0x20 | |
| 40 | #define RK3288_PMU_PLL_CNT 0x24 | |
| 41 | #define RK3288_PMU_STABL_CNT 0x28 | |
| 42 | #define RK3288_PMU_DDR0IO_PWRON_CNT 0x2c | |
| 43 | #define RK3288_PMU_DDR1IO_PWRON_CNT 0x30 | |
| 44 | #define RK3288_PMU_CORE_PWRDWN_CNT 0x34 | |
| 45 | #define RK3288_PMU_CORE_PWRUP_CNT 0x38 | |
| 46 | #define RK3288_PMU_GPU_PWRDWN_CNT 0x3c | |
| 47 | #define RK3288_PMU_GPU_PWRUP_CNT 0x40 | |
| 48 | #define RK3288_PMU_WAKEUP_RST_CLR_CNT 0x44 | |
| 49 | #define RK3288_PMU_PWRMODE_CON1 0x90 | |
| 50 | ||
| 51 | #define RK3288_SGRF_SOC_CON0 (0x0000) | |
| 52 | #define RK3288_SGRF_FAST_BOOT_ADDR (0x0120) | |
| a0307d18 CZ |
53 | #define SGRF_PCLK_WDT_GATE BIT(6) |
| 54 | #define SGRF_PCLK_WDT_GATE_WRITE BIT(22) | |
| 9c1ec8e1 CZ |
55 | #define SGRF_FAST_BOOT_EN BIT(8) |
| 56 | #define SGRF_FAST_BOOT_EN_WRITE BIT(24) | |
| 57 | ||
| 0ea001d3 CZ |
58 | #define RK3288_SGRF_CPU_CON0 (0x40) |
| 59 | #define SGRF_DAPDEVICEEN BIT(0) | |
| 60 | #define SGRF_DAPDEVICEEN_WRITE BIT(16) | |
| 61 | ||
| 9c1ec8e1 CZ |
62 | /* PMU_WAKEUP_CFG1 bits */ |
| 63 | #define PMU_ARMINT_WAKEUP_EN BIT(0) | |
| 64 | ||
| aefc7c75 CZ |
65 | /* wait 30ms for OSC stable and 30ms for pmic stable */ |
| 66 | #define OSC_STABL_CNT_THRESH (32 * 30) | |
| 67 | #define PMU_STABL_CNT_THRESH (32 * 30) | |
| 68 | ||
| 9c1ec8e1 CZ |
69 | enum rk3288_pwr_mode_con { |
| 70 | PMU_PWR_MODE_EN = 0, | |
| 71 | PMU_CLK_CORE_SRC_GATE_EN, | |
| 72 | PMU_GLOBAL_INT_DISABLE, | |
| 73 | PMU_L2FLUSH_EN, | |
| 74 | PMU_BUS_PD_EN, | |
| 75 | PMU_A12_0_PD_EN, | |
| 76 | PMU_SCU_EN, | |
| 77 | PMU_PLL_PD_EN, | |
| 78 | PMU_CHIP_PD_EN, /* POWER OFF PIN ENABLE */ | |
| 79 | PMU_PWROFF_COMB, | |
| 80 | PMU_ALIVE_USE_LF, | |
| 81 | PMU_PMU_USE_LF, | |
| 82 | PMU_OSC_24M_DIS, | |
| 83 | PMU_INPUT_CLAMP_EN, | |
| 84 | PMU_WAKEUP_RESET_EN, | |
| 85 | PMU_SREF0_ENTER_EN, | |
| 86 | PMU_SREF1_ENTER_EN, | |
| 87 | PMU_DDR0IO_RET_EN, | |
| 88 | PMU_DDR1IO_RET_EN, | |
| 89 | PMU_DDR0_GATING_EN, | |
| 90 | PMU_DDR1_GATING_EN, | |
| 91 | PMU_DDR0IO_RET_DE_REQ, | |
| 92 | PMU_DDR1IO_RET_DE_REQ | |
| 93 | }; | |
| 94 | ||
| 95 | enum rk3288_pwr_mode_con1 { | |
| 96 | PMU_CLR_BUS = 0, | |
| 97 | PMU_CLR_CORE, | |
| 98 | PMU_CLR_CPUP, | |
| 99 | PMU_CLR_ALIVE, | |
| 100 | PMU_CLR_DMA, | |
| 101 | PMU_CLR_PERI, | |
| 102 | PMU_CLR_GPU, | |
| 103 | PMU_CLR_VIDEO, | |
| 104 | PMU_CLR_HEVC, | |
| 105 | PMU_CLR_VIO, | |
| 106 | }; | |
| 107 | ||
| 108 | #endif /* __MACH_ROCKCHIP_PM_H */ |