[deliverable/linux.git] / arch / arm / mach-sa1100 / clock.c

/*
 *  linux/arch/arm/mach-sa1100/clock.c
 */
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/device.h>
#include <linux/list.h>
#include <linux/errno.h>
#include <linux/err.h>
#include <linux/string.h>
#include <linux/clk.h>
#include <linux/spinlock.h>
#include <linux/mutex.h>
#include <linux/io.h>
#include <linux/clkdev.h>

#include <mach/hardware.h>
#include <mach/generic.h>

struct clkops {
	void			(*enable)(struct clk *);
	void			(*disable)(struct clk *);
	unsigned long		(*get_rate)(struct clk *);
};

struct clk {
	const struct clkops	*ops;
	unsigned int		enabled;
};

#define DEFINE_CLK(_name, _ops)				\
struct clk clk_##_name = {				\
		.ops	= _ops,				\
	}

static DEFINE_SPINLOCK(clocks_lock);

static void clk_gpio27_enable(struct clk *clk)
{
	/*
	 * First, set up the 3.6864MHz clock on GPIO 27 for the SA-1111:
	 * (SA-1110 Developer's Manual, section 9.1.2.1)
	 */
	GAFR |= GPIO_32_768kHz;
	GPDR |= GPIO_32_768kHz;
	TUCR = TUCR_3_6864MHz;
}

static void clk_gpio27_disable(struct clk *clk)
{
	TUCR = 0;
	GPDR &= ~GPIO_32_768kHz;
	GAFR &= ~GPIO_32_768kHz;
}

static void clk_cpu_enable(struct clk *clk)
{
}

static void clk_cpu_disable(struct clk *clk)
{
}

static unsigned long clk_cpu_get_rate(struct clk *clk)
{
	return sa11x0_getspeed(0) * 1000;
}

int clk_enable(struct clk *clk)
{
	unsigned long flags;

	if (clk) {
		spin_lock_irqsave(&clocks_lock, flags);
		if (clk->enabled++ == 0)
			clk->ops->enable(clk);
		spin_unlock_irqrestore(&clocks_lock, flags);
	}

	return 0;
}
EXPORT_SYMBOL(clk_enable);

void clk_disable(struct clk *clk)
{
	unsigned long flags;

	if (clk) {
		WARN_ON(clk->enabled == 0);
		spin_lock_irqsave(&clocks_lock, flags);
		if (--clk->enabled == 0)
			clk->ops->disable(clk);
		spin_unlock_irqrestore(&clocks_lock, flags);
	}
}
EXPORT_SYMBOL(clk_disable);

unsigned long clk_get_rate(struct clk *clk)
{
	if (clk && clk->ops && clk->ops->get_rate)
		return clk->ops->get_rate(clk);

	return 0;
}
EXPORT_SYMBOL(clk_get_rate);

const struct clkops clk_gpio27_ops = {
	.enable		= clk_gpio27_enable,
	.disable	= clk_gpio27_disable,
};

const struct clkops clk_cpu_ops = {
	.enable		= clk_cpu_enable,
	.disable	= clk_cpu_disable,
	.get_rate	= clk_cpu_get_rate,
};

static DEFINE_CLK(gpio27, &clk_gpio27_ops);

static DEFINE_CLK(cpu, &clk_cpu_ops);

static unsigned long clk_36864_get_rate(struct clk *clk)
{
	return 3686400;
}

static struct clkops clk_36864_ops = {
	.enable		= clk_cpu_enable,
	.disable	= clk_cpu_disable,
	.get_rate	= clk_36864_get_rate,
};

static DEFINE_CLK(36864, &clk_36864_ops);

static struct clk_lookup sa11xx_clkregs[] = {
	CLKDEV_INIT("sa1111.0", NULL, &clk_gpio27),
	CLKDEV_INIT("sa1100-rtc", NULL, NULL),
	CLKDEV_INIT("sa11x0-fb", NULL, &clk_cpu),
	CLKDEV_INIT("sa11x0-pcmcia", NULL, &clk_cpu),
	/* sa1111 names devices using internal offsets, PCMCIA is at 0x1800 */
	CLKDEV_INIT("1800", NULL, &clk_cpu),
	CLKDEV_INIT(NULL, "OSTIMER0", &clk_36864),
};

int __init sa11xx_clk_init(void)
{
	clkdev_add_table(sa11xx_clkregs, ARRAY_SIZE(sa11xx_clkregs));
	return 0;
}
Commit	Line	Data
97d654f8 RK	1	/*
	2	* linux/arch/arm/mach-sa1100/clock.c
	3	*/
	4	#include <linux/module.h>
	5	#include <linux/kernel.h>
5e1dbdb4	6	#include <linux/device.h>
97d654f8 RK	7	#include <linux/list.h>
	8	#include <linux/errno.h>
	9	#include <linux/err.h>
	10	#include <linux/string.h>
	11	#include <linux/clk.h>
	12	#include <linux/spinlock.h>
d0a9d75b	13	#include <linux/mutex.h>
4a8f8340 JZ	14	#include <linux/io.h>
4a8f8340 JZ	15	#include <linux/clkdev.h>
97d654f8	16
a09e64fb	17	#include <mach/hardware.h>
4faee128	18	#include <mach/generic.h>
97d654f8	19
4a8f8340 JZ	20	struct clkops {
	21	void (enable)(struct clk );
	22	void (disable)(struct clk );
4faee128	23	unsigned long (get_rate)(struct clk );
4a8f8340 JZ	24	};
4a8f8340 JZ	25
97d654f8	26	struct clk {
4a8f8340	27	const struct clkops *ops;
97d654f8	28	unsigned int enabled;
97d654f8 RK	29	};
97d654f8 RK	30
4a8f8340 JZ	31	#define DEFINE_CLK(_name, _ops) \
	32	struct clk clk_##_name = { \
	33	.ops = _ops, \
	34	}
	35
	36	static DEFINE_SPINLOCK(clocks_lock);
	37
	38	static void clk_gpio27_enable(struct clk *clk)
5e1dbdb4 RK	39	{
	40	/*
	41	* First, set up the 3.6864MHz clock on GPIO 27 for the SA-1111:
	42	* (SA-1110 Developer's Manual, section 9.1.2.1)
	43	*/
	44	GAFR \|= GPIO_32_768kHz;
	45	GPDR \|= GPIO_32_768kHz;
	46	TUCR = TUCR_3_6864MHz;
	47	}
	48
4a8f8340	49	static void clk_gpio27_disable(struct clk *clk)
5e1dbdb4 RK	50	{
	51	TUCR = 0;
	52	GPDR &= ~GPIO_32_768kHz;
	53	GAFR &= ~GPIO_32_768kHz;
	54	}
	55
4faee128 DES	56	static void clk_cpu_enable(struct clk *clk)
	57	{
	58	}
	59
	60	static void clk_cpu_disable(struct clk *clk)
	61	{
	62	}
	63
	64	static unsigned long clk_cpu_get_rate(struct clk *clk)
	65	{
	66	return sa11x0_getspeed(0) * 1000;
	67	}
	68
97d654f8 RK	69	int clk_enable(struct clk *clk)
	70	{
	71	unsigned long flags;
	72
4a8f8340 JZ	73	if (clk) {
	74	spin_lock_irqsave(&clocks_lock, flags);
	75	if (clk->enabled++ == 0)
	76	clk->ops->enable(clk);
	77	spin_unlock_irqrestore(&clocks_lock, flags);
	78	}
	79
97d654f8 RK	80	return 0;
	81	}
	82	EXPORT_SYMBOL(clk_enable);
	83
	84	void clk_disable(struct clk *clk)
	85	{
	86	unsigned long flags;
	87
4a8f8340 JZ	88	if (clk) {
	89	WARN_ON(clk->enabled == 0);
	90	spin_lock_irqsave(&clocks_lock, flags);
	91	if (--clk->enabled == 0)
	92	clk->ops->disable(clk);
	93	spin_unlock_irqrestore(&clocks_lock, flags);
	94	}
97d654f8 RK	95	}
	96	EXPORT_SYMBOL(clk_disable);
	97
4faee128 DES	98	unsigned long clk_get_rate(struct clk *clk)
	99	{
	100	if (clk && clk->ops && clk->ops->get_rate)
	101	return clk->ops->get_rate(clk);
	102
	103	return 0;
	104	}
	105	EXPORT_SYMBOL(clk_get_rate);
	106
4a8f8340 JZ	107	const struct clkops clk_gpio27_ops = {
	108	.enable = clk_gpio27_enable,
	109	.disable = clk_gpio27_disable,
	110	};
	111
4faee128 DES	112	const struct clkops clk_cpu_ops = {
	113	.enable = clk_cpu_enable,
	114	.disable = clk_cpu_disable,
	115	.get_rate = clk_cpu_get_rate,
	116	};
	117
4a8f8340 JZ	118	static DEFINE_CLK(gpio27, &clk_gpio27_ops);
4a8f8340 JZ	119
4faee128 DES	120	static DEFINE_CLK(cpu, &clk_cpu_ops);
4faee128 DES	121
ee3a4020 DES	122	static unsigned long clk_36864_get_rate(struct clk *clk)
	123	{
	124	return 3686400;
	125	}
	126
	127	static struct clkops clk_36864_ops = {
02ba38a5 RK	128	.enable = clk_cpu_enable,
02ba38a5 RK	129	.disable = clk_cpu_disable,
ee3a4020 DES	130	.get_rate = clk_36864_get_rate,
	131	};
	132
	133	static DEFINE_CLK(36864, &clk_36864_ops);
	134
4a8f8340 JZ	135	static struct clk_lookup sa11xx_clkregs[] = {
	136	CLKDEV_INIT("sa1111.0", NULL, &clk_gpio27),
	137	CLKDEV_INIT("sa1100-rtc", NULL, NULL),
4faee128 DES	138	CLKDEV_INIT("sa11x0-fb", NULL, &clk_cpu),
4faee128 DES	139	CLKDEV_INIT("sa11x0-pcmcia", NULL, &clk_cpu),
7faf6d1a DES	140	/* sa1111 names devices using internal offsets, PCMCIA is at 0x1800 */
7faf6d1a DES	141	CLKDEV_INIT("1800", NULL, &clk_cpu),
ee3a4020	142	CLKDEV_INIT(NULL, "OSTIMER0", &clk_36864),
4a8f8340 JZ	143	};
4a8f8340 JZ	144
198b51e8	145	int __init sa11xx_clk_init(void)
97d654f8	146	{
4a8f8340 JZ	147	clkdev_add_table(sa11xx_clkregs, ARRAY_SIZE(sa11xx_clkregs));
4a8f8340 JZ	148	return 0;
97d654f8	149	}