[deliverable/linux.git] / arch / arm / mach-sa1100 / generic.c

/*
 * linux/arch/arm/mach-sa1100/generic.c
 *
 * Author: Nicolas Pitre
 *
 * Code common to all SA11x0 machines.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
#include <linux/gpio.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/dma-mapping.h>
#include <linux/pm.h>
#include <linux/cpufreq.h>
#include <linux/ioport.h>
#include <linux/platform_device.h>
#include <linux/reboot.h>
#include <linux/irqchip/irq-sa11x0.h>

#include <video/sa1100fb.h>

#include <soc/sa1100/pwer.h>

#include <asm/div64.h>
#include <asm/mach/map.h>
#include <asm/mach/flash.h>
#include <asm/irq.h>
#include <asm/system_misc.h>

#include <mach/hardware.h>
#include <mach/irqs.h>
#include <mach/reset.h>

#include "generic.h"
#include <clocksource/pxa.h>

unsigned int reset_status;
EXPORT_SYMBOL(reset_status);

#define NR_FREQS	16

/*
 * This table is setup for a 3.6864MHz Crystal.
 */
struct cpufreq_frequency_table sa11x0_freq_table[NR_FREQS+1] = {
	{ .frequency = 59000,	/*  59.0 MHz */},
	{ .frequency = 73700,	/*  73.7 MHz */},
	{ .frequency = 88500,	/*  88.5 MHz */},
	{ .frequency = 103200,	/* 103.2 MHz */},
	{ .frequency = 118000,	/* 118.0 MHz */},
	{ .frequency = 132700,	/* 132.7 MHz */},
	{ .frequency = 147500,	/* 147.5 MHz */},
	{ .frequency = 162200,	/* 162.2 MHz */},
	{ .frequency = 176900,	/* 176.9 MHz */},
	{ .frequency = 191700,	/* 191.7 MHz */},
	{ .frequency = 206400,	/* 206.4 MHz */},
	{ .frequency = 221200,	/* 221.2 MHz */},
	{ .frequency = 235900,	/* 235.9 MHz */},
	{ .frequency = 250700,	/* 250.7 MHz */},
	{ .frequency = 265400,	/* 265.4 MHz */},
	{ .frequency = 280200,	/* 280.2 MHz */},
	{ .frequency = CPUFREQ_TABLE_END, },
};

unsigned int sa11x0_getspeed(unsigned int cpu)
{
	if (cpu)
		return 0;
	return sa11x0_freq_table[PPCR & 0xf].frequency;
}

/*
 * Default power-off for SA1100
 */
static void sa1100_power_off(void)
{
	mdelay(100);
	local_irq_disable();
	/* disable internal oscillator, float CS lines */
	PCFR = (PCFR_OPDE | PCFR_FP | PCFR_FS);
	/* enable wake-up on GPIO0 (Assabet...) */
	PWER = GFER = GRER = 1;
	/*
	 * set scratchpad to zero, just in case it is used as a
	 * restart address by the bootloader.
	 */
	PSPR = 0;
	/* enter sleep mode */
	PMCR = PMCR_SF;
}

void sa11x0_restart(enum reboot_mode mode, const char *cmd)
{
	clear_reset_status(RESET_STATUS_ALL);

	if (mode == REBOOT_SOFT) {
		/* Jump into ROM at address 0 */
		soft_restart(0);
	} else {
		/* Use on-chip reset capability */
		RSRR = RSRR_SWR;
	}
}

static void sa11x0_register_device(struct platform_device *dev, void *data)
{
	int err;
	dev->dev.platform_data = data;
	err = platform_device_register(dev);
	if (err)
		printk(KERN_ERR "Unable to register device %s: %d\n",
			dev->name, err);
}


static struct resource sa11x0udc_resources[] = {
	[0] = DEFINE_RES_MEM(__PREG(Ser0UDCCR), SZ_64K),
	[1] = DEFINE_RES_IRQ(IRQ_Ser0UDC),
};

static u64 sa11x0udc_dma_mask = 0xffffffffUL;

static struct platform_device sa11x0udc_device = {
	.name		= "sa11x0-udc",
	.id		= -1,
	.dev		= {
		.dma_mask = &sa11x0udc_dma_mask,
		.coherent_dma_mask = 0xffffffff,
	},
	.num_resources	= ARRAY_SIZE(sa11x0udc_resources),
	.resource	= sa11x0udc_resources,
};

static struct resource sa11x0uart1_resources[] = {
	[0] = DEFINE_RES_MEM(__PREG(Ser1UTCR0), SZ_64K),
	[1] = DEFINE_RES_IRQ(IRQ_Ser1UART),
};

static struct platform_device sa11x0uart1_device = {
	.name		= "sa11x0-uart",
	.id		= 1,
	.num_resources	= ARRAY_SIZE(sa11x0uart1_resources),
	.resource	= sa11x0uart1_resources,
};

static struct resource sa11x0uart3_resources[] = {
	[0] = DEFINE_RES_MEM(__PREG(Ser3UTCR0), SZ_64K),
	[1] = DEFINE_RES_IRQ(IRQ_Ser3UART),
};

static struct platform_device sa11x0uart3_device = {
	.name		= "sa11x0-uart",
	.id		= 3,
	.num_resources	= ARRAY_SIZE(sa11x0uart3_resources),
	.resource	= sa11x0uart3_resources,
};

static struct resource sa11x0mcp_resources[] = {
	[0] = DEFINE_RES_MEM(__PREG(Ser4MCCR0), SZ_64K),
	[1] = DEFINE_RES_MEM(__PREG(Ser4MCCR1), 4),
	[2] = DEFINE_RES_IRQ(IRQ_Ser4MCP),
};

static u64 sa11x0mcp_dma_mask = 0xffffffffUL;

static struct platform_device sa11x0mcp_device = {
	.name		= "sa11x0-mcp",
	.id		= -1,
	.dev = {
		.dma_mask = &sa11x0mcp_dma_mask,
		.coherent_dma_mask = 0xffffffff,
	},
	.num_resources	= ARRAY_SIZE(sa11x0mcp_resources),
	.resource	= sa11x0mcp_resources,
};

void __init sa11x0_ppc_configure_mcp(void)
{
	/* Setup the PPC unit for the MCP */
	PPDR &= ~PPC_RXD4;
	PPDR |= PPC_TXD4 | PPC_SCLK | PPC_SFRM;
	PSDR |= PPC_RXD4;
	PSDR &= ~(PPC_TXD4 | PPC_SCLK | PPC_SFRM);
	PPSR &= ~(PPC_TXD4 | PPC_SCLK | PPC_SFRM);
}

void sa11x0_register_mcp(struct mcp_plat_data *data)
{
	sa11x0_register_device(&sa11x0mcp_device, data);
}

static struct resource sa11x0ssp_resources[] = {
	[0] = DEFINE_RES_MEM(0x80070000, SZ_64K),
	[1] = DEFINE_RES_IRQ(IRQ_Ser4SSP),
};

static u64 sa11x0ssp_dma_mask = 0xffffffffUL;

static struct platform_device sa11x0ssp_device = {
	.name		= "sa11x0-ssp",
	.id		= -1,
	.dev = {
		.dma_mask = &sa11x0ssp_dma_mask,
		.coherent_dma_mask = 0xffffffff,
	},
	.num_resources	= ARRAY_SIZE(sa11x0ssp_resources),
	.resource	= sa11x0ssp_resources,
};

static struct resource sa11x0fb_resources[] = {
	[0] = DEFINE_RES_MEM(0xb0100000, SZ_64K),
	[1] = DEFINE_RES_IRQ(IRQ_LCD),
};

static struct platform_device sa11x0fb_device = {
	.name		= "sa11x0-fb",
	.id		= -1,
	.dev = {
		.coherent_dma_mask = 0xffffffff,
	},
	.num_resources	= ARRAY_SIZE(sa11x0fb_resources),
	.resource	= sa11x0fb_resources,
};

void sa11x0_register_lcd(struct sa1100fb_mach_info *inf)
{
	sa11x0_register_device(&sa11x0fb_device, inf);
}

static struct platform_device sa11x0pcmcia_device = {
	.name		= "sa11x0-pcmcia",
	.id		= -1,
};

static struct platform_device sa11x0mtd_device = {
	.name		= "sa1100-mtd",
	.id		= -1,
};

void sa11x0_register_mtd(struct flash_platform_data *flash,
			 struct resource *res, int nr)
{
	flash->name = "sa1100";
	sa11x0mtd_device.resource = res;
	sa11x0mtd_device.num_resources = nr;
	sa11x0_register_device(&sa11x0mtd_device, flash);
}

static struct resource sa11x0ir_resources[] = {
	DEFINE_RES_MEM(__PREG(Ser2UTCR0), 0x24),
	DEFINE_RES_MEM(__PREG(Ser2HSCR0), 0x1c),
	DEFINE_RES_MEM(__PREG(Ser2HSCR2), 0x04),
	DEFINE_RES_IRQ(IRQ_Ser2ICP),
};

static struct platform_device sa11x0ir_device = {
	.name		= "sa11x0-ir",
	.id		= -1,
	.num_resources	= ARRAY_SIZE(sa11x0ir_resources),
	.resource	= sa11x0ir_resources,
};

void sa11x0_register_irda(struct irda_platform_data *irda)
{
	sa11x0_register_device(&sa11x0ir_device, irda);
}

static struct resource sa1100_rtc_resources[] = {
	DEFINE_RES_MEM(0x90010000, 0x40),
	DEFINE_RES_IRQ_NAMED(IRQ_RTC1Hz, "rtc 1Hz"),
	DEFINE_RES_IRQ_NAMED(IRQ_RTCAlrm, "rtc alarm"),
};

static struct platform_device sa11x0rtc_device = {
	.name		= "sa1100-rtc",
	.id		= -1,
	.num_resources	= ARRAY_SIZE(sa1100_rtc_resources),
	.resource	= sa1100_rtc_resources,
};

static struct resource sa11x0dma_resources[] = {
	DEFINE_RES_MEM(DMA_PHYS, DMA_SIZE),
	DEFINE_RES_IRQ(IRQ_DMA0),
	DEFINE_RES_IRQ(IRQ_DMA1),
	DEFINE_RES_IRQ(IRQ_DMA2),
	DEFINE_RES_IRQ(IRQ_DMA3),
	DEFINE_RES_IRQ(IRQ_DMA4),
	DEFINE_RES_IRQ(IRQ_DMA5),
};

static u64 sa11x0dma_dma_mask = DMA_BIT_MASK(32);

static struct platform_device sa11x0dma_device = {
	.name		= "sa11x0-dma",
	.id		= -1,
	.dev = {
		.dma_mask = &sa11x0dma_dma_mask,
		.coherent_dma_mask = 0xffffffff,
	},
	.num_resources	= ARRAY_SIZE(sa11x0dma_resources),
	.resource	= sa11x0dma_resources,
};

static struct platform_device *sa11x0_devices[] __initdata = {
	&sa11x0udc_device,
	&sa11x0uart1_device,
	&sa11x0uart3_device,
	&sa11x0ssp_device,
	&sa11x0pcmcia_device,
	&sa11x0rtc_device,
	&sa11x0dma_device,
};

static int __init sa1100_init(void)
{
	pm_power_off = sa1100_power_off;
	return platform_add_devices(sa11x0_devices, ARRAY_SIZE(sa11x0_devices));
}

arch_initcall(sa1100_init);

void __init sa11x0_init_late(void)
{
	sa11x0_pm_init();
}

/*
 * Common I/O mapping:
 *
 * Typically, static virtual address mappings are as follow:
 *
 * 0xf0000000-0xf3ffffff:	miscellaneous stuff (CPLDs, etc.)
 * 0xf4000000-0xf4ffffff:	SA-1111
 * 0xf5000000-0xf5ffffff:	reserved (used by cache flushing area)
 * 0xf6000000-0xfffeffff:	reserved (internal SA1100 IO defined above)
 * 0xffff0000-0xffff0fff:	SA1100 exception vectors
 * 0xffff2000-0xffff2fff:	Minicache copy_user_page area
 *
 * Below 0xe8000000 is reserved for vm allocation.
 *
 * The machine specific code must provide the extra mapping beside the
 * default mapping provided here.
 */

static struct map_desc standard_io_desc[] __initdata = {
	{	/* PCM */
		.virtual	=  0xf8000000,
		.pfn		= __phys_to_pfn(0x80000000),
		.length		= 0x00100000,
		.type		= MT_DEVICE
	}, {	/* SCM */
		.virtual	=  0xfa000000,
		.pfn		= __phys_to_pfn(0x90000000),
		.length		= 0x00100000,
		.type		= MT_DEVICE
	}, {	/* MER */
		.virtual	=  0xfc000000,
		.pfn		= __phys_to_pfn(0xa0000000),
		.length		= 0x00100000,
		.type		= MT_DEVICE
	}, {	/* LCD + DMA */
		.virtual	=  0xfe000000,
		.pfn		= __phys_to_pfn(0xb0000000),
		.length		= 0x00200000,
		.type		= MT_DEVICE
	},
};

void __init sa1100_map_io(void)
{
	iotable_init(standard_io_desc, ARRAY_SIZE(standard_io_desc));
}

void __init sa1100_timer_init(void)
{
	pxa_timer_nodt_init(IRQ_OST0, io_p2v(0x90000000), 3686400);
}

static struct resource irq_resource =
	DEFINE_RES_MEM_NAMED(0x90050000, SZ_64K, "irqs");

void __init sa1100_init_irq(void)
{
	request_resource(&iomem_resource, &irq_resource);

	sa11x0_init_irq_nodt(IRQ_GPIO0_SC, irq_resource.start);

	sa1100_init_gpio();
	sa11xx_clk_init();
}

/*
 * Disable the memory bus request/grant signals on the SA1110 to
 * ensure that we don't receive spurious memory requests.  We set
 * the MBGNT signal false to ensure the SA1111 doesn't own the
 * SDRAM bus.
 */
void sa1110_mb_disable(void)
{
	unsigned long flags;

	local_irq_save(flags);
	
	PGSR &= ~GPIO_MBGNT;
	GPCR = GPIO_MBGNT;
	GPDR = (GPDR & ~GPIO_MBREQ) | GPIO_MBGNT;

	GAFR &= ~(GPIO_MBGNT | GPIO_MBREQ);

	local_irq_restore(flags);
}

/*
 * If the system is going to use the SA-1111 DMA engines, set up
 * the memory bus request/grant pins.
 */
void sa1110_mb_enable(void)
{
	unsigned long flags;

	local_irq_save(flags);

	PGSR &= ~GPIO_MBGNT;
	GPCR = GPIO_MBGNT;
	GPDR = (GPDR & ~GPIO_MBREQ) | GPIO_MBGNT;

	GAFR |= (GPIO_MBGNT | GPIO_MBREQ);
	TUCR |= TUCR_MR;

	local_irq_restore(flags);
}

int sa11x0_gpio_set_wake(unsigned int gpio, unsigned int on)
{
	if (on)
		PWER |= BIT(gpio);
	else
		PWER &= ~BIT(gpio);

	return 0;
}

int sa11x0_sc_set_wake(unsigned int irq, unsigned int on)
{
	if (BIT(irq) != IC_RTCAlrm)
		return -EINVAL;

	if (on)
		PWER |= PWER_RTC;
	else
		PWER &= ~PWER_RTC;

	return 0;
}
Commit	Line	Data
1da177e4 LT	1	/*
	2	* linux/arch/arm/mach-sa1100/generic.c
	3	*
	4	* Author: Nicolas Pitre
	5	*
	6	* Code common to all SA11x0 machines.
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2 as
	10	* published by the Free Software Foundation.
	11	*/
2f8163ba	12	#include <linux/gpio.h>
1da177e4 LT	13	#include <linux/module.h>
	14	#include <linux/kernel.h>
	15	#include <linux/init.h>
	16	#include <linux/delay.h>
7931d92f	17	#include <linux/dma-mapping.h>
1da177e4 LT	18	#include <linux/pm.h>
	19	#include <linux/cpufreq.h>
	20	#include <linux/ioport.h>
d052d1be	21	#include <linux/platform_device.h>
7b6d864b	22	#include <linux/reboot.h>
85e6f097	23	#include <linux/irqchip/irq-sa11x0.h>
1da177e4	24
e1b7a72a RK	25	#include <video/sa1100fb.h>
e1b7a72a RK	26
982b465a DES	27	#include <soc/sa1100/pwer.h>
982b465a DES	28
1da177e4	29	#include <asm/div64.h>
1da177e4	30	#include <asm/mach/map.h>
14e66f76	31	#include <asm/mach/flash.h>
1da177e4	32	#include <asm/irq.h>
9f97da78	33	#include <asm/system_misc.h>
1da177e4	34
f314f33b RH	35	#include <mach/hardware.h>
f314f33b RH	36	#include <mach/irqs.h>
da60626e	37	#include <mach/reset.h>
f314f33b	38
1da177e4	39	#include "generic.h"
7a8ca0a0	40	#include <clocksource/pxa.h>
1da177e4	41
04fef228 EM	42	unsigned int reset_status;
	43	EXPORT_SYMBOL(reset_status);
	44
1da177e4 LT	45	#define NR_FREQS 16
	46
	47	/*
	48	* This table is setup for a 3.6864MHz Crystal.
	49	*/
22c8b4f1 VK	50	struct cpufreq_frequency_table sa11x0_freq_table[NR_FREQS+1] = {
	51	{ .frequency = 59000, /* 59.0 MHz */},
	52	{ .frequency = 73700, /* 73.7 MHz */},
	53	{ .frequency = 88500, /* 88.5 MHz */},
	54	{ .frequency = 103200, /* 103.2 MHz */},
	55	{ .frequency = 118000, /* 118.0 MHz */},
	56	{ .frequency = 132700, /* 132.7 MHz */},
	57	{ .frequency = 147500, /* 147.5 MHz */},
	58	{ .frequency = 162200, /* 162.2 MHz */},
	59	{ .frequency = 176900, /* 176.9 MHz */},
	60	{ .frequency = 191700, /* 191.7 MHz */},
	61	{ .frequency = 206400, /* 206.4 MHz */},
	62	{ .frequency = 221200, /* 221.2 MHz */},
	63	{ .frequency = 235900, /* 235.9 MHz */},
	64	{ .frequency = 250700, /* 250.7 MHz */},
	65	{ .frequency = 265400, /* 265.4 MHz */},
	66	{ .frequency = 280200, /* 280.2 MHz */},
	67	{ .frequency = CPUFREQ_TABLE_END, },
1da177e4 LT	68	};
1da177e4 LT	69
1da177e4 LT	70	unsigned int sa11x0_getspeed(unsigned int cpu)
	71	{
	72	if (cpu)
	73	return 0;
22c8b4f1	74	return sa11x0_freq_table[PPCR & 0xf].frequency;
1da177e4 LT	75	}
1da177e4 LT	76
1da177e4 LT	77	/*
	78	* Default power-off for SA1100
	79	*/
	80	static void sa1100_power_off(void)
	81	{
	82	mdelay(100);
	83	local_irq_disable();
	84	/* disable internal oscillator, float CS lines */
	85	PCFR = (PCFR_OPDE \| PCFR_FP \| PCFR_FS);
	86	/* enable wake-up on GPIO0 (Assabet...) */
	87	PWER = GFER = GRER = 1;
	88	/*
	89	* set scratchpad to zero, just in case it is used as a
	90	* restart address by the bootloader.
	91	*/
	92	PSPR = 0;
	93	/* enter sleep mode */
	94	PMCR = PMCR_SF;
	95	}
	96
7b6d864b	97	void sa11x0_restart(enum reboot_mode mode, const char *cmd)
d9ca5839	98	{
da60626e RK	99	clear_reset_status(RESET_STATUS_ALL);
da60626e RK	100
7b6d864b	101	if (mode == REBOOT_SOFT) {
d9ca5839 RK	102	/* Jump into ROM at address 0 */
	103	soft_restart(0);
	104	} else {
	105	/* Use on-chip reset capability */
	106	RSRR = RSRR_SWR;
	107	}
	108	}
	109
7a5b4e16 RK	110	static void sa11x0_register_device(struct platform_device dev, void data)
	111	{
	112	int err;
	113	dev->dev.platform_data = data;
	114	err = platform_device_register(dev);
	115	if (err)
	116	printk(KERN_ERR "Unable to register device %s: %d\n",
	117	dev->name, err);
	118	}
	119
	120
1da177e4	121	static struct resource sa11x0udc_resources[] = {
a181099e RK	122	[0] = DEFINE_RES_MEM(__PREG(Ser0UDCCR), SZ_64K),
a181099e RK	123	[1] = DEFINE_RES_IRQ(IRQ_Ser0UDC),
1da177e4 LT	124	};
	125
	126	static u64 sa11x0udc_dma_mask = 0xffffffffUL;
	127
	128	static struct platform_device sa11x0udc_device = {
	129	.name = "sa11x0-udc",
	130	.id = -1,
	131	.dev = {
	132	.dma_mask = &sa11x0udc_dma_mask,
	133	.coherent_dma_mask = 0xffffffff,
	134	},
	135	.num_resources = ARRAY_SIZE(sa11x0udc_resources),
	136	.resource = sa11x0udc_resources,
	137	};
	138
	139	static struct resource sa11x0uart1_resources[] = {
a181099e RK	140	[0] = DEFINE_RES_MEM(__PREG(Ser1UTCR0), SZ_64K),
a181099e RK	141	[1] = DEFINE_RES_IRQ(IRQ_Ser1UART),
1da177e4 LT	142	};
	143
	144	static struct platform_device sa11x0uart1_device = {
	145	.name = "sa11x0-uart",
	146	.id = 1,
	147	.num_resources = ARRAY_SIZE(sa11x0uart1_resources),
	148	.resource = sa11x0uart1_resources,
	149	};
	150
	151	static struct resource sa11x0uart3_resources[] = {
a181099e RK	152	[0] = DEFINE_RES_MEM(__PREG(Ser3UTCR0), SZ_64K),
a181099e RK	153	[1] = DEFINE_RES_IRQ(IRQ_Ser3UART),
1da177e4 LT	154	};
	155
	156	static struct platform_device sa11x0uart3_device = {
	157	.name = "sa11x0-uart",
	158	.id = 3,
	159	.num_resources = ARRAY_SIZE(sa11x0uart3_resources),
	160	.resource = sa11x0uart3_resources,
	161	};
	162
	163	static struct resource sa11x0mcp_resources[] = {
a181099e	164	[0] = DEFINE_RES_MEM(__PREG(Ser4MCCR0), SZ_64K),
7256ecc2 RK	165	[1] = DEFINE_RES_MEM(__PREG(Ser4MCCR1), 4),
7256ecc2 RK	166	[2] = DEFINE_RES_IRQ(IRQ_Ser4MCP),
1da177e4 LT	167	};
	168
	169	static u64 sa11x0mcp_dma_mask = 0xffffffffUL;
	170
	171	static struct platform_device sa11x0mcp_device = {
	172	.name = "sa11x0-mcp",
	173	.id = -1,
	174	.dev = {
	175	.dma_mask = &sa11x0mcp_dma_mask,
	176	.coherent_dma_mask = 0xffffffff,
	177	},
	178	.num_resources = ARRAY_SIZE(sa11x0mcp_resources),
	179	.resource = sa11x0mcp_resources,
	180	};
	181
e36e26a8 RK	182	void __init sa11x0_ppc_configure_mcp(void)
	183	{
	184	/* Setup the PPC unit for the MCP */
	185	PPDR &= ~PPC_RXD4;
	186	PPDR \|= PPC_TXD4 \| PPC_SCLK \| PPC_SFRM;
	187	PSDR \|= PPC_RXD4;
	188	PSDR &= ~(PPC_TXD4 \| PPC_SCLK \| PPC_SFRM);
	189	PPSR &= ~(PPC_TXD4 \| PPC_SCLK \| PPC_SFRM);
	190	}
	191
7a5b4e16	192	void sa11x0_register_mcp(struct mcp_plat_data *data)
323cdfc1	193	{
7a5b4e16	194	sa11x0_register_device(&sa11x0mcp_device, data);
323cdfc1 RK	195	}
323cdfc1 RK	196
1da177e4	197	static struct resource sa11x0ssp_resources[] = {
a181099e RK	198	[0] = DEFINE_RES_MEM(0x80070000, SZ_64K),
a181099e RK	199	[1] = DEFINE_RES_IRQ(IRQ_Ser4SSP),
1da177e4 LT	200	};
	201
	202	static u64 sa11x0ssp_dma_mask = 0xffffffffUL;
	203
	204	static struct platform_device sa11x0ssp_device = {
	205	.name = "sa11x0-ssp",
	206	.id = -1,
	207	.dev = {
	208	.dma_mask = &sa11x0ssp_dma_mask,
	209	.coherent_dma_mask = 0xffffffff,
	210	},
	211	.num_resources = ARRAY_SIZE(sa11x0ssp_resources),
	212	.resource = sa11x0ssp_resources,
	213	};
	214
	215	static struct resource sa11x0fb_resources[] = {
a181099e RK	216	[0] = DEFINE_RES_MEM(0xb0100000, SZ_64K),
a181099e RK	217	[1] = DEFINE_RES_IRQ(IRQ_LCD),
1da177e4 LT	218	};
	219
	220	static struct platform_device sa11x0fb_device = {
	221	.name = "sa11x0-fb",
	222	.id = -1,
	223	.dev = {
	224	.coherent_dma_mask = 0xffffffff,
	225	},
	226	.num_resources = ARRAY_SIZE(sa11x0fb_resources),
	227	.resource = sa11x0fb_resources,
	228	};
	229
e1b7a72a RK	230	void sa11x0_register_lcd(struct sa1100fb_mach_info *inf)
	231	{
	232	sa11x0_register_device(&sa11x0fb_device, inf);
	233	}
	234
1da177e4 LT	235	static struct platform_device sa11x0pcmcia_device = {
	236	.name = "sa11x0-pcmcia",
	237	.id = -1,
	238	};
	239
	240	static struct platform_device sa11x0mtd_device = {
bcc8f3e0	241	.name = "sa1100-mtd",
1da177e4 LT	242	.id = -1,
	243	};
	244
7a5b4e16 RK	245	void sa11x0_register_mtd(struct flash_platform_data *flash,
7a5b4e16 RK	246	struct resource *res, int nr)
1da177e4	247	{
14e66f76	248	flash->name = "sa1100";
1da177e4 LT	249	sa11x0mtd_device.resource = res;
1da177e4 LT	250	sa11x0mtd_device.num_resources = nr;
7a5b4e16	251	sa11x0_register_device(&sa11x0mtd_device, flash);
1da177e4 LT	252	}
	253
	254	static struct resource sa11x0ir_resources[] = {
a181099e RK	255	DEFINE_RES_MEM(__PREG(Ser2UTCR0), 0x24),
	256	DEFINE_RES_MEM(__PREG(Ser2HSCR0), 0x1c),
	257	DEFINE_RES_MEM(__PREG(Ser2HSCR2), 0x04),
	258	DEFINE_RES_IRQ(IRQ_Ser2ICP),
1da177e4 LT	259	};
	260
	261	static struct platform_device sa11x0ir_device = {
	262	.name = "sa11x0-ir",
	263	.id = -1,
	264	.num_resources = ARRAY_SIZE(sa11x0ir_resources),
	265	.resource = sa11x0ir_resources,
	266	};
	267
7a5b4e16	268	void sa11x0_register_irda(struct irda_platform_data *irda)
1da177e4	269	{
7a5b4e16	270	sa11x0_register_device(&sa11x0ir_device, irda);
1da177e4 LT	271	}
1da177e4 LT	272
3888c090	273	static struct resource sa1100_rtc_resources[] = {
9f9d27e3	274	DEFINE_RES_MEM(0x90010000, 0x40),
3888c090 HZ	275	DEFINE_RES_IRQ_NAMED(IRQ_RTC1Hz, "rtc 1Hz"),
	276	DEFINE_RES_IRQ_NAMED(IRQ_RTCAlrm, "rtc alarm"),
	277	};
	278
e842f1c8 RP	279	static struct platform_device sa11x0rtc_device = {
	280	.name = "sa1100-rtc",
	281	.id = -1,
3888c090 HZ	282	.num_resources = ARRAY_SIZE(sa1100_rtc_resources),
3888c090 HZ	283	.resource = sa1100_rtc_resources,
e842f1c8 RP	284	};
e842f1c8 RP	285
7931d92f	286	static struct resource sa11x0dma_resources[] = {
c2132010	287	DEFINE_RES_MEM(DMA_PHYS, DMA_SIZE),
7931d92f RK	288	DEFINE_RES_IRQ(IRQ_DMA0),
	289	DEFINE_RES_IRQ(IRQ_DMA1),
	290	DEFINE_RES_IRQ(IRQ_DMA2),
	291	DEFINE_RES_IRQ(IRQ_DMA3),
	292	DEFINE_RES_IRQ(IRQ_DMA4),
	293	DEFINE_RES_IRQ(IRQ_DMA5),
	294	};
	295
	296	static u64 sa11x0dma_dma_mask = DMA_BIT_MASK(32);
	297
	298	static struct platform_device sa11x0dma_device = {
	299	.name = "sa11x0-dma",
	300	.id = -1,
	301	.dev = {
	302	.dma_mask = &sa11x0dma_dma_mask,
	303	.coherent_dma_mask = 0xffffffff,
	304	},
	305	.num_resources = ARRAY_SIZE(sa11x0dma_resources),
	306	.resource = sa11x0dma_resources,
	307	};
	308
1da177e4 LT	309	static struct platform_device *sa11x0_devices[] __initdata = {
	310	&sa11x0udc_device,
	311	&sa11x0uart1_device,
	312	&sa11x0uart3_device,
1da177e4 LT	313	&sa11x0ssp_device,
1da177e4 LT	314	&sa11x0pcmcia_device,
e842f1c8	315	&sa11x0rtc_device,
7931d92f	316	&sa11x0dma_device,
1da177e4 LT	317	};
	318
	319	static int __init sa1100_init(void)
	320	{
	321	pm_power_off = sa1100_power_off;
1da177e4 LT	322	return platform_add_devices(sa11x0_devices, ARRAY_SIZE(sa11x0_devices));
	323	}
	324
	325	arch_initcall(sa1100_init);
	326
7fea1ba5 SG	327	void __init sa11x0_init_late(void)
	328	{
	329	sa11x0_pm_init();
	330	}
1da177e4 LT	331
	332	/*
	333	* Common I/O mapping:
	334	*
	335	* Typically, static virtual address mappings are as follow:
	336	*
	337	* 0xf0000000-0xf3ffffff: miscellaneous stuff (CPLDs, etc.)
	338	* 0xf4000000-0xf4ffffff: SA-1111
	339	* 0xf5000000-0xf5ffffff: reserved (used by cache flushing area)
	340	* 0xf6000000-0xfffeffff: reserved (internal SA1100 IO defined above)
	341	* 0xffff0000-0xffff0fff: SA1100 exception vectors
	342	* 0xffff2000-0xffff2fff: Minicache copy_user_page area
	343	*
	344	* Below 0xe8000000 is reserved for vm allocation.
	345	*
	346	* The machine specific code must provide the extra mapping beside the
	347	* default mapping provided here.
	348	*/
	349
	350	static struct map_desc standard_io_desc[] __initdata = {
bda03086	351	{ /* PCM */
92519d82 DS	352	.virtual = 0xf8000000,
	353	.pfn = __phys_to_pfn(0x80000000),
	354	.length = 0x00100000,
	355	.type = MT_DEVICE
	356	}, { /* SCM */
	357	.virtual = 0xfa000000,
	358	.pfn = __phys_to_pfn(0x90000000),
	359	.length = 0x00100000,
	360	.type = MT_DEVICE
	361	}, { /* MER */
	362	.virtual = 0xfc000000,
	363	.pfn = __phys_to_pfn(0xa0000000),
	364	.length = 0x00100000,
	365	.type = MT_DEVICE
	366	}, { /* LCD + DMA */
	367	.virtual = 0xfe000000,
	368	.pfn = __phys_to_pfn(0xb0000000),
	369	.length = 0x00200000,
	370	.type = MT_DEVICE
	371	},
1da177e4 LT	372	};
	373
	374	void __init sa1100_map_io(void)
	375	{
	376	iotable_init(standard_io_desc, ARRAY_SIZE(standard_io_desc));
	377	}
	378
7a8ca0a0 DES	379	void __init sa1100_timer_init(void)
	380	{
	381	pxa_timer_nodt_init(IRQ_OST0, io_p2v(0x90000000), 3686400);
	382	}
	383
85e6f097 DES	384	static struct resource irq_resource =
	385	DEFINE_RES_MEM_NAMED(0x90050000, SZ_64K, "irqs");
	386
	387	void __init sa1100_init_irq(void)
	388	{
	389	request_resource(&iomem_resource, &irq_resource);
	390
	391	sa11x0_init_irq_nodt(IRQ_GPIO0_SC, irq_resource.start);
	392
	393	sa1100_init_gpio();
198b51e8	394	sa11xx_clk_init();
85e6f097 DES	395	}
85e6f097 DES	396
1da177e4 LT	397	/*
	398	* Disable the memory bus request/grant signals on the SA1110 to
	399	* ensure that we don't receive spurious memory requests. We set
	400	* the MBGNT signal false to ensure the SA1111 doesn't own the
	401	* SDRAM bus.
	402	*/
80ea2065	403	void sa1110_mb_disable(void)
1da177e4 LT	404	{
	405	unsigned long flags;
	406
	407	local_irq_save(flags);
	408
	409	PGSR &= ~GPIO_MBGNT;
	410	GPCR = GPIO_MBGNT;
	411	GPDR = (GPDR & ~GPIO_MBREQ) \| GPIO_MBGNT;
	412
	413	GAFR &= ~(GPIO_MBGNT \| GPIO_MBREQ);
	414
	415	local_irq_restore(flags);
	416	}
	417
	418	/*
	419	* If the system is going to use the SA-1111 DMA engines, set up
	420	* the memory bus request/grant pins.
	421	*/
80ea2065	422	void sa1110_mb_enable(void)
1da177e4 LT	423	{
	424	unsigned long flags;
	425
	426	local_irq_save(flags);
	427
	428	PGSR &= ~GPIO_MBGNT;
	429	GPCR = GPIO_MBGNT;
	430	GPDR = (GPDR & ~GPIO_MBREQ) \| GPIO_MBGNT;
	431
	432	GAFR \|= (GPIO_MBGNT \| GPIO_MBREQ);
	433	TUCR \|= TUCR_MR;
	434
	435	local_irq_restore(flags);
	436	}
	437
982b465a DES	438	int sa11x0_gpio_set_wake(unsigned int gpio, unsigned int on)
	439	{
	440	if (on)
	441	PWER \|= BIT(gpio);
	442	else
	443	PWER &= ~BIT(gpio);
	444
	445	return 0;
	446	}
	447
	448	int sa11x0_sc_set_wake(unsigned int irq, unsigned int on)
	449	{
	450	if (BIT(irq) != IC_RTCAlrm)
	451	return -EINVAL;
	452
	453	if (on)
	454	PWER \|= PWER_RTC;
	455	else
	456	PWER &= ~PWER_RTC;
	457
	458	return 0;
	459	}