[deliverable/linux.git] / arch / arm / mm / proc-v7m.S

/*
 *  linux/arch/arm/mm/proc-v7m.S
 *
 *  Copyright (C) 2008 ARM Ltd.
 *  Copyright (C) 2001 Deep Blue Solutions Ltd.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 *  This is the "shell" of the ARMv7-M processor support.
 */
#include <linux/linkage.h>
#include <asm/assembler.h>
#include <asm/memory.h>
#include <asm/v7m.h>
#include "proc-macros.S"

ENTRY(cpu_v7m_proc_init)
	ret	lr
ENDPROC(cpu_v7m_proc_init)

ENTRY(cpu_v7m_proc_fin)
	ret	lr
ENDPROC(cpu_v7m_proc_fin)

/*
 *	cpu_v7m_reset(loc)
 *
 *	Perform a soft reset of the system.  Put the CPU into the
 *	same state as it would be if it had been reset, and branch
 *	to what would be the reset vector.
 *
 *	- loc   - location to jump to for soft reset
 */
	.align	5
ENTRY(cpu_v7m_reset)
	ret	r0
ENDPROC(cpu_v7m_reset)

/*
 *	cpu_v7m_do_idle()
 *
 *	Idle the processor (eg, wait for interrupt).
 *
 *	IRQs are already disabled.
 */
ENTRY(cpu_v7m_do_idle)
	wfi
	ret	lr
ENDPROC(cpu_v7m_do_idle)

ENTRY(cpu_v7m_dcache_clean_area)
	ret	lr
ENDPROC(cpu_v7m_dcache_clean_area)

/*
 * There is no MMU, so here is nothing to do.
 */
ENTRY(cpu_v7m_switch_mm)
	ret	lr
ENDPROC(cpu_v7m_switch_mm)

.globl	cpu_v7m_suspend_size
.equ	cpu_v7m_suspend_size, 0

#ifdef CONFIG_ARM_CPU_SUSPEND
ENTRY(cpu_v7m_do_suspend)
	ret	lr
ENDPROC(cpu_v7m_do_suspend)

ENTRY(cpu_v7m_do_resume)
	ret	lr
ENDPROC(cpu_v7m_do_resume)
#endif

ENTRY(cpu_cm7_dcache_clean_area)
	dcache_line_size r2, r3
	movw	r3, #:lower16:BASEADDR_V7M_SCB + V7M_SCB_DCCMVAC
	movt	r3, #:upper16:BASEADDR_V7M_SCB + V7M_SCB_DCCMVAC

1:	str	r0, [r3]		@ clean D entry
	add	r0, r0, r2
	subs	r1, r1, r2
	bhi	1b
	dsb
	ret	lr
ENDPROC(cpu_cm7_dcache_clean_area)

ENTRY(cpu_cm7_proc_fin)
	movw	r2, #:lower16:(BASEADDR_V7M_SCB + V7M_SCB_CCR)
	movt	r2, #:upper16:(BASEADDR_V7M_SCB + V7M_SCB_CCR)
	ldr	r0, [r2]
	bic	r0, r0, #(V7M_SCB_CCR_DC | V7M_SCB_CCR_IC)
	str	r0, [r2]
	ret	lr
ENDPROC(cpu_cm7_proc_fin)

	.section ".text.init", #alloc, #execinstr

__v7m_cm7_setup:
	mov	r8, #(V7M_SCB_CCR_DC | V7M_SCB_CCR_IC| V7M_SCB_CCR_BP)
	b	__v7m_setup_cont
/*
 *	__v7m_setup
 *
 *	This should be able to cover all ARMv7-M cores.
 */
__v7m_setup:
	mov	r8, 0

__v7m_setup_cont:
	@ Configure the vector table base address
	ldr	r0, =BASEADDR_V7M_SCB
	ldr	r12, =vector_table
	str	r12, [r0, V7M_SCB_VTOR]

	@ enable UsageFault, BusFault and MemManage fault.
	ldr	r5, [r0, #V7M_SCB_SHCSR]
	orr	r5, #(V7M_SCB_SHCSR_USGFAULTENA | V7M_SCB_SHCSR_BUSFAULTENA | V7M_SCB_SHCSR_MEMFAULTENA)
	str	r5, [r0, #V7M_SCB_SHCSR]

	@ Lower the priority of the SVC and PendSV exceptions
	mov	r5, #0x80000000
	str	r5, [r0, V7M_SCB_SHPR2]	@ set SVC priority
	mov	r5, #0x00800000
	str	r5, [r0, V7M_SCB_SHPR3]	@ set PendSV priority

	@ SVC to switch to handler mode. Notice that this requires sp to
	@ point to writeable memory because the processor saves
	@ some registers to the stack.
	badr	r1, 1f
	ldr	r5, [r12, #11 * 4]	@ read the SVC vector entry
	str	r1, [r12, #11 * 4]	@ write the temporary SVC vector entry
	dsb
	mov	r6, lr			@ save LR
	ldr	sp, =init_thread_union + THREAD_START_SP
	cpsie	i
	svc	#0
1:	cpsid	i
	str	r5, [r12, #11 * 4]	@ restore the original SVC vector entry
	mov	lr, r6			@ restore LR

	@ Special-purpose control register
	mov	r1, #1
	msr	control, r1		@ Thread mode has unpriviledged access

	@ Configure caches (if implemented)
	teq     r8, #0
	stmneia	r12, {r0-r6, lr}	@ v7m_invalidate_l1 touches r0-r6
	blne	v7m_invalidate_l1
	teq     r8, #0			@ re-evalutae condition
	ldmneia	r12, {r0-r6, lr}

	@ Configure the System Control Register to ensure 8-byte stack alignment
	@ Note the STKALIGN bit is either RW or RAO.
	ldr	r0, [r0, V7M_SCB_CCR]   @ system control register
	orr	r0, #V7M_SCB_CCR_STKALIGN
	orr	r0, r0, r8

	ret	lr
ENDPROC(__v7m_setup)

/*
 * Cortex-M7 processor functions
 */
	globl_equ	cpu_cm7_proc_init,	cpu_v7m_proc_init
	globl_equ	cpu_cm7_reset,		cpu_v7m_reset
	globl_equ	cpu_cm7_do_idle,	cpu_v7m_do_idle
	globl_equ	cpu_cm7_switch_mm,	cpu_v7m_switch_mm

	define_processor_functions v7m, dabort=nommu_early_abort, pabort=legacy_pabort, nommu=1
	define_processor_functions cm7, dabort=nommu_early_abort, pabort=legacy_pabort, nommu=1

	.section ".rodata"
	string cpu_arch_name, "armv7m"
	string cpu_elf_name "v7m"
	string cpu_v7m_name "ARMv7-M"

	.section ".proc.info.init", #alloc

.macro __v7m_proc name, initfunc, cache_fns = nop_cache_fns, hwcaps = 0,  proc_fns = v7m_processor_functions
	.long	0			/* proc_info_list.__cpu_mm_mmu_flags */
	.long	0			/* proc_info_list.__cpu_io_mmu_flags */
	initfn	\initfunc, \name
	.long	cpu_arch_name
	.long	cpu_elf_name
	.long	HWCAP_HALF | HWCAP_THUMB | HWCAP_FAST_MULT | \hwcaps
	.long	cpu_v7m_name
	.long   \proc_fns
	.long	0			/* proc_info_list.tlb */
	.long	0			/* proc_info_list.user */
	.long	\cache_fns
.endm

	/*
	 * Match ARM Cortex-M7 processor.
	 */
	.type	__v7m_cm7_proc_info, #object
__v7m_cm7_proc_info:
	.long	0x410fc270		/* ARM Cortex-M7 0xC27 */
	.long	0xff0ffff0		/* Mask off revision, patch release */
	__v7m_proc __v7m_cm7_proc_info, __v7m_cm7_setup, hwcaps = HWCAP_EDSP, cache_fns = v7m_cache_fns, proc_fns = cm7_processor_functions
	.size	__v7m_cm7_proc_info, . - __v7m_cm7_proc_info

	/*
	 * Match ARM Cortex-M4 processor.
	 */
	.type	__v7m_cm4_proc_info, #object
__v7m_cm4_proc_info:
	.long	0x410fc240		/* ARM Cortex-M4 0xC24 */
	.long	0xff0ffff0		/* Mask off revision, patch release */
	__v7m_proc __v7m_cm4_proc_info, __v7m_setup, hwcaps = HWCAP_EDSP
	.size	__v7m_cm4_proc_info, . - __v7m_cm4_proc_info

	/*
	 * Match ARM Cortex-M3 processor.
	 */
	.type	__v7m_cm3_proc_info, #object
__v7m_cm3_proc_info:
	.long	0x410fc230		/* ARM Cortex-M3 0xC23 */
	.long	0xff0ffff0		/* Mask off revision, patch release */
	__v7m_proc __v7m_cm3_proc_info, __v7m_setup
	.size	__v7m_cm3_proc_info, . - __v7m_cm3_proc_info

	/*
	 * Match any ARMv7-M processor core.
	 */
	.type	__v7m_proc_info, #object
__v7m_proc_info:
	.long	0x000f0000		@ Required ID value
	.long	0x000f0000		@ Mask for ID
	__v7m_proc __v7m_proc_info, __v7m_setup
	.size	__v7m_proc_info, . - __v7m_proc_info
Commit	Line	Data
55bdd694 CM	1	/*
	2	* linux/arch/arm/mm/proc-v7m.S
	3	*
	4	* Copyright (C) 2008 ARM Ltd.
	5	* Copyright (C) 2001 Deep Blue Solutions Ltd.
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*
	11	* This is the "shell" of the ARMv7-M processor support.
	12	*/
	13	#include <linux/linkage.h>
	14	#include <asm/assembler.h>
a4124e72	15	#include <asm/memory.h>
55bdd694 CM	16	#include <asm/v7m.h>
	17	#include "proc-macros.S"
	18
	19	ENTRY(cpu_v7m_proc_init)
6ebbf2ce	20	ret lr
55bdd694 CM	21	ENDPROC(cpu_v7m_proc_init)
	22
	23	ENTRY(cpu_v7m_proc_fin)
6ebbf2ce	24	ret lr
55bdd694 CM	25	ENDPROC(cpu_v7m_proc_fin)
	26
	27	/*
	28	* cpu_v7m_reset(loc)
	29	*
	30	* Perform a soft reset of the system. Put the CPU into the
	31	* same state as it would be if it had been reset, and branch
	32	* to what would be the reset vector.
	33	*
	34	* - loc - location to jump to for soft reset
	35	*/
	36	.align 5
	37	ENTRY(cpu_v7m_reset)
6ebbf2ce	38	ret r0
55bdd694 CM	39	ENDPROC(cpu_v7m_reset)
	40
	41	/*
	42	* cpu_v7m_do_idle()
	43	*
	44	* Idle the processor (eg, wait for interrupt).
	45	*
	46	* IRQs are already disabled.
	47	*/
	48	ENTRY(cpu_v7m_do_idle)
	49	wfi
6ebbf2ce	50	ret lr
55bdd694 CM	51	ENDPROC(cpu_v7m_do_idle)
	52
	53	ENTRY(cpu_v7m_dcache_clean_area)
6ebbf2ce	54	ret lr
55bdd694 CM	55	ENDPROC(cpu_v7m_dcache_clean_area)
	56
	57	/*
	58	* There is no MMU, so here is nothing to do.
	59	*/
	60	ENTRY(cpu_v7m_switch_mm)
6ebbf2ce	61	ret lr
55bdd694 CM	62	ENDPROC(cpu_v7m_switch_mm)
	63
	64	.globl cpu_v7m_suspend_size
	65	.equ cpu_v7m_suspend_size, 0
	66
	67	#ifdef CONFIG_ARM_CPU_SUSPEND
	68	ENTRY(cpu_v7m_do_suspend)
6ebbf2ce	69	ret lr
55bdd694 CM	70	ENDPROC(cpu_v7m_do_suspend)
	71
	72	ENTRY(cpu_v7m_do_resume)
6ebbf2ce	73	ret lr
55bdd694 CM	74	ENDPROC(cpu_v7m_do_resume)
	75	#endif
	76
6a8146f4 JA	77	ENTRY(cpu_cm7_dcache_clean_area)
	78	dcache_line_size r2, r3
	79	movw r3, #:lower16:BASEADDR_V7M_SCB + V7M_SCB_DCCMVAC
	80	movt r3, #:upper16:BASEADDR_V7M_SCB + V7M_SCB_DCCMVAC
	81
	82	1: str r0, [r3] @ clean D entry
	83	add r0, r0, r2
	84	subs r1, r1, r2
	85	bhi 1b
	86	dsb
	87	ret lr
	88	ENDPROC(cpu_cm7_dcache_clean_area)
	89
	90	ENTRY(cpu_cm7_proc_fin)
	91	movw r2, #:lower16:(BASEADDR_V7M_SCB + V7M_SCB_CCR)
	92	movt r2, #:upper16:(BASEADDR_V7M_SCB + V7M_SCB_CCR)
	93	ldr r0, [r2]
	94	bic r0, r0, #(V7M_SCB_CCR_DC \| V7M_SCB_CCR_IC)
	95	str r0, [r2]
	96	ret lr
	97	ENDPROC(cpu_cm7_proc_fin)
	98
55bdd694 CM	99	.section ".text.init", #alloc, #execinstr
55bdd694 CM	100
6a8146f4 JA	101	__v7m_cm7_setup:
	102	mov r8, #(V7M_SCB_CCR_DC \| V7M_SCB_CCR_IC\| V7M_SCB_CCR_BP)
	103	b __v7m_setup_cont
55bdd694 CM	104	/*
	105	* __v7m_setup
	106	*
	107	* This should be able to cover all ARMv7-M cores.
	108	*/
	109	__v7m_setup:
6a8146f4 JA	110	mov r8, 0
	111
	112	__v7m_setup_cont:
55bdd694 CM	113	@ Configure the vector table base address
	114	ldr r0, =BASEADDR_V7M_SCB
	115	ldr r12, =vector_table
	116	str r12, [r0, V7M_SCB_VTOR]
	117
	118	@ enable UsageFault, BusFault and MemManage fault.
	119	ldr r5, [r0, #V7M_SCB_SHCSR]
	120	orr r5, #(V7M_SCB_SHCSR_USGFAULTENA \| V7M_SCB_SHCSR_BUSFAULTENA \| V7M_SCB_SHCSR_MEMFAULTENA)
	121	str r5, [r0, #V7M_SCB_SHCSR]
	122
	123	@ Lower the priority of the SVC and PendSV exceptions
	124	mov r5, #0x80000000
	125	str r5, [r0, V7M_SCB_SHPR2] @ set SVC priority
	126	mov r5, #0x00800000
	127	str r5, [r0, V7M_SCB_SHPR3] @ set PendSV priority
	128
a4124e72 EG	129	@ SVC to switch to handler mode. Notice that this requires sp to
	130	@ point to writeable memory because the processor saves
	131	@ some registers to the stack.
14327c66	132	badr r1, 1f
55bdd694 CM	133	ldr r5, [r12, #11 * 4] @ read the SVC vector entry
55bdd694 CM	134	str r1, [r12, #11 * 4] @ write the temporary SVC vector entry
8e02676f	135	dsb
55bdd694	136	mov r6, lr @ save LR
a4124e72	137	ldr sp, =init_thread_union + THREAD_START_SP
55bdd694 CM	138	cpsie i
	139	svc #0
	140	1: cpsid i
	141	str r5, [r12, #11 * 4] @ restore the original SVC vector entry
	142	mov lr, r6 @ restore LR
55bdd694 CM	143
	144	@ Special-purpose control register
	145	mov r1, #1
	146	msr control, r1 @ Thread mode has unpriviledged access
	147
6a8146f4 JA	148	@ Configure caches (if implemented)
	149	teq r8, #0
	150	stmneia r12, {r0-r6, lr} @ v7m_invalidate_l1 touches r0-r6
	151	blne v7m_invalidate_l1
	152	teq r8, #0 @ re-evalutae condition
	153	ldmneia r12, {r0-r6, lr}
	154
55bdd694 CM	155	@ Configure the System Control Register to ensure 8-byte stack alignment
55bdd694 CM	156	@ Note the STKALIGN bit is either RW or RAO.
bc0ee9d2 JA	157	ldr r0, [r0, V7M_SCB_CCR] @ system control register
bc0ee9d2 JA	158	orr r0, #V7M_SCB_CCR_STKALIGN
6a8146f4 JA	159	orr r0, r0, r8
6a8146f4 JA	160
6ebbf2ce	161	ret lr
55bdd694 CM	162	ENDPROC(__v7m_setup)
55bdd694 CM	163
6a8146f4 JA	164	/*
	165	* Cortex-M7 processor functions
	166	*/
	167	globl_equ cpu_cm7_proc_init, cpu_v7m_proc_init
	168	globl_equ cpu_cm7_reset, cpu_v7m_reset
	169	globl_equ cpu_cm7_do_idle, cpu_v7m_do_idle
	170	globl_equ cpu_cm7_switch_mm, cpu_v7m_switch_mm
	171
55bdd694	172	define_processor_functions v7m, dabort=nommu_early_abort, pabort=legacy_pabort, nommu=1
6a8146f4	173	define_processor_functions cm7, dabort=nommu_early_abort, pabort=legacy_pabort, nommu=1
55bdd694 CM	174
	175	.section ".rodata"
	176	string cpu_arch_name, "armv7m"
	177	string cpu_elf_name "v7m"
	178	string cpu_v7m_name "ARMv7-M"
	179
bf35706f	180	.section ".proc.info.init", #alloc
55bdd694	181
c3a6bcbe JA	182	.macro __v7m_proc name, initfunc, cache_fns = nop_cache_fns, hwcaps = 0, proc_fns = v7m_processor_functions
	183	.long 0 /* proc_info_list.__cpu_mm_mmu_flags */
	184	.long 0 /* proc_info_list.__cpu_io_mmu_flags */
	185	initfn \initfunc, \name
	186	.long cpu_arch_name
	187	.long cpu_elf_name
	188	.long HWCAP_HALF \| HWCAP_THUMB \| HWCAP_FAST_MULT \| \hwcaps
	189	.long cpu_v7m_name
	190	.long \proc_fns
	191	.long 0 /* proc_info_list.tlb */
	192	.long 0 /* proc_info_list.user */
	193	.long \cache_fns
	194	.endm
	195
6a8146f4 JA	196	/*
	197	* Match ARM Cortex-M7 processor.
	198	*/
	199	.type __v7m_cm7_proc_info, #object
	200	__v7m_cm7_proc_info:
	201	.long 0x410fc270 /* ARM Cortex-M7 0xC27 */
	202	.long 0xff0ffff0 /* Mask off revision, patch release */
	203	__v7m_proc __v7m_cm7_proc_info, __v7m_cm7_setup, hwcaps = HWCAP_EDSP, cache_fns = v7m_cache_fns, proc_fns = cm7_processor_functions
	204	.size __v7m_cm7_proc_info, . - __v7m_cm7_proc_info
	205
c3a6bcbe JA	206	/*
	207	* Match ARM Cortex-M4 processor.
	208	*/
	209	.type __v7m_cm4_proc_info, #object
	210	__v7m_cm4_proc_info:
	211	.long 0x410fc240 /* ARM Cortex-M4 0xC24 */
	212	.long 0xff0ffff0 /* Mask off revision, patch release */
	213	__v7m_proc __v7m_cm4_proc_info, __v7m_setup, hwcaps = HWCAP_EDSP
	214	.size __v7m_cm4_proc_info, . - __v7m_cm4_proc_info
	215
	216	/*
	217	* Match ARM Cortex-M3 processor.
	218	*/
	219	.type __v7m_cm3_proc_info, #object
	220	__v7m_cm3_proc_info:
	221	.long 0x410fc230 /* ARM Cortex-M3 0xC23 */
	222	.long 0xff0ffff0 /* Mask off revision, patch release */
	223	__v7m_proc __v7m_cm3_proc_info, __v7m_setup
	224	.size __v7m_cm3_proc_info, . - __v7m_cm3_proc_info
	225
55bdd694 CM	226	/*
	227	* Match any ARMv7-M processor core.
	228	*/
	229	.type __v7m_proc_info, #object
	230	__v7m_proc_info:
	231	.long 0x000f0000 @ Required ID value
	232	.long 0x000f0000 @ Mask for ID
c3a6bcbe	233	__v7m_proc __v7m_proc_info, __v7m_setup
55bdd694 CM	234	.size __v7m_proc_info, . - __v7m_proc_info
55bdd694 CM	235