[deliverable/linux.git] / arch / arm64 / boot / dts / arm / juno-base.dtsi

	/*
	 *  Devices shared by all Juno boards
	 */

	memtimer: timer@2a810000 {
		compatible = "arm,armv7-timer-mem";
		reg = <0x0 0x2a810000 0x0 0x10000>;
		clock-frequency = <50000000>;
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;
		status = "disabled";
		frame@2a830000 {
			frame-number = <1>;
			interrupts = <0 60 4>;
			reg = <0x0 0x2a830000 0x0 0x10000>;
		};
	};

	mailbox: mhu@2b1f0000 {
		compatible = "arm,mhu", "arm,primecell";
		reg = <0x0 0x2b1f0000 0x0 0x1000>;
		interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "mhu_lpri_rx",
				  "mhu_hpri_rx";
		#mbox-cells = <1>;
		clocks = <&soc_refclk100mhz>;
		clock-names = "apb_pclk";
	};

	gic: interrupt-controller@2c010000 {
		compatible = "arm,gic-400", "arm,cortex-a15-gic";
		reg = <0x0 0x2c010000 0 0x1000>,
		      <0x0 0x2c02f000 0 0x2000>,
		      <0x0 0x2c04f000 0 0x2000>,
		      <0x0 0x2c06f000 0 0x2000>;
		#address-cells = <2>;
		#interrupt-cells = <3>;
		#size-cells = <2>;
		interrupt-controller;
		interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
		ranges = <0 0 0 0x2c1c0000 0 0x40000>;
		v2m_0: v2m@0 {
			compatible = "arm,gic-v2m-frame";
			msi-controller;
			reg = <0 0 0 0x1000>;
		};
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
	};

	/*
	 * Juno TRMs specify the size for these coresight components as 64K.
	 * The actual size is just 4K though 64K is reserved. Access to the
	 * unmapped reserved region results in a DECERR response.
	 */
	etf@20010000 {
		compatible = "arm,coresight-tmc", "arm,primecell";
		reg = <0 0x20010000 0 0x1000>;

		clocks = <&soc_smc50mhz>;
		clock-names = "apb_pclk";
		power-domains = <&scpi_devpd 0>;
		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			/* input port */
			port@0 {
				reg = <0>;
				etf_in_port: endpoint {
					slave-mode;
					remote-endpoint = <&main_funnel_out_port>;
				};
			};

			/* output port */
			port@1 {
				reg = <0>;
				etf_out_port: endpoint {
					remote-endpoint = <&replicator_in_port0>;
				};
			};
		};
	};

	tpiu@20030000 {
		compatible = "arm,coresight-tpiu", "arm,primecell";
		reg = <0 0x20030000 0 0x1000>;

		clocks = <&soc_smc50mhz>;
		clock-names = "apb_pclk";
		power-domains = <&scpi_devpd 0>;
		port {
			tpiu_in_port: endpoint {
				slave-mode;
				remote-endpoint = <&replicator_out_port0>;
			};
		};
	};

	main-funnel@20040000 {
		compatible = "arm,coresight-funnel", "arm,primecell";
		reg = <0 0x20040000 0 0x1000>;

		clocks = <&soc_smc50mhz>;
		clock-names = "apb_pclk";
		power-domains = <&scpi_devpd 0>;
		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port@0 {
				reg = <0>;
				main_funnel_out_port: endpoint {
					remote-endpoint = <&etf_in_port>;
				};
			};

			port@1 {
				reg = <0>;
				main_funnel_in_port0: endpoint {
					slave-mode;
					remote-endpoint = <&cluster0_funnel_out_port>;
				};
			};

			port@2 {
				reg = <1>;
				main_funnel_in_port1: endpoint {
					slave-mode;
					remote-endpoint = <&cluster1_funnel_out_port>;
				};
			};

		};
	};

	etr@20070000 {
		compatible = "arm,coresight-tmc", "arm,primecell";
		reg = <0 0x20070000 0 0x1000>;

		clocks = <&soc_smc50mhz>;
		clock-names = "apb_pclk";
		power-domains = <&scpi_devpd 0>;
		port {
			etr_in_port: endpoint {
				slave-mode;
				remote-endpoint = <&replicator_out_port1>;
			};
		};
	};

	etm0: etm@22040000 {
		compatible = "arm,coresight-etm4x", "arm,primecell";
		reg = <0 0x22040000 0 0x1000>;

		clocks = <&soc_smc50mhz>;
		clock-names = "apb_pclk";
		power-domains = <&scpi_devpd 0>;
		port {
			cluster0_etm0_out_port: endpoint {
				remote-endpoint = <&cluster0_funnel_in_port0>;
			};
		};
	};

	cluster0-funnel@220c0000 {
		compatible = "arm,coresight-funnel", "arm,primecell";
		reg = <0 0x220c0000 0 0x1000>;

		clocks = <&soc_smc50mhz>;
		clock-names = "apb_pclk";
		power-domains = <&scpi_devpd 0>;
		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port@0 {
				reg = <0>;
				cluster0_funnel_out_port: endpoint {
					remote-endpoint = <&main_funnel_in_port0>;
				};
			};

			port@1 {
				reg = <0>;
				cluster0_funnel_in_port0: endpoint {
					slave-mode;
					remote-endpoint = <&cluster0_etm0_out_port>;
				};
			};

			port@2 {
				reg = <1>;
				cluster0_funnel_in_port1: endpoint {
					slave-mode;
					remote-endpoint = <&cluster0_etm1_out_port>;
				};
			};
		};
	};

	etm1: etm@22140000 {
		compatible = "arm,coresight-etm4x", "arm,primecell";
		reg = <0 0x22140000 0 0x1000>;

		clocks = <&soc_smc50mhz>;
		clock-names = "apb_pclk";
		power-domains = <&scpi_devpd 0>;
		port {
			cluster0_etm1_out_port: endpoint {
				remote-endpoint = <&cluster0_funnel_in_port1>;
			};
		};
	};

	etm2: etm@23040000 {
		compatible = "arm,coresight-etm4x", "arm,primecell";
		reg = <0 0x23040000 0 0x1000>;

		clocks = <&soc_smc50mhz>;
		clock-names = "apb_pclk";
		power-domains = <&scpi_devpd 0>;
		port {
			cluster1_etm0_out_port: endpoint {
				remote-endpoint = <&cluster1_funnel_in_port0>;
			};
		};
	};

	cluster1-funnel@230c0000 {
		compatible = "arm,coresight-funnel", "arm,primecell";
		reg = <0 0x230c0000 0 0x1000>;

		clocks = <&soc_smc50mhz>;
		clock-names = "apb_pclk";
		power-domains = <&scpi_devpd 0>;
		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port@0 {
				reg = <0>;
				cluster1_funnel_out_port: endpoint {
					remote-endpoint = <&main_funnel_in_port1>;
				};
			};

			port@1 {
				reg = <0>;
				cluster1_funnel_in_port0: endpoint {
					slave-mode;
					remote-endpoint = <&cluster1_etm0_out_port>;
				};
			};

			port@2 {
				reg = <1>;
				cluster1_funnel_in_port1: endpoint {
					slave-mode;
					remote-endpoint = <&cluster1_etm1_out_port>;
				};
			};
			port@3 {
				reg = <2>;
				cluster1_funnel_in_port2: endpoint {
					slave-mode;
					remote-endpoint = <&cluster1_etm2_out_port>;
				};
			};
			port@4 {
				reg = <3>;
				cluster1_funnel_in_port3: endpoint {
					slave-mode;
					remote-endpoint = <&cluster1_etm3_out_port>;
				};
			};
		};
	};

	etm3: etm@23140000 {
		compatible = "arm,coresight-etm4x", "arm,primecell";
		reg = <0 0x23140000 0 0x1000>;

		clocks = <&soc_smc50mhz>;
		clock-names = "apb_pclk";
		power-domains = <&scpi_devpd 0>;
		port {
			cluster1_etm1_out_port: endpoint {
				remote-endpoint = <&cluster1_funnel_in_port1>;
			};
		};
	};

	etm4: etm@23240000 {
		compatible = "arm,coresight-etm4x", "arm,primecell";
		reg = <0 0x23240000 0 0x1000>;

		clocks = <&soc_smc50mhz>;
		clock-names = "apb_pclk";
		power-domains = <&scpi_devpd 0>;
		port {
			cluster1_etm2_out_port: endpoint {
				remote-endpoint = <&cluster1_funnel_in_port2>;
			};
		};
	};

	etm5: etm@23340000 {
		compatible = "arm,coresight-etm4x", "arm,primecell";
		reg = <0 0x23340000 0 0x1000>;

		clocks = <&soc_smc50mhz>;
		clock-names = "apb_pclk";
		power-domains = <&scpi_devpd 0>;
		port {
			cluster1_etm3_out_port: endpoint {
				remote-endpoint = <&cluster1_funnel_in_port3>;
			};
		};
	};

	coresight-replicator {
		/*
		 * Non-configurable replicators don't show up on the
		 * AMBA bus.  As such no need to add "arm,primecell".
		 */
		compatible = "arm,coresight-replicator";

		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			/* replicator output ports */
			port@0 {
				reg = <0>;
				replicator_out_port0: endpoint {
					remote-endpoint = <&tpiu_in_port>;
				};
			};

			port@1 {
				reg = <1>;
				replicator_out_port1: endpoint {
					remote-endpoint = <&etr_in_port>;
				};
			};

			/* replicator input port */
			port@2 {
				reg = <0>;
				replicator_in_port0: endpoint {
					slave-mode;
					remote-endpoint = <&etf_out_port>;
				};
			};
		};
	};

	sram: sram@2e000000 {
		compatible = "arm,juno-sram-ns", "mmio-sram";
		reg = <0x0 0x2e000000 0x0 0x8000>;

		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0x0 0x2e000000 0x8000>;

		cpu_scp_lpri: scp-shmem@0 {
			compatible = "arm,juno-scp-shmem";
			reg = <0x0 0x200>;
		};

		cpu_scp_hpri: scp-shmem@200 {
			compatible = "arm,juno-scp-shmem";
			reg = <0x200 0x200>;
		};
	};

	pcie_ctlr: pcie-controller@40000000 {
		compatible = "arm,juno-r1-pcie", "plda,xpressrich3-axi", "pci-host-ecam-generic";
		device_type = "pci";
		reg = <0 0x40000000 0 0x10000000>;	/* ECAM config space */
		bus-range = <0 255>;
		linux,pci-domain = <0>;
		#address-cells = <3>;
		#size-cells = <2>;
		dma-coherent;
		ranges = <0x01000000 0x00 0x5f800000 0x00 0x5f800000 0x0 0x00800000>,
			 <0x02000000 0x00 0x50000000 0x00 0x50000000 0x0 0x08000000>,
			 <0x42000000 0x40 0x00000000 0x40 0x00000000 0x1 0x00000000>;
		#interrupt-cells = <1>;
		interrupt-map-mask = <0 0 0 7>;
		interrupt-map = <0 0 0 1 &gic 0 0 0 136 4>,
				<0 0 0 2 &gic 0 0 0 137 4>,
				<0 0 0 3 &gic 0 0 0 138 4>,
				<0 0 0 4 &gic 0 0 0 139 4>;
		msi-parent = <&v2m_0>;
		status = "disabled";
	};

	scpi {
		compatible = "arm,scpi";
		mboxes = <&mailbox 1>;
		shmem = <&cpu_scp_hpri>;

		clocks {
			compatible = "arm,scpi-clocks";

			scpi_dvfs: scpi-dvfs {
				compatible = "arm,scpi-dvfs-clocks";
				#clock-cells = <1>;
				clock-indices = <0>, <1>, <2>;
				clock-output-names = "atlclk", "aplclk","gpuclk";
			};
			scpi_clk: scpi-clk {
				compatible = "arm,scpi-variable-clocks";
				#clock-cells = <1>;
				clock-indices = <3>;
				clock-output-names = "pxlclk";
			};
		};

		scpi_devpd: scpi-power-domains {
			compatible = "arm,scpi-power-domains";
			num-domains = <2>;
			#power-domain-cells = <1>;
		};

		scpi_sensors0: sensors {
			compatible = "arm,scpi-sensors";
			#thermal-sensor-cells = <1>;
		};
	};

	thermal-zones {
		pmic {
			polling-delay = <1000>;
			polling-delay-passive = <100>;
			thermal-sensors = <&scpi_sensors0 0>;
		};

		soc {
			polling-delay = <1000>;
			polling-delay-passive = <100>;
			thermal-sensors = <&scpi_sensors0 3>;
		};

		big_cluster_thermal_zone: big_cluster {
			polling-delay = <1000>;
			polling-delay-passive = <100>;
			thermal-sensors = <&scpi_sensors0 21>;
			status = "disabled";
		};

		little_cluster_thermal_zone: little_cluster {
			polling-delay = <1000>;
			polling-delay-passive = <100>;
			thermal-sensors = <&scpi_sensors0 22>;
			status = "disabled";
		};

		gpu0_thermal_zone: gpu0 {
			polling-delay = <1000>;
			polling-delay-passive = <100>;
			thermal-sensors = <&scpi_sensors0 23>;
			status = "disabled";
		};

		gpu1_thermal_zone: gpu1 {
			polling-delay = <1000>;
			polling-delay-passive = <100>;
			thermal-sensors = <&scpi_sensors0 24>;
			status = "disabled";
		};
	};

	/include/ "juno-clocks.dtsi"

	dma@7ff00000 {
		compatible = "arm,pl330", "arm,primecell";
		reg = <0x0 0x7ff00000 0 0x1000>;
		#dma-cells = <1>;
		#dma-channels = <8>;
		#dma-requests = <32>;
		interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&soc_faxiclk>;
		clock-names = "apb_pclk";
	};

	hdlcd@7ff50000 {
		compatible = "arm,hdlcd";
		reg = <0 0x7ff50000 0 0x1000>;
		interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&scpi_clk 3>;
		clock-names = "pxlclk";

		port {
			hdlcd1_output: hdlcd1-endpoint {
				remote-endpoint = <&tda998x_1_input>;
			};
		};
	};

	hdlcd@7ff60000 {
		compatible = "arm,hdlcd";
		reg = <0 0x7ff60000 0 0x1000>;
		interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&scpi_clk 3>;
		clock-names = "pxlclk";

		port {
			hdlcd0_output: hdlcd0-endpoint {
				remote-endpoint = <&tda998x_0_input>;
			};
		};
	};

	soc_uart0: uart@7ff80000 {
		compatible = "arm,pl011", "arm,primecell";
		reg = <0x0 0x7ff80000 0x0 0x1000>;
		interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&soc_uartclk>, <&soc_refclk100mhz>;
		clock-names = "uartclk", "apb_pclk";
	};

	i2c@7ffa0000 {
		compatible = "snps,designware-i2c";
		reg = <0x0 0x7ffa0000 0x0 0x1000>;
		#address-cells = <1>;
		#size-cells = <0>;
		interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
		clock-frequency = <400000>;
		i2c-sda-hold-time-ns = <500>;
		clocks = <&soc_smc50mhz>;

		hdmi-transmitter@70 {
			compatible = "nxp,tda998x";
			reg = <0x70>;
			port {
				tda998x_0_input: tda998x-0-endpoint {
					remote-endpoint = <&hdlcd0_output>;
				};
			};
		};

		hdmi-transmitter@71 {
			compatible = "nxp,tda998x";
			reg = <0x71>;
			port {
				tda998x_1_input: tda998x-1-endpoint {
					remote-endpoint = <&hdlcd1_output>;
				};
			};
		};
	};

	ohci@7ffb0000 {
		compatible = "generic-ohci";
		reg = <0x0 0x7ffb0000 0x0 0x10000>;
		interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&soc_usb48mhz>;
	};

	ehci@7ffc0000 {
		compatible = "generic-ehci";
		reg = <0x0 0x7ffc0000 0x0 0x10000>;
		interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&soc_usb48mhz>;
	};

	memory-controller@7ffd0000 {
		compatible = "arm,pl354", "arm,primecell";
		reg = <0 0x7ffd0000 0 0x1000>;
		interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&soc_smc50mhz>;
		clock-names = "apb_pclk";
	};

	memory@80000000 {
		device_type = "memory";
		/* last 16MB of the first memory area is reserved for secure world use by firmware */
		reg = <0x00000000 0x80000000 0x0 0x7f000000>,
		      <0x00000008 0x80000000 0x1 0x80000000>;
	};

	smb@08000000 {
		compatible = "simple-bus";
		#address-cells = <2>;
		#size-cells = <1>;
		ranges = <0 0 0 0x08000000 0x04000000>,
			 <1 0 0 0x14000000 0x04000000>,
			 <2 0 0 0x18000000 0x04000000>,
			 <3 0 0 0x1c000000 0x04000000>,
			 <4 0 0 0x0c000000 0x04000000>,
			 <5 0 0 0x10000000 0x04000000>;

		#interrupt-cells = <1>;
		interrupt-map-mask = <0 0 15>;
		interrupt-map = <0 0  0 &gic 0 0 0  68 IRQ_TYPE_LEVEL_HIGH>,
				<0 0  1 &gic 0 0 0  69 IRQ_TYPE_LEVEL_HIGH>,
				<0 0  2 &gic 0 0 0  70 IRQ_TYPE_LEVEL_HIGH>,
				<0 0  3 &gic 0 0 0 160 IRQ_TYPE_LEVEL_HIGH>,
				<0 0  4 &gic 0 0 0 161 IRQ_TYPE_LEVEL_HIGH>,
				<0 0  5 &gic 0 0 0 162 IRQ_TYPE_LEVEL_HIGH>,
				<0 0  6 &gic 0 0 0 163 IRQ_TYPE_LEVEL_HIGH>,
				<0 0  7 &gic 0 0 0 164 IRQ_TYPE_LEVEL_HIGH>,
				<0 0  8 &gic 0 0 0 165 IRQ_TYPE_LEVEL_HIGH>,
				<0 0  9 &gic 0 0 0 166 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 10 &gic 0 0 0 167 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 11 &gic 0 0 0 168 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 12 &gic 0 0 0 169 IRQ_TYPE_LEVEL_HIGH>;

		/include/ "juno-motherboard.dtsi"
	};

	site2: tlx@60000000 {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0 0x60000000 0x10000000>;
		#interrupt-cells = <1>;
		interrupt-map-mask = <0 0>;
		interrupt-map = <0 0 &gic 0 0 0 168 IRQ_TYPE_LEVEL_HIGH>;
	};
Commit	Line	Data
e8020874 LD	1	/*
	2	* Devices shared by all Juno boards
	3	*/
	4
79502355 LD	5	memtimer: timer@2a810000 {
	6	compatible = "arm,armv7-timer-mem";
	7	reg = <0x0 0x2a810000 0x0 0x10000>;
	8	clock-frequency = <50000000>;
	9	#address-cells = <2>;
	10	#size-cells = <2>;
	11	ranges;
	12	status = "disabled";
	13	frame@2a830000 {
	14	frame-number = <1>;
	15	interrupts = <0 60 4>;
	16	reg = <0x0 0x2a830000 0x0 0x10000>;
	17	};
	18	};
	19
ff9a6262 SH	20	mailbox: mhu@2b1f0000 {
	21	compatible = "arm,mhu", "arm,primecell";
	22	reg = <0x0 0x2b1f0000 0x0 0x1000>;
	23	interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
	24	<GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
	25	interrupt-names = "mhu_lpri_rx",
	26	"mhu_hpri_rx";
	27	#mbox-cells = <1>;
	28	clocks = <&soc_refclk100mhz>;
	29	clock-names = "apb_pclk";
	30	};
	31
e8020874 LD	32	gic: interrupt-controller@2c010000 {
	33	compatible = "arm,gic-400", "arm,cortex-a15-gic";
	34	reg = <0x0 0x2c010000 0 0x1000>,
	35	<0x0 0x2c02f000 0 0x2000>,
	36	<0x0 0x2c04f000 0 0x2000>,
	37	<0x0 0x2c06f000 0 0x2000>;
9e6f374f	38	#address-cells = <2>;
e8020874	39	#interrupt-cells = <3>;
9e6f374f	40	#size-cells = <2>;
e8020874 LD	41	interrupt-controller;
e8020874 LD	42	interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(6) \| IRQ_TYPE_LEVEL_HIGH)>;
9e6f374f LD	43	ranges = <0 0 0 0x2c1c0000 0 0x40000>;
	44	v2m_0: v2m@0 {
	45	compatible = "arm,gic-v2m-frame";
	46	msi-controller;
	47	reg = <0 0 0 0x1000>;
	48	};
e8020874 LD	49	};
	50
	51	timer {
	52	compatible = "arm,armv8-timer";
	53	interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) \| IRQ_TYPE_LEVEL_LOW)>,
	54	<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) \| IRQ_TYPE_LEVEL_LOW)>,
	55	<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) \| IRQ_TYPE_LEVEL_LOW)>,
	56	<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) \| IRQ_TYPE_LEVEL_LOW)>;
	57	};
	58
3e287cf6 SH	59	/*
	60	* Juno TRMs specify the size for these coresight components as 64K.
	61	* The actual size is just 4K though 64K is reserved. Access to the
	62	* unmapped reserved region results in a DECERR response.
	63	*/
	64	etf@20010000 {
	65	compatible = "arm,coresight-tmc", "arm,primecell";
	66	reg = <0 0x20010000 0 0x1000>;
	67
	68	clocks = <&soc_smc50mhz>;
	69	clock-names = "apb_pclk";
bdeaa21a	70	power-domains = <&scpi_devpd 0>;
3e287cf6 SH	71	ports {
	72	#address-cells = <1>;
	73	#size-cells = <0>;
	74
	75	/* input port */
	76	port@0 {
	77	reg = <0>;
	78	etf_in_port: endpoint {
	79	slave-mode;
	80	remote-endpoint = <&main_funnel_out_port>;
	81	};
	82	};
	83
	84	/* output port */
	85	port@1 {
	86	reg = <0>;
	87	etf_out_port: endpoint {
	88	remote-endpoint = <&replicator_in_port0>;
	89	};
	90	};
	91	};
	92	};
	93
	94	tpiu@20030000 {
	95	compatible = "arm,coresight-tpiu", "arm,primecell";
	96	reg = <0 0x20030000 0 0x1000>;
	97
	98	clocks = <&soc_smc50mhz>;
	99	clock-names = "apb_pclk";
bdeaa21a	100	power-domains = <&scpi_devpd 0>;
3e287cf6 SH	101	port {
	102	tpiu_in_port: endpoint {
	103	slave-mode;
	104	remote-endpoint = <&replicator_out_port0>;
	105	};
	106	};
	107	};
	108
	109	main-funnel@20040000 {
	110	compatible = "arm,coresight-funnel", "arm,primecell";
	111	reg = <0 0x20040000 0 0x1000>;
	112
	113	clocks = <&soc_smc50mhz>;
	114	clock-names = "apb_pclk";
bdeaa21a	115	power-domains = <&scpi_devpd 0>;
3e287cf6 SH	116	ports {
	117	#address-cells = <1>;
	118	#size-cells = <0>;
	119
	120	port@0 {
	121	reg = <0>;
	122	main_funnel_out_port: endpoint {
	123	remote-endpoint = <&etf_in_port>;
	124	};
	125	};
	126
	127	port@1 {
	128	reg = <0>;
	129	main_funnel_in_port0: endpoint {
	130	slave-mode;
	131	remote-endpoint = <&cluster0_funnel_out_port>;
	132	};
	133	};
	134
	135	port@2 {
	136	reg = <1>;
	137	main_funnel_in_port1: endpoint {
	138	slave-mode;
	139	remote-endpoint = <&cluster1_funnel_out_port>;
	140	};
	141	};
	142
	143	};
	144	};
	145
	146	etr@20070000 {
	147	compatible = "arm,coresight-tmc", "arm,primecell";
	148	reg = <0 0x20070000 0 0x1000>;
	149
	150	clocks = <&soc_smc50mhz>;
	151	clock-names = "apb_pclk";
bdeaa21a	152	power-domains = <&scpi_devpd 0>;
3e287cf6 SH	153	port {
	154	etr_in_port: endpoint {
	155	slave-mode;
	156	remote-endpoint = <&replicator_out_port1>;
	157	};
	158	};
	159	};
	160
	161	etm0: etm@22040000 {
	162	compatible = "arm,coresight-etm4x", "arm,primecell";
	163	reg = <0 0x22040000 0 0x1000>;
	164
	165	clocks = <&soc_smc50mhz>;
	166	clock-names = "apb_pclk";
bdeaa21a	167	power-domains = <&scpi_devpd 0>;
3e287cf6 SH	168	port {
	169	cluster0_etm0_out_port: endpoint {
	170	remote-endpoint = <&cluster0_funnel_in_port0>;
	171	};
	172	};
	173	};
	174
	175	cluster0-funnel@220c0000 {
	176	compatible = "arm,coresight-funnel", "arm,primecell";
	177	reg = <0 0x220c0000 0 0x1000>;
	178
	179	clocks = <&soc_smc50mhz>;
	180	clock-names = "apb_pclk";
bdeaa21a	181	power-domains = <&scpi_devpd 0>;
3e287cf6 SH	182	ports {
	183	#address-cells = <1>;
	184	#size-cells = <0>;
	185
	186	port@0 {
	187	reg = <0>;
	188	cluster0_funnel_out_port: endpoint {
	189	remote-endpoint = <&main_funnel_in_port0>;
	190	};
	191	};
	192
	193	port@1 {
	194	reg = <0>;
	195	cluster0_funnel_in_port0: endpoint {
	196	slave-mode;
	197	remote-endpoint = <&cluster0_etm0_out_port>;
	198	};
	199	};
	200
	201	port@2 {
	202	reg = <1>;
	203	cluster0_funnel_in_port1: endpoint {
	204	slave-mode;
	205	remote-endpoint = <&cluster0_etm1_out_port>;
	206	};
	207	};
	208	};
	209	};
	210
	211	etm1: etm@22140000 {
	212	compatible = "arm,coresight-etm4x", "arm,primecell";
	213	reg = <0 0x22140000 0 0x1000>;
	214
	215	clocks = <&soc_smc50mhz>;
	216	clock-names = "apb_pclk";
bdeaa21a	217	power-domains = <&scpi_devpd 0>;
3e287cf6 SH	218	port {
	219	cluster0_etm1_out_port: endpoint {
	220	remote-endpoint = <&cluster0_funnel_in_port1>;
	221	};
	222	};
	223	};
	224
	225	etm2: etm@23040000 {
	226	compatible = "arm,coresight-etm4x", "arm,primecell";
	227	reg = <0 0x23040000 0 0x1000>;
	228
	229	clocks = <&soc_smc50mhz>;
	230	clock-names = "apb_pclk";
bdeaa21a	231	power-domains = <&scpi_devpd 0>;
3e287cf6 SH	232	port {
	233	cluster1_etm0_out_port: endpoint {
	234	remote-endpoint = <&cluster1_funnel_in_port0>;
	235	};
	236	};
	237	};
	238
	239	cluster1-funnel@230c0000 {
	240	compatible = "arm,coresight-funnel", "arm,primecell";
	241	reg = <0 0x230c0000 0 0x1000>;
	242
	243	clocks = <&soc_smc50mhz>;
	244	clock-names = "apb_pclk";
bdeaa21a	245	power-domains = <&scpi_devpd 0>;
3e287cf6 SH	246	ports {
	247	#address-cells = <1>;
	248	#size-cells = <0>;
	249
	250	port@0 {
	251	reg = <0>;
	252	cluster1_funnel_out_port: endpoint {
	253	remote-endpoint = <&main_funnel_in_port1>;
	254	};
	255	};
	256
	257	port@1 {
	258	reg = <0>;
	259	cluster1_funnel_in_port0: endpoint {
	260	slave-mode;
	261	remote-endpoint = <&cluster1_etm0_out_port>;
	262	};
	263	};
	264
	265	port@2 {
	266	reg = <1>;
	267	cluster1_funnel_in_port1: endpoint {
	268	slave-mode;
	269	remote-endpoint = <&cluster1_etm1_out_port>;
	270	};
	271	};
	272	port@3 {
	273	reg = <2>;
	274	cluster1_funnel_in_port2: endpoint {
	275	slave-mode;
	276	remote-endpoint = <&cluster1_etm2_out_port>;
	277	};
	278	};
	279	port@4 {
	280	reg = <3>;
	281	cluster1_funnel_in_port3: endpoint {
	282	slave-mode;
	283	remote-endpoint = <&cluster1_etm3_out_port>;
	284	};
	285	};
	286	};
	287	};
	288
	289	etm3: etm@23140000 {
	290	compatible = "arm,coresight-etm4x", "arm,primecell";
	291	reg = <0 0x23140000 0 0x1000>;
	292
	293	clocks = <&soc_smc50mhz>;
	294	clock-names = "apb_pclk";
bdeaa21a	295	power-domains = <&scpi_devpd 0>;
3e287cf6 SH	296	port {
	297	cluster1_etm1_out_port: endpoint {
	298	remote-endpoint = <&cluster1_funnel_in_port1>;
	299	};
	300	};
	301	};
	302
	303	etm4: etm@23240000 {
	304	compatible = "arm,coresight-etm4x", "arm,primecell";
	305	reg = <0 0x23240000 0 0x1000>;
	306
	307	clocks = <&soc_smc50mhz>;
	308	clock-names = "apb_pclk";
bdeaa21a	309	power-domains = <&scpi_devpd 0>;
3e287cf6 SH	310	port {
	311	cluster1_etm2_out_port: endpoint {
	312	remote-endpoint = <&cluster1_funnel_in_port2>;
	313	};
	314	};
	315	};
	316
	317	etm5: etm@23340000 {
	318	compatible = "arm,coresight-etm4x", "arm,primecell";
	319	reg = <0 0x23340000 0 0x1000>;
	320
	321	clocks = <&soc_smc50mhz>;
	322	clock-names = "apb_pclk";
bdeaa21a	323	power-domains = <&scpi_devpd 0>;
3e287cf6 SH	324	port {
	325	cluster1_etm3_out_port: endpoint {
	326	remote-endpoint = <&cluster1_funnel_in_port3>;
	327	};
	328	};
	329	};
	330
	331	coresight-replicator {
	332	/*
	333	* Non-configurable replicators don't show up on the
	334	* AMBA bus. As such no need to add "arm,primecell".
	335	*/
	336	compatible = "arm,coresight-replicator";
	337
	338	ports {
	339	#address-cells = <1>;
	340	#size-cells = <0>;
	341
	342	/* replicator output ports */
	343	port@0 {
	344	reg = <0>;
	345	replicator_out_port0: endpoint {
	346	remote-endpoint = <&tpiu_in_port>;
	347	};
	348	};
	349
	350	port@1 {
	351	reg = <1>;
	352	replicator_out_port1: endpoint {
	353	remote-endpoint = <&etr_in_port>;
	354	};
	355	};
	356
	357	/* replicator input port */
	358	port@2 {
	359	reg = <0>;
	360	replicator_in_port0: endpoint {
	361	slave-mode;
	362	remote-endpoint = <&etf_out_port>;
	363	};
	364	};
	365	};
	366	};
	367
ff9a6262 SH	368	sram: sram@2e000000 {
	369	compatible = "arm,juno-sram-ns", "mmio-sram";
	370	reg = <0x0 0x2e000000 0x0 0x8000>;
	371
	372	#address-cells = <1>;
	373	#size-cells = <1>;
	374	ranges = <0 0x0 0x2e000000 0x8000>;
	375
	376	cpu_scp_lpri: scp-shmem@0 {
	377	compatible = "arm,juno-scp-shmem";
	378	reg = <0x0 0x200>;
	379	};
	380
	381	cpu_scp_hpri: scp-shmem@200 {
	382	compatible = "arm,juno-scp-shmem";
	383	reg = <0x200 0x200>;
	384	};
	385	};
	386
36582c60 SH	387	pcie_ctlr: pcie-controller@40000000 {
	388	compatible = "arm,juno-r1-pcie", "plda,xpressrich3-axi", "pci-host-ecam-generic";
	389	device_type = "pci";
	390	reg = <0 0x40000000 0 0x10000000>; /* ECAM config space */
	391	bus-range = <0 255>;
	392	linux,pci-domain = <0>;
	393	#address-cells = <3>;
	394	#size-cells = <2>;
	395	dma-coherent;
	396	ranges = <0x01000000 0x00 0x5f800000 0x00 0x5f800000 0x0 0x00800000>,
	397	<0x02000000 0x00 0x50000000 0x00 0x50000000 0x0 0x08000000>,
	398	<0x42000000 0x40 0x00000000 0x40 0x00000000 0x1 0x00000000>;
	399	#interrupt-cells = <1>;
	400	interrupt-map-mask = <0 0 0 7>;
	401	interrupt-map = <0 0 0 1 &gic 0 0 0 136 4>,
	402	<0 0 0 2 &gic 0 0 0 137 4>,
	403	<0 0 0 3 &gic 0 0 0 138 4>,
	404	<0 0 0 4 &gic 0 0 0 139 4>;
	405	msi-parent = <&v2m_0>;
	406	status = "disabled";
	407	};
	408
ff9a6262 SH	409	scpi {
	410	compatible = "arm,scpi";
	411	mboxes = <&mailbox 1>;
	412	shmem = <&cpu_scp_hpri>;
	413
	414	clocks {
	415	compatible = "arm,scpi-clocks";
	416
6d6acd14	417	scpi_dvfs: scpi-dvfs {
ff9a6262 SH	418	compatible = "arm,scpi-dvfs-clocks";
	419	#clock-cells = <1>;
	420	clock-indices = <0>, <1>, <2>;
	421	clock-output-names = "atlclk", "aplclk","gpuclk";
	422	};
6d6acd14	423	scpi_clk: scpi-clk {
ff9a6262 SH	424	compatible = "arm,scpi-variable-clocks";
ff9a6262 SH	425	#clock-cells = <1>;
9fd9288e LD	426	clock-indices = <3>;
9fd9288e LD	427	clock-output-names = "pxlclk";
ff9a6262 SH	428	};
ff9a6262 SH	429	};
dfacaf0e	430
bdeaa21a SH	431	scpi_devpd: scpi-power-domains {
	432	compatible = "arm,scpi-power-domains";
	433	num-domains = <2>;
	434	#power-domain-cells = <1>;
	435	};
	436
dfacaf0e PA	437	scpi_sensors0: sensors {
	438	compatible = "arm,scpi-sensors";
	439	#thermal-sensor-cells = <1>;
	440	};
ff9a6262 SH	441	};
ff9a6262 SH	442
f7b636a8 JM	443	thermal-zones {
	444	pmic {
	445	polling-delay = <1000>;
	446	polling-delay-passive = <100>;
	447	thermal-sensors = <&scpi_sensors0 0>;
	448	};
	449
	450	soc {
	451	polling-delay = <1000>;
	452	polling-delay-passive = <100>;
	453	thermal-sensors = <&scpi_sensors0 3>;
	454	};
	455
	456	big_cluster_thermal_zone: big_cluster {
	457	polling-delay = <1000>;
	458	polling-delay-passive = <100>;
	459	thermal-sensors = <&scpi_sensors0 21>;
	460	status = "disabled";
	461	};
	462
	463	little_cluster_thermal_zone: little_cluster {
	464	polling-delay = <1000>;
	465	polling-delay-passive = <100>;
	466	thermal-sensors = <&scpi_sensors0 22>;
	467	status = "disabled";
	468	};
	469
	470	gpu0_thermal_zone: gpu0 {
	471	polling-delay = <1000>;
	472	polling-delay-passive = <100>;
	473	thermal-sensors = <&scpi_sensors0 23>;
	474	status = "disabled";
	475	};
	476
	477	gpu1_thermal_zone: gpu1 {
	478	polling-delay = <1000>;
	479	polling-delay-passive = <100>;
	480	thermal-sensors = <&scpi_sensors0 24>;
	481	status = "disabled";
	482	};
	483	};
	484
e8020874 LD	485	/include/ "juno-clocks.dtsi"
	486
	487	dma@7ff00000 {
	488	compatible = "arm,pl330", "arm,primecell";
	489	reg = <0x0 0x7ff00000 0 0x1000>;
	490	#dma-cells = <1>;
	491	#dma-channels = <8>;
	492	#dma-requests = <32>;
	493	interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
	494	<GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
	495	<GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
	496	<GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
aeb2ee56	497	<GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
e8020874 LD	498	<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
	499	<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
	500	<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
	501	<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
	502	clocks = <&soc_faxiclk>;
	503	clock-names = "apb_pclk";
	504	};
	505
9fd9288e LD	506	hdlcd@7ff50000 {
	507	compatible = "arm,hdlcd";
	508	reg = <0 0x7ff50000 0 0x1000>;
	509	interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
	510	clocks = <&scpi_clk 3>;
	511	clock-names = "pxlclk";
	512
	513	port {
6d6acd14	514	hdlcd1_output: hdlcd1-endpoint {
9fd9288e LD	515	remote-endpoint = <&tda998x_1_input>;
	516	};
	517	};
	518	};
	519
	520	hdlcd@7ff60000 {
	521	compatible = "arm,hdlcd";
	522	reg = <0 0x7ff60000 0 0x1000>;
	523	interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
	524	clocks = <&scpi_clk 3>;
	525	clock-names = "pxlclk";
	526
	527	port {
6d6acd14	528	hdlcd0_output: hdlcd0-endpoint {
9fd9288e LD	529	remote-endpoint = <&tda998x_0_input>;
	530	};
	531	};
	532	};
	533
e8020874 LD	534	soc_uart0: uart@7ff80000 {
	535	compatible = "arm,pl011", "arm,primecell";
	536	reg = <0x0 0x7ff80000 0x0 0x1000>;
	537	interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
	538	clocks = <&soc_uartclk>, <&soc_refclk100mhz>;
	539	clock-names = "uartclk", "apb_pclk";
	540	};
	541
	542	i2c@7ffa0000 {
	543	compatible = "snps,designware-i2c";
	544	reg = <0x0 0x7ffa0000 0x0 0x1000>;
	545	#address-cells = <1>;
	546	#size-cells = <0>;
	547	interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
	548	clock-frequency = <400000>;
	549	i2c-sda-hold-time-ns = <500>;
	550	clocks = <&soc_smc50mhz>;
	551
9fd9288e	552	hdmi-transmitter@70 {
e8020874 LD	553	compatible = "nxp,tda998x";
e8020874 LD	554	reg = <0x70>;
9fd9288e	555	port {
6d6acd14	556	tda998x_0_input: tda998x-0-endpoint {
9fd9288e LD	557	remote-endpoint = <&hdlcd0_output>;
	558	};
	559	};
e8020874 LD	560	};
e8020874 LD	561
9fd9288e	562	hdmi-transmitter@71 {
e8020874 LD	563	compatible = "nxp,tda998x";
e8020874 LD	564	reg = <0x71>;
9fd9288e	565	port {
6d6acd14	566	tda998x_1_input: tda998x-1-endpoint {
9fd9288e LD	567	remote-endpoint = <&hdlcd1_output>;
	568	};
	569	};
e8020874 LD	570	};
	571	};
	572
	573	ohci@7ffb0000 {
	574	compatible = "generic-ohci";
	575	reg = <0x0 0x7ffb0000 0x0 0x10000>;
	576	interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
	577	clocks = <&soc_usb48mhz>;
	578	};
	579
	580	ehci@7ffc0000 {
	581	compatible = "generic-ehci";
	582	reg = <0x0 0x7ffc0000 0x0 0x10000>;
	583	interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
	584	clocks = <&soc_usb48mhz>;
	585	};
	586
	587	memory-controller@7ffd0000 {
	588	compatible = "arm,pl354", "arm,primecell";
	589	reg = <0 0x7ffd0000 0 0x1000>;
	590	interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
	591	<GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
	592	clocks = <&soc_smc50mhz>;
	593	clock-names = "apb_pclk";
	594	};
	595
	596	memory@80000000 {
	597	device_type = "memory";
	598	/* last 16MB of the first memory area is reserved for secure world use by firmware */
	599	reg = <0x00000000 0x80000000 0x0 0x7f000000>,
	600	<0x00000008 0x80000000 0x1 0x80000000>;
	601	};
	602
6d6acd14	603	smb@08000000 {
e8020874 LD	604	compatible = "simple-bus";
	605	#address-cells = <2>;
	606	#size-cells = <1>;
	607	ranges = <0 0 0 0x08000000 0x04000000>,
	608	<1 0 0 0x14000000 0x04000000>,
	609	<2 0 0 0x18000000 0x04000000>,
	610	<3 0 0 0x1c000000 0x04000000>,
	611	<4 0 0 0x0c000000 0x04000000>,
	612	<5 0 0 0x10000000 0x04000000>;
	613
	614	#interrupt-cells = <1>;
	615	interrupt-map-mask = <0 0 15>;
9e6f374f LD	616	interrupt-map = <0 0 0 &gic 0 0 0 68 IRQ_TYPE_LEVEL_HIGH>,
	617	<0 0 1 &gic 0 0 0 69 IRQ_TYPE_LEVEL_HIGH>,
	618	<0 0 2 &gic 0 0 0 70 IRQ_TYPE_LEVEL_HIGH>,
	619	<0 0 3 &gic 0 0 0 160 IRQ_TYPE_LEVEL_HIGH>,
	620	<0 0 4 &gic 0 0 0 161 IRQ_TYPE_LEVEL_HIGH>,
	621	<0 0 5 &gic 0 0 0 162 IRQ_TYPE_LEVEL_HIGH>,
	622	<0 0 6 &gic 0 0 0 163 IRQ_TYPE_LEVEL_HIGH>,
	623	<0 0 7 &gic 0 0 0 164 IRQ_TYPE_LEVEL_HIGH>,
	624	<0 0 8 &gic 0 0 0 165 IRQ_TYPE_LEVEL_HIGH>,
	625	<0 0 9 &gic 0 0 0 166 IRQ_TYPE_LEVEL_HIGH>,
	626	<0 0 10 &gic 0 0 0 167 IRQ_TYPE_LEVEL_HIGH>,
	627	<0 0 11 &gic 0 0 0 168 IRQ_TYPE_LEVEL_HIGH>,
	628	<0 0 12 &gic 0 0 0 169 IRQ_TYPE_LEVEL_HIGH>;
e8020874 LD	629
	630	/include/ "juno-motherboard.dtsi"
	631	};
f5f7e455 BS	632
	633	site2: tlx@60000000 {
	634	compatible = "simple-bus";
	635	#address-cells = <1>;
	636	#size-cells = <1>;
	637	ranges = <0 0 0x60000000 0x10000000>;
	638	#interrupt-cells = <1>;
	639	interrupt-map-mask = <0 0>;
	640	interrupt-map = <0 0 &gic 0 0 0 168 IRQ_TYPE_LEVEL_HIGH>;
	641	};