projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 796c2b35 LD |
1 | /* |
| 2 | * ARM Ltd. Juno Platform | |
| 3 | * | |
| 4 | * Copyright (c) 2015 ARM Ltd. | |
| 5 | * | |
| 6 | * This file is licensed under a dual GPLv2 or BSD license. | |
| 7 | */ | |
| 8 | ||
| 9 | /dts-v1/; | |
| 10 | ||
| 11 | #include <dt-bindings/interrupt-controller/arm-gic.h> | |
| 12 | ||
| 13 | / { | |
| 14 | model = "ARM Juno development board (r1)"; | |
| 15 | compatible = "arm,juno-r1", "arm,juno", "arm,vexpress"; | |
| 16 | interrupt-parent = <&gic>; | |
| 17 | #address-cells = <2>; | |
| 18 | #size-cells = <2>; | |
| 19 | ||
| 20 | aliases { | |
| 21 | serial0 = &soc_uart0; | |
| 22 | }; | |
| 23 | ||
| 24 | chosen { | |
| 25 | stdout-path = "serial0:115200n8"; | |
| 26 | }; | |
| 27 | ||
| 28 | psci { | |
| 29 | compatible = "arm,psci-0.2"; | |
| 30 | method = "smc"; | |
| 31 | }; | |
| 32 | ||
| 33 | cpus { | |
| 34 | #address-cells = <2>; | |
| 35 | #size-cells = <0>; | |
| 36 | ||
| 37 | A57_0: cpu@0 { | |
| 38 | compatible = "arm,cortex-a57","arm,armv8"; | |
| 39 | reg = <0x0 0x0>; | |
| 40 | device_type = "cpu"; | |
| 41 | enable-method = "psci"; | |
| 42 | next-level-cache = <&A57_L2>; | |
| 43 | }; | |
| 44 | ||
| 45 | A57_1: cpu@1 { | |
| 46 | compatible = "arm,cortex-a57","arm,armv8"; | |
| 47 | reg = <0x0 0x1>; | |
| 48 | device_type = "cpu"; | |
| 49 | enable-method = "psci"; | |
| 50 | next-level-cache = <&A57_L2>; | |
| 51 | }; | |
| 52 | ||
| 53 | A53_0: cpu@100 { | |
| 54 | compatible = "arm,cortex-a53","arm,armv8"; | |
| 55 | reg = <0x0 0x100>; | |
| 56 | device_type = "cpu"; | |
| 57 | enable-method = "psci"; | |
| 58 | next-level-cache = <&A53_L2>; | |
| 59 | }; | |
| 60 | ||
| 61 | A53_1: cpu@101 { | |
| 62 | compatible = "arm,cortex-a53","arm,armv8"; | |
| 63 | reg = <0x0 0x101>; | |
| 64 | device_type = "cpu"; | |
| 65 | enable-method = "psci"; | |
| 66 | next-level-cache = <&A53_L2>; | |
| 67 | }; | |
| 68 | ||
| 69 | A53_2: cpu@102 { | |
| 70 | compatible = "arm,cortex-a53","arm,armv8"; | |
| 71 | reg = <0x0 0x102>; | |
| 72 | device_type = "cpu"; | |
| 73 | enable-method = "psci"; | |
| 74 | next-level-cache = <&A53_L2>; | |
| 75 | }; | |
| 76 | ||
| 77 | A53_3: cpu@103 { | |
| 78 | compatible = "arm,cortex-a53","arm,armv8"; | |
| 79 | reg = <0x0 0x103>; | |
| 80 | device_type = "cpu"; | |
| 81 | enable-method = "psci"; | |
| 82 | next-level-cache = <&A53_L2>; | |
| 83 | }; | |
| 84 | ||
| 85 | A57_L2: l2-cache0 { | |
| 86 | compatible = "cache"; | |
| 87 | }; | |
| 88 | ||
| 89 | A53_L2: l2-cache1 { | |
| 90 | compatible = "cache"; | |
| 91 | }; | |
| 92 | }; | |
| 93 | ||
| 01a507a3 MR |
94 | pmu_a57 { |
| 95 | compatible = "arm,cortex-a57-pmu"; | |
| 796c2b35 | 96 | interrupts = <GIC_SPI 02 IRQ_TYPE_LEVEL_HIGH>, |
| 01a507a3 MR |
97 | <GIC_SPI 06 IRQ_TYPE_LEVEL_HIGH>; |
| 98 | interrupt-affinity = <&A57_0>, | |
| 99 | <&A57_1>; | |
| 100 | }; | |
| 101 | ||
| 102 | pmu_a53 { | |
| 103 | compatible = "arm,cortex-a53-pmu"; | |
| 104 | interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, | |
| 796c2b35 LD |
105 | <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, |
| 106 | <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, | |
| 107 | <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; | |
| 01a507a3 | 108 | interrupt-affinity = <&A53_0>, |
| 796c2b35 LD |
109 | <&A53_1>, |
| 110 | <&A53_2>, | |
| 111 | <&A53_3>; | |
| 112 | }; | |
| 113 | ||
| 114 | #include "juno-base.dtsi" | |
| 115 | ||
| 116 | }; | |
| 117 | ||
| 118 | &memtimer { | |
| 119 | status = "okay"; | |
| 120 | }; |