[deliverable/linux.git] / arch / arm64 / boot / dts / marvell / armada-ap806.dtsi

/*
 * Copyright (C) 2016 Marvell Technology Group Ltd.
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPLv2 or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 *  a) This library is free software; you can redistribute it and/or
 *     modify it under the terms of the GNU General Public License as
 *     published by the Free Software Foundation; either version 2 of the
 *     License, or (at your option) any later version.
 *
 *     This library is distributed in the hope that it will be useful,
 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *     GNU General Public License for more details.
 *
 * Or, alternatively,
 *
 *  b) Permission is hereby granted, free of charge, to any person
 *     obtaining a copy of this software and associated documentation
 *     files (the "Software"), to deal in the Software without
 *     restriction, including without limitation the rights to use,
 *     copy, modify, merge, publish, distribute, sublicense, and/or
 *     sell copies of the Software, and to permit persons to whom the
 *     Software is furnished to do so, subject to the following
 *     conditions:
 *
 *     The above copyright notice and this permission notice shall be
 *     included in all copies or substantial portions of the Software.
 *
 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 *     OTHER DEALINGS IN THE SOFTWARE.
 */

/*
 * Device Tree file for Marvell Armada AP806.
 */

#include <dt-bindings/interrupt-controller/arm-gic.h>

/dts-v1/;

/ {
	model = "Marvell Armada AP806";
	compatible = "marvell,armada-ap806";
	#address-cells = <2>;
	#size-cells = <2>;

	aliases {
		serial0 = &uart0;
		serial1 = &uart1;
	};

	psci {
		compatible = "arm,psci-0.2";
		method = "smc";
	};

	ap806 {
		#address-cells = <2>;
		#size-cells = <2>;
		compatible = "simple-bus";
		interrupt-parent = <&gic>;
		ranges;

		config-space {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "simple-bus";
			ranges = <0x0 0x0 0xf0000000 0x1000000>;

			gic: interrupt-controller@210000 {
				compatible = "arm,gic-400";
				#interrupt-cells = <3>;
				#address-cells = <1>;
				#size-cells = <1>;
				ranges;
				interrupt-controller;
				interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
				reg = <0x210000 0x10000>,
				      <0x220000 0x20000>,
				      <0x240000 0x20000>,
				      <0x260000 0x20000>;

				gic_v2m0: v2m@280000 {
					compatible = "arm,gic-v2m-frame";
					msi-controller;
					reg = <0x280000 0x1000>;
					arm,msi-base-spi = <160>;
					arm,msi-num-spis = <32>;
				};
				gic_v2m1: v2m@290000 {
					compatible = "arm,gic-v2m-frame";
					msi-controller;
					reg = <0x290000 0x1000>;
					arm,msi-base-spi = <192>;
					arm,msi-num-spis = <32>;
				};
				gic_v2m2: v2m@2a0000 {
					compatible = "arm,gic-v2m-frame";
					msi-controller;
					reg = <0x2a0000 0x1000>;
					arm,msi-base-spi = <224>;
					arm,msi-num-spis = <32>;
				};
				gic_v2m3: v2m@2b0000 {
					compatible = "arm,gic-v2m-frame";
					msi-controller;
					reg = <0x2b0000 0x1000>;
					arm,msi-base-spi = <256>;
					arm,msi-num-spis = <32>;
				};
			};

			timer {
				compatible = "arm,armv8-timer";
				interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
					     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
					     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
					     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
			};

			pmu {
				compatible = "arm,cortex-a72-pmu";
				interrupt-parent = <&pic>;
				interrupts = <17>;
			};

			odmi: odmi@300000 {
				compatible = "marvell,odmi-controller";
				interrupt-controller;
				msi-controller;
				marvell,odmi-frames = <4>;
				reg = <0x300000 0x4000>,
				      <0x304000 0x4000>,
				      <0x308000 0x4000>,
				      <0x30C000 0x4000>;
				marvell,spi-base = <128>, <136>, <144>, <152>;
			};

			pic: interrupt-controller@3f0100 {
				compatible = "marvell,armada-8k-pic";
				reg = <0x3f0100 0x10>;
				#interrupt-cells = <1>;
				interrupt-controller;
				interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
			};

			xor@400000 {
				compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
				reg = <0x400000 0x1000>,
				      <0x410000 0x1000>;
				msi-parent = <&gic_v2m0>;
				dma-coherent;
			};

			xor@420000 {
				compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
				reg = <0x420000 0x1000>,
				      <0x430000 0x1000>;
				msi-parent = <&gic_v2m0>;
				dma-coherent;
			};

			xor@440000 {
				compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
				reg = <0x440000 0x1000>,
				      <0x450000 0x1000>;
				msi-parent = <&gic_v2m0>;
				dma-coherent;
			};

			xor@460000 {
				compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
				reg = <0x460000 0x1000>,
				      <0x470000 0x1000>;
				msi-parent = <&gic_v2m0>;
				dma-coherent;
			};

			spi0: spi@510600 {
				compatible = "marvell,armada-380-spi";
				reg = <0x510600 0x50>;
				#address-cells = <1>;
				#size-cells = <0>;
				cell-index = <0>;
				interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&ap_syscon 3>;
				status = "disabled";
			};

			i2c0: i2c@511000 {
				compatible = "marvell,mv78230-i2c";
				reg = <0x511000 0x20>;
				#address-cells = <1>;
				#size-cells = <0>;
				interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
				timeout-ms = <1000>;
				clocks = <&ap_syscon 3>;
				status = "disabled";
			};

			uart0: serial@512000 {
				compatible = "snps,dw-apb-uart";
				reg = <0x512000 0x100>;
				reg-shift = <2>;
				interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
				reg-io-width = <1>;
				clocks = <&ap_syscon 3>;
				status = "disabled";
			};

			uart1: serial@512100 {
				compatible = "snps,dw-apb-uart";
				reg = <0x512100 0x100>;
				reg-shift = <2>;
				interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
				reg-io-width = <1>;
				clocks = <&ap_syscon 3>;
				status = "disabled";

			};

			ap_syscon: system-controller@6f4000 {
				compatible = "marvell,ap806-system-controller",
					     "syscon";
				#clock-cells = <1>;
				clock-output-names = "ap-cpu-cluster-0",
						     "ap-cpu-cluster-1",
						     "ap-fixed", "ap-mss";
				reg = <0x6f4000 0x1000>;
			};
		};
	};
};
Commit	Line	Data
ec7e5a56 TP	1	/*
	2	* Copyright (C) 2016 Marvell Technology Group Ltd.
	3	*
	4	* This file is dual-licensed: you can use it either under the terms
	5	* of the GPLv2 or the X11 license, at your option. Note that this dual
	6	* licensing only applies to this file, and not this project as a
	7	* whole.
	8	*
	9	* a) This library is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU General Public License as
	11	* published by the Free Software Foundation; either version 2 of the
	12	* License, or (at your option) any later version.
	13	*
	14	* This library is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* Or, alternatively,
	20	*
	21	* b) Permission is hereby granted, free of charge, to any person
	22	* obtaining a copy of this software and associated documentation
	23	* files (the "Software"), to deal in the Software without
	24	* restriction, including without limitation the rights to use,
	25	* copy, modify, merge, publish, distribute, sublicense, and/or
	26	* sell copies of the Software, and to permit persons to whom the
	27	* Software is furnished to do so, subject to the following
	28	* conditions:
	29	*
	30	* The above copyright notice and this permission notice shall be
	31	* included in all copies or substantial portions of the Software.
	32	*
	33	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	34	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
	35	* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	36	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
	37	* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
	38	* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	39	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	40	* OTHER DEALINGS IN THE SOFTWARE.
	41	*/
	42
	43	/*
	44	* Device Tree file for Marvell Armada AP806.
	45	*/
	46
	47	#include <dt-bindings/interrupt-controller/arm-gic.h>
	48
	49	/dts-v1/;
	50
	51	/ {
	52	model = "Marvell Armada AP806";
	53	compatible = "marvell,armada-ap806";
	54	#address-cells = <2>;
	55	#size-cells = <2>;
	56
bf151162 TP	57	aliases {
	58	serial0 = &uart0;
	59	serial1 = &uart1;
	60	};
	61
ec7e5a56 TP	62	psci {
	63	compatible = "arm,psci-0.2";
	64	method = "smc";
	65	};
	66
ec7e5a56 TP	67	ap806 {
	68	#address-cells = <2>;
	69	#size-cells = <2>;
	70	compatible = "simple-bus";
	71	interrupt-parent = <&gic>;
	72	ranges;
	73
	74	config-space {
	75	#address-cells = <1>;
	76	#size-cells = <1>;
	77	compatible = "simple-bus";
	78	ranges = <0x0 0x0 0xf0000000 0x1000000>;
	79
	80	gic: interrupt-controller@210000 {
	81	compatible = "arm,gic-400";
	82	#interrupt-cells = <3>;
	83	#address-cells = <1>;
	84	#size-cells = <1>;
	85	ranges;
	86	interrupt-controller;
	87	interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_HIGH)>;
	88	reg = <0x210000 0x10000>,
	89	<0x220000 0x20000>,
	90	<0x240000 0x20000>,
	91	<0x260000 0x20000>;
	92
	93	gic_v2m0: v2m@280000 {
	94	compatible = "arm,gic-v2m-frame";
	95	msi-controller;
	96	reg = <0x280000 0x1000>;
	97	arm,msi-base-spi = <160>;
	98	arm,msi-num-spis = <32>;
	99	};
	100	gic_v2m1: v2m@290000 {
	101	compatible = "arm,gic-v2m-frame";
	102	msi-controller;
	103	reg = <0x290000 0x1000>;
	104	arm,msi-base-spi = <192>;
	105	arm,msi-num-spis = <32>;
	106	};
	107	gic_v2m2: v2m@2a0000 {
	108	compatible = "arm,gic-v2m-frame";
	109	msi-controller;
	110	reg = <0x2a0000 0x1000>;
	111	arm,msi-base-spi = <224>;
	112	arm,msi-num-spis = <32>;
	113	};
	114	gic_v2m3: v2m@2b0000 {
	115	compatible = "arm,gic-v2m-frame";
	116	msi-controller;
	117	reg = <0x2b0000 0x1000>;
	118	arm,msi-base-spi = <256>;
	119	arm,msi-num-spis = <32>;
	120	};
	121	};
	122
	123	timer {
	124	compatible = "arm,armv8-timer";
585dcaca MZ	125	interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
	126	<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
	127	<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
	128	<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>;
ec7e5a56 TP	129	};
ec7e5a56 TP	130
98e45c16 TP	131	pmu {
	132	compatible = "arm,cortex-a72-pmu";
	133	interrupt-parent = <&pic>;
	134	interrupts = <17>;
	135	};
	136
ec7e5a56 TP	137	odmi: odmi@300000 {
	138	compatible = "marvell,odmi-controller";
	139	interrupt-controller;
	140	msi-controller;
	141	marvell,odmi-frames = <4>;
	142	reg = <0x300000 0x4000>,
	143	<0x304000 0x4000>,
	144	<0x308000 0x4000>,
	145	<0x30C000 0x4000>;
	146	marvell,spi-base = <128>, <136>, <144>, <152>;
	147	};
	148
98e45c16 TP	149	pic: interrupt-controller@3f0100 {
	150	compatible = "marvell,armada-8k-pic";
	151	reg = <0x3f0100 0x10>;
	152	#interrupt-cells = <1>;
	153	interrupt-controller;
	154	interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
	155	};
	156
1093e5f6	157	xor@400000 {
7eec6594	158	compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
b5ebfad8 TP	159	reg = <0x400000 0x1000>,
	160	<0x410000 0x1000>;
	161	msi-parent = <&gic_v2m0>;
	162	dma-coherent;
	163	};
	164
1093e5f6	165	xor@420000 {
7eec6594	166	compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
b5ebfad8 TP	167	reg = <0x420000 0x1000>,
	168	<0x430000 0x1000>;
	169	msi-parent = <&gic_v2m0>;
	170	dma-coherent;
	171	};
	172
1093e5f6	173	xor@440000 {
7eec6594	174	compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
b5ebfad8 TP	175	reg = <0x440000 0x1000>,
	176	<0x450000 0x1000>;
	177	msi-parent = <&gic_v2m0>;
	178	dma-coherent;
	179	};
	180
1093e5f6	181	xor@460000 {
7eec6594	182	compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
b5ebfad8 TP	183	reg = <0x460000 0x1000>,
	184	<0x470000 0x1000>;
	185	msi-parent = <&gic_v2m0>;
	186	dma-coherent;
	187	};
	188
ec7e5a56 TP	189	spi0: spi@510600 {
	190	compatible = "marvell,armada-380-spi";
	191	reg = <0x510600 0x50>;
	192	#address-cells = <1>;
	193	#size-cells = <0>;
	194	cell-index = <0>;
	195	interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
bb233a93	196	clocks = <&ap_syscon 3>;
ec7e5a56 TP	197	status = "disabled";
	198	};
	199
	200	i2c0: i2c@511000 {
d8b330a3	201	compatible = "marvell,mv78230-i2c";
ec7e5a56 TP	202	reg = <0x511000 0x20>;
	203	#address-cells = <1>;
	204	#size-cells = <0>;
	205	interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
	206	timeout-ms = <1000>;
bb233a93	207	clocks = <&ap_syscon 3>;
ec7e5a56 TP	208	status = "disabled";
	209	};
	210
037ad463	211	uart0: serial@512000 {
ec7e5a56 TP	212	compatible = "snps,dw-apb-uart";
	213	reg = <0x512000 0x100>;
	214	reg-shift = <2>;
	215	interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
	216	reg-io-width = <1>;
bb233a93	217	clocks = <&ap_syscon 3>;
ec7e5a56 TP	218	status = "disabled";
	219	};
	220
037ad463	221	uart1: serial@512100 {
ec7e5a56 TP	222	compatible = "snps,dw-apb-uart";
	223	reg = <0x512100 0x100>;
	224	reg-shift = <2>;
	225	interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
	226	reg-io-width = <1>;
bb233a93	227	clocks = <&ap_syscon 3>;
ec7e5a56 TP	228	status = "disabled";
	229
	230	};
	231
bb233a93 TP	232	ap_syscon: system-controller@6f4000 {
	233	compatible = "marvell,ap806-system-controller",
	234	"syscon";
	235	#clock-cells = <1>;
	236	clock-output-names = "ap-cpu-cluster-0",
	237	"ap-cpu-cluster-1",
	238	"ap-fixed", "ap-mss";
	239	reg = <0x6f4000 0x1000>;
d2b78fb6	240	};
ec7e5a56 TP	241	};
ec7e5a56 TP	242	};
ec7e5a56	243	};