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Merge remote-tracking branch 'block/for-next'
[deliverable/linux.git] / arch / arm64 / boot / dts / qcom / msm8916.dtsi
CommitLineData
57f0a7ea
KG		 1/*
2 * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#include <dt-bindings/interrupt-controller/arm-gic.h>
15#include <dt-bindings/clock/qcom,gcc-msm8916.h>
16#include <dt-bindings/reset/qcom,gcc-msm8916.h>
17
18/ {
19 model = "Qualcomm Technologies, Inc. MSM8916";
20 compatible = "qcom,msm8916";
21
22 interrupt-parent = <&intc>;
23
24 #address-cells = <2>;
25 #size-cells = <2>;
26
c4da5a56
SK		 27 aliases {
28 sdhc1 = &sdhc_1; /* SDC1 eMMC slot */
29 sdhc2 = &sdhc_2; /* SDC2 SD card slot */
30 };
57f0a7ea
KG		 31
32 chosen { };
33
34 memory {
35 device_type = "memory";
36 /* We expect the bootloader to fill in the reg */
37 reg = <0 0 0 0>;
38 };
39
a0ece657
AG		 40 reserved-memory {
41 #address-cells = <2>;
42 #size-cells = <2>;
43 ranges;
44
7258e10e
BA		 45 tz-apps@86000000 {
46 reg = <0x0 0x86000000 0x0 0x300000>;
a0ece657
AG		 47 no-map;
48 };
49
50 smem_mem: smem_region@86300000 {
7258e10e
BA		 51 reg = <0x0 0x86300000 0x0 0x100000>;
52 no-map;
53 };
54
55 hypervisor@86400000 {
56 reg = <0x0 0x86400000 0x0 0x100000>;
57 no-map;
58 };
59
60 tz@86500000 {
61 reg = <0x0 0x86500000 0x0 0x180000>;
62 no-map;
63 };
64
65 reserved@8668000 {
66 reg = <0x0 0x86680000 0x0 0x80000>;
67 no-map;
68 };
69
70 rmtfs@86700000 {
71 reg = <0x0 0x86700000 0x0 0xe0000>;
72 no-map;
73 };
74
75 rfsa@867e00000 {
76 reg = <0x0 0x867e0000 0x0 0x20000>;
77 no-map;
78 };
79
80 mpss@86800000 {
81 reg = <0x0 0x86800000 0x0 0x2b00000>;
82 no-map;
83 };
84
85 wcnss@89300000 {
86 reg = <0x0 0x89300000 0x0 0x600000>;
a0ece657
AG		 87 no-map;
88 };
d9a3e0c5
BA		 89
90 mba_mem: mba@8ea00000 {
91 no-map;
92 reg = <0 0x8ea00000 0 0x100000>;
93 };
a0ece657
AG		 94 };
95
57f0a7ea
KG		 96 cpus {
97 #address-cells = <1>;
98 #size-cells = <0>;
99
100 CPU0: cpu@0 {
101 device_type = "cpu";
102 compatible = "arm,cortex-a53", "arm,armv8";
103 reg = <0x0>;
0a9bcf4e 104 next-level-cache = <&L2_0>;
a0df399f
LI		 105 enable-method = "psci";
106 cpu-idle-states = <&CPU_SPC>;
57f0a7ea
KG		 107 };
108
109 CPU1: cpu@1 {
110 device_type = "cpu";
111 compatible = "arm,cortex-a53", "arm,armv8";
112 reg = <0x1>;
0a9bcf4e 113 next-level-cache = <&L2_0>;
a0df399f
LI		 114 enable-method = "psci";
115 cpu-idle-states = <&CPU_SPC>;
57f0a7ea
KG		 116 };
117
118 CPU2: cpu@2 {
119 device_type = "cpu";
120 compatible = "arm,cortex-a53", "arm,armv8";
121 reg = <0x2>;
0a9bcf4e 122 next-level-cache = <&L2_0>;
a0df399f
LI		 123 enable-method = "psci";
124 cpu-idle-states = <&CPU_SPC>;
57f0a7ea
KG		 125 };
126
127 CPU3: cpu@3 {
128 device_type = "cpu";
129 compatible = "arm,cortex-a53", "arm,armv8";
130 reg = <0x3>;
0a9bcf4e 131 next-level-cache = <&L2_0>;
a0df399f
LI		 132 enable-method = "psci";
133 cpu-idle-states = <&CPU_SPC>;
0a9bcf4e
SB		 134 };
135
136 L2_0: l2-cache {
137 compatible = "cache";
138 cache-level = <2>;
57f0a7ea 139 };
a0df399f
LI		 140
141 idle-states {
142 CPU_SPC: spc {
143 compatible = "arm,idle-state";
144 arm,psci-suspend-param = <0x40000002>;
145 entry-latency-us = <130>;
146 exit-latency-us = <150>;
147 min-residency-us = <2000>;
148 local-timer-stop;
149 };
150 };
151 };
152
153 psci {
154 compatible = "arm,psci-1.0";
155 method = "smc";
57f0a7ea
KG		 156 };
157
5daa7a60
SB		 158 pmu {
159 compatible = "arm,armv8-pmuv3";
160 interrupts = <GIC_PPI 7 GIC_CPU_MASK_SIMPLE(4)>;
161 };
162
4f6e4892
RN		 163 thermal-zones {
164 cpu-thermal0 {
165 polling-delay-passive = <250>;
166 polling-delay = <1000>;
167
168 thermal-sensors = <&tsens 4>;
169
170 trips {
171 cpu_alert0: trip0 {
172 temperature = <75000>;
173 hysteresis = <2000>;
174 type = "passive";
175 };
176 cpu_crit0: trip1 {
177 temperature = <110000>;
178 hysteresis = <2000>;
179 type = "critical";
180 };
181 };
182 };
183
184 cpu-thermal1 {
185 polling-delay-passive = <250>;
186 polling-delay = <1000>;
187
188 thermal-sensors = <&tsens 3>;
189
190 trips {
191 cpu_alert1: trip0 {
192 temperature = <75000>;
193 hysteresis = <2000>;
194 type = "passive";
195 };
196 cpu_crit1: trip1 {
197 temperature = <110000>;
198 hysteresis = <2000>;
199 type = "critical";
200 };
201 };
202 };
203
204 };
205
57f0a7ea
KG		 206 timer {
207 compatible = "arm,armv8-timer";
208 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
209 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
210 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
211 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
212 };
213
f4fb6aea
GD		 214 clocks {
215 xo_board: xo_board {
216 compatible = "fixed-clock";
217 #clock-cells = <0>;
218 clock-frequency = <19200000>;
219 };
220
221 sleep_clk: sleep_clk {
222 compatible = "fixed-clock";
223 #clock-cells = <0>;
224 clock-frequency = <32768>;
225 };
226 };
227
a0ece657
AG		 228 smem {
229 compatible = "qcom,smem";
230
231 memory-region = <&smem_mem>;
232 qcom,rpm-msg-ram = <&rpm_msg_ram>;
233
234 hwlocks = <&tcsr_mutex 3>;
235 };
236
ea49e164 237 firmware {
fb3013d3 238 scm: scm {
ea49e164
AG		 239 compatible = "qcom,scm";
240 clocks = <&gcc GCC_CRYPTO_CLK>, <&gcc GCC_CRYPTO_AXI_CLK>, <&gcc GCC_CRYPTO_AHB_CLK>;
241 clock-names = "core", "bus", "iface";
fb3013d3 242 #reset-cells = <1>;
ea49e164
AG		 243 };
244 };
245
57f0a7ea
KG		 246 soc: soc {
247 #address-cells = <1>;
248 #size-cells = <1>;
249 ranges = <0 0 0 0xffffffff>;
250 compatible = "simple-bus";
251
366655c9
II		 252 restart@4ab000 {
253 compatible = "qcom,pshold";
254 reg = <0x4ab000 0x4>;
255 };
256
a190a1ce 257 msmgpio: pinctrl@1000000 {
57f0a7ea
KG		 258 compatible = "qcom,msm8916-pinctrl";
259 reg = <0x1000000 0x300000>;
260 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
261 gpio-controller;
262 #gpio-cells = <2>;
263 interrupt-controller;
264 #interrupt-cells = <2>;
57f0a7ea
KG		 265 };
266
886c73ba 267 gcc: clock-controller@1800000 {
57f0a7ea
KG		 268 compatible = "qcom,gcc-msm8916";
269 #clock-cells = <1>;
270 #reset-cells = <1>;
89c7e671 271 #power-domain-cells = <1>;
57f0a7ea
KG		 272 reg = <0x1800000 0x80000>;
273 };
274
a0ece657
AG		 275 tcsr_mutex_regs: syscon@1905000 {
276 compatible = "syscon";
277 reg = <0x1905000 0x20000>;
278 };
279
e95c08f4
BA		 280 tcsr: syscon@1937000 {
281 compatible = "qcom,tcsr-msm8916", "syscon";
282 reg = <0x1937000 0x30000>;
283 };
284
a0ece657
AG		 285 tcsr_mutex: hwlock {
286 compatible = "qcom,tcsr-mutex";
287 syscon = <&tcsr_mutex_regs 0 0x1000>;
288 #hwlock-cells = <1>;
289 };
290
291 rpm_msg_ram: memory@60000 {
292 compatible = "qcom,rpm-msg-ram";
293 reg = <0x60000 0x8000>;
294 };
295
9f43020d
AG		 296 blsp1_uart1: serial@78af000 {
297 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
298 reg = <0x78af000 0x200>;
299 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
300 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
301 clock-names = "core", "iface";
d66dd9e0
II		 302 dmas = <&blsp_dma 1>, <&blsp_dma 0>;
303 dma-names = "rx", "tx";
9f43020d
AG		 304 status = "disabled";
305 };
306
8fd55d41
AG		 307 apcs: syscon@b011000 {
308 compatible = "syscon";
309 reg = <0x0b011000 0x1000>;
310 };
311
57f0a7ea
KG		 312 blsp1_uart2: serial@78b0000 {
313 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
314 reg = <0x78b0000 0x200>;
315 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
316 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
317 clock-names = "core", "iface";
d66dd9e0
II		 318 dmas = <&blsp_dma 3>, <&blsp_dma 2>;
319 dma-names = "rx", "tx";
57f0a7ea
KG		 320 status = "disabled";
321 };
a0e5fb10
II		 322
323 blsp_dma: dma@7884000 {
324 compatible = "qcom,bam-v1.7.0";
325 reg = <0x07884000 0x23000>;
326 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
327 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
328 clock-names = "bam_clk";
329 #dma-cells = <1>;
330 qcom,ee = <0>;
331 status = "disabled";
332 };
333
334 blsp_spi1: spi@78b5000 {
335 compatible = "qcom,spi-qup-v2.2.1";
336 reg = <0x078b5000 0x600>;
337 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
338 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
339 <&gcc GCC_BLSP1_AHB_CLK>;
340 clock-names = "core", "iface";
341 dmas = <&blsp_dma 5>, <&blsp_dma 4>;
342 dma-names = "rx", "tx";
343 pinctrl-names = "default", "sleep";
344 pinctrl-0 = <&spi1_default>;
345 pinctrl-1 = <&spi1_sleep>;
346 #address-cells = <1>;
347 #size-cells = <0>;
348 status = "disabled";
349 };
350
351 blsp_spi2: spi@78b6000 {
352 compatible = "qcom,spi-qup-v2.2.1";
353 reg = <0x078b6000 0x600>;
354 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
355 clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
356 <&gcc GCC_BLSP1_AHB_CLK>;
357 clock-names = "core", "iface";
358 dmas = <&blsp_dma 7>, <&blsp_dma 6>;
359 dma-names = "rx", "tx";
360 pinctrl-names = "default", "sleep";
361 pinctrl-0 = <&spi2_default>;
362 pinctrl-1 = <&spi2_sleep>;
363 #address-cells = <1>;
364 #size-cells = <0>;
365 status = "disabled";
366 };
367
368 blsp_spi3: spi@78b7000 {
369 compatible = "qcom,spi-qup-v2.2.1";
370 reg = <0x078b7000 0x600>;
371 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
372 clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>,
373 <&gcc GCC_BLSP1_AHB_CLK>;
374 clock-names = "core", "iface";
375 dmas = <&blsp_dma 9>, <&blsp_dma 8>;
376 dma-names = "rx", "tx";
377 pinctrl-names = "default", "sleep";
378 pinctrl-0 = <&spi3_default>;
379 pinctrl-1 = <&spi3_sleep>;
380 #address-cells = <1>;
381 #size-cells = <0>;
382 status = "disabled";
383 };
384
385 blsp_spi4: spi@78b8000 {
386 compatible = "qcom,spi-qup-v2.2.1";
387 reg = <0x078b8000 0x600>;
388 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
389 clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>,
390 <&gcc GCC_BLSP1_AHB_CLK>;
391 clock-names = "core", "iface";
392 dmas = <&blsp_dma 11>, <&blsp_dma 10>;
393 dma-names = "rx", "tx";
394 pinctrl-names = "default", "sleep";
395 pinctrl-0 = <&spi4_default>;
396 pinctrl-1 = <&spi4_sleep>;
397 #address-cells = <1>;
398 #size-cells = <0>;
399 status = "disabled";
400 };
401
402 blsp_spi5: spi@78b9000 {
403 compatible = "qcom,spi-qup-v2.2.1";
404 reg = <0x078b9000 0x600>;
405 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
406 clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>,
407 <&gcc GCC_BLSP1_AHB_CLK>;
408 clock-names = "core", "iface";
409 dmas = <&blsp_dma 13>, <&blsp_dma 12>;
410 dma-names = "rx", "tx";
411 pinctrl-names = "default", "sleep";
412 pinctrl-0 = <&spi5_default>;
413 pinctrl-1 = <&spi5_sleep>;
414 #address-cells = <1>;
415 #size-cells = <0>;
416 status = "disabled";
417 };
418
419 blsp_spi6: spi@78ba000 {
420 compatible = "qcom,spi-qup-v2.2.1";
421 reg = <0x078ba000 0x600>;
422 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
423 clocks = <&gcc GCC_BLSP1_QUP6_SPI_APPS_CLK>,
424 <&gcc GCC_BLSP1_AHB_CLK>;
425 clock-names = "core", "iface";
426 dmas = <&blsp_dma 15>, <&blsp_dma 14>;
427 dma-names = "rx", "tx";
428 pinctrl-names = "default", "sleep";
429 pinctrl-0 = <&spi6_default>;
430 pinctrl-1 = <&spi6_sleep>;
431 #address-cells = <1>;
432 #size-cells = <0>;
433 status = "disabled";
434 };
435
7f5b0921
SK		 436 blsp_i2c2: i2c@78b6000 {
437 compatible = "qcom,i2c-qup-v2.2.1";
438 reg = <0x78b6000 0x1000>;
439 interrupts = <GIC_SPI 96 0>;
440 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
441 <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
442 clock-names = "iface", "core";
443 pinctrl-names = "default", "sleep";
444 pinctrl-0 = <&i2c2_default>;
445 pinctrl-1 = <&i2c2_sleep>;
446 #address-cells = <1>;
447 #size-cells = <0>;
448 status = "disabled";
449 };
450
a0e5fb10
II		 451 blsp_i2c4: i2c@78b8000 {
452 compatible = "qcom,i2c-qup-v2.2.1";
453 reg = <0x78b8000 0x1000>;
454 interrupts = <GIC_SPI 98 0>;
455 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
456 <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>;
457 clock-names = "iface", "core";
458 pinctrl-names = "default", "sleep";
459 pinctrl-0 = <&i2c4_default>;
460 pinctrl-1 = <&i2c4_sleep>;
461 #address-cells = <1>;
462 #size-cells = <0>;
463 status = "disabled";
464 };
c4da5a56 465
7f5b0921
SK		 466 blsp_i2c6: i2c@78ba000 {
467 compatible = "qcom,i2c-qup-v2.2.1";
468 reg = <0x78ba000 0x1000>;
469 interrupts = <GIC_SPI 100 0>;
470 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
471 <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>;
472 clock-names = "iface", "core";
473 pinctrl-names = "default", "sleep";
474 pinctrl-0 = <&i2c6_default>;
475 pinctrl-1 = <&i2c6_sleep>;
476 #address-cells = <1>;
477 #size-cells = <0>;
478 status = "disabled";
479 };
480
3761a361
SK		 481 lpass: lpass@07708000 {
482 status = "disabled";
483 compatible = "qcom,lpass-cpu-apq8016";
484 clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>,
485 <&gcc GCC_ULTAUDIO_PCNOC_MPORT_CLK>,
486 <&gcc GCC_ULTAUDIO_PCNOC_SWAY_CLK>,
487 <&gcc GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK>,
488 <&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>,
489 <&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>,
490 <&gcc GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK>;
491
492 clock-names = "ahbix-clk",
493 "pcnoc-mport-clk",
494 "pcnoc-sway-clk",
495 "mi2s-bit-clk0",
496 "mi2s-bit-clk1",
497 "mi2s-bit-clk2",
498 "mi2s-bit-clk3";
499 #sound-dai-cells = <1>;
500
501 interrupts = <0 160 0>;
502 interrupt-names = "lpass-irq-lpaif";
503 reg = <0x07708000 0x10000>;
504 reg-names = "lpass-lpaif";
505 };
506
c4da5a56
SK		 507 sdhc_1: sdhci@07824000 {
508 compatible = "qcom,sdhci-msm-v4";
509 reg = <0x07824900 0x11c>, <0x07824000 0x800>;
510 reg-names = "hc_mem", "core_mem";
511
512 interrupts = <0 123 0>, <0 138 0>;
513 interrupt-names = "hc_irq", "pwr_irq";
514 clocks = <&gcc GCC_SDCC1_APPS_CLK>,
515 <&gcc GCC_SDCC1_AHB_CLK>;
516 clock-names = "core", "iface";
517 bus-width = <8>;
518 non-removable;
519 status = "disabled";
520 };
521
522 sdhc_2: sdhci@07864000 {
523 compatible = "qcom,sdhci-msm-v4";
524 reg = <0x07864900 0x11c>, <0x07864000 0x800>;
525 reg-names = "hc_mem", "core_mem";
526
527 interrupts = <0 125 0>, <0 221 0>;
528 interrupt-names = "hc_irq", "pwr_irq";
529 clocks = <&gcc GCC_SDCC2_APPS_CLK>,
530 <&gcc GCC_SDCC2_AHB_CLK>;
531 clock-names = "core", "iface";
532 bus-width = <4>;
533 status = "disabled";
534 };
59600865
II		 535
536 usb_dev: usb@78d9000 {
537 compatible = "qcom,ci-hdrc";
538 reg = <0x78d9000 0x400>;
539 dr_mode = "peripheral";
0f6625fd 540 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
59600865
II		 541 usb-phy = <&usb_otg>;
542 status = "disabled";
543 };
544
545 usb_host: ehci@78d9000 {
546 compatible = "qcom,ehci-host";
547 reg = <0x78d9000 0x400>;
0f6625fd 548 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
59600865
II		 549 usb-phy = <&usb_otg>;
550 status = "disabled";
551 };
552
553 usb_otg: phy@78d9000 {
554 compatible = "qcom,usb-otg-snps";
555 reg = <0x78d9000 0x400>;
0f6625fd
MZ		 556 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
557 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
59600865 558
a7b2466c 559 qcom,vdd-levels = <500000 1000000 1320000>;
59600865
II		 560 qcom,phy-init-sequence = <0x44 0x6B 0x24 0x13>;
561 dr_mode = "peripheral";
562 qcom,otg-control = <2>; // PMIC
2a0bc810 563 qcom,manual-pullup;
59600865
II		 564
565 clocks = <&gcc GCC_USB_HS_AHB_CLK>,
566 <&gcc GCC_USB_HS_SYSTEM_CLK>,
567 <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
568 clock-names = "iface", "core", "sleep";
569
570 resets = <&gcc GCC_USB2A_PHY_BCR>,
571 <&gcc GCC_USB_HS_BCR>;
572 reset-names = "phy", "link";
573 status = "disabled";
574 };
57f0a7ea
KG		 575
576 intc: interrupt-controller@b000000 {
577 compatible = "qcom,msm-qgic2";
578 interrupt-controller;
579 #interrupt-cells = <3>;
580 reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>;
581 };
582
583 timer@b020000 {
584 #address-cells = <1>;
585 #size-cells = <1>;
586 ranges;
587 compatible = "arm,armv7-timer-mem";
588 reg = <0xb020000 0x1000>;
589 clock-frequency = <19200000>;
590
591 frame@b021000 {
592 frame-number = <0>;
593 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
594 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
595 reg = <0xb021000 0x1000>,
596 <0xb022000 0x1000>;
597 };
598
599 frame@b023000 {
600 frame-number = <1>;
601 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
602 reg = <0xb023000 0x1000>;
603 status = "disabled";
604 };
605
606 frame@b024000 {
607 frame-number = <2>;
608 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
609 reg = <0xb024000 0x1000>;
610 status = "disabled";
611 };
612
613 frame@b025000 {
614 frame-number = <3>;
615 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
616 reg = <0xb025000 0x1000>;
617 status = "disabled";
618 };
619
620 frame@b026000 {
621 frame-number = <4>;
622 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
623 reg = <0xb026000 0x1000>;
624 status = "disabled";
625 };
626
627 frame@b027000 {
628 frame-number = <5>;
629 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
630 reg = <0xb027000 0x1000>;
631 status = "disabled";
632 };
633
634 frame@b028000 {
635 frame-number = <6>;
636 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
637 reg = <0xb028000 0x1000>;
638 status = "disabled";
639 };
640 };
232461ff
II		 641
642 spmi_bus: spmi@200f000 {
643 compatible = "qcom,spmi-pmic-arb";
644 reg = <0x200f000 0x001000>,
645 <0x2400000 0x400000>,
646 <0x2c00000 0x400000>,
647 <0x3800000 0x200000>,
648 <0x200a000 0x002100>;
649 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
650 interrupt-names = "periph_irq";
0f6625fd 651 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
232461ff
II		 652 qcom,ee = <0>;
653 qcom,channel = <0>;
654 #address-cells = <2>;
655 #size-cells = <0>;
656 interrupt-controller;
657 #interrupt-cells = <4>;
658 };
f6d24bf3
SV		 659
660 rng@22000 {
661 compatible = "qcom,prng";
662 reg = <0x00022000 0x200>;
663 clocks = <&gcc GCC_PRNG_AHB_CLK>;
664 clock-names = "core";
665 };
4f6e4892
RN		 666
667 qfprom: qfprom@5c000 {
668 compatible = "qcom,qfprom";
669 reg = <0x5c000 0x1000>;
670 #address-cells = <1>;
671 #size-cells = <1>;
672 tsens_caldata: caldata@d0 {
673 reg = <0xd0 0x8>;
674 };
675 tsens_calsel: calsel@ec {
676 reg = <0xec 0x4>;
677 };
678 };
679
680 tsens: thermal-sensor@4a8000 {
681 compatible = "qcom,msm8916-tsens";
682 reg = <0x4a8000 0x2000>;
683 nvmem-cells = <&tsens_caldata>, <&tsens_calsel>;
684 nvmem-cell-names = "calib", "calib_sel";
685 #thermal-sensor-cells = <1>;
686 };
305410ff
AT		 687
688 mdss: mdss@1a00000 {
689 compatible = "qcom,mdss";
690 reg = <0x1a00000 0x1000>,
691 <0x1ac8000 0x3000>;
692 reg-names = "mdss_phys", "vbif_phys";
693
694 power-domains = <&gcc MDSS_GDSC>;
695
696 clocks = <&gcc GCC_MDSS_AHB_CLK>,
697 <&gcc GCC_MDSS_AXI_CLK>,
698 <&gcc GCC_MDSS_VSYNC_CLK>;
699 clock-names = "iface_clk",
700 "bus_clk",
701 "vsync_clk";
702
703 interrupts = <0 72 0>;
704
705 interrupt-controller;
706 #interrupt-cells = <1>;
707
708 #address-cells = <1>;
709 #size-cells = <1>;
710 ranges;
711
712 mdp: mdp@1a01000 {
713 compatible = "qcom,mdp5";
714 reg = <0x1a01000 0x90000>;
715 reg-names = "mdp_phys";
716
717 interrupt-parent = <&mdss>;
718 interrupts = <0 0>;
719
720 clocks = <&gcc GCC_MDSS_AHB_CLK>,
721 <&gcc GCC_MDSS_AXI_CLK>,
722 <&gcc GCC_MDSS_MDP_CLK>,
723 <&gcc GCC_MDSS_VSYNC_CLK>;
724 clock-names = "iface_clk",
725 "bus_clk",
726 "core_clk",
727 "vsync_clk";
728
729 ports {
730 #address-cells = <1>;
731 #size-cells = <0>;
732
733 port@0 {
734 reg = <0>;
735 mdp5_intf1_out: endpoint {
736 remote-endpoint = <&dsi0_in>;
737 };
738 };
739 };
740 };
741
742 dsi0: dsi@1a98000 {
743 compatible = "qcom,mdss-dsi-ctrl";
744 reg = <0x1a98000 0x25c>;
745 reg-names = "dsi_ctrl";
746
747 interrupt-parent = <&mdss>;
748 interrupts = <4 0>;
749
750 assigned-clocks = <&gcc BYTE0_CLK_SRC>,
751 <&gcc PCLK0_CLK_SRC>;
752 assigned-clock-parents = <&dsi_phy0 0>,
753 <&dsi_phy0 1>;
754
755 clocks = <&gcc GCC_MDSS_MDP_CLK>,
756 <&gcc GCC_MDSS_AHB_CLK>,
757 <&gcc GCC_MDSS_AXI_CLK>,
758 <&gcc GCC_MDSS_BYTE0_CLK>,
759 <&gcc GCC_MDSS_PCLK0_CLK>,
760 <&gcc GCC_MDSS_ESC0_CLK>;
761 clock-names = "mdp_core_clk",
762 "iface_clk",
763 "bus_clk",
764 "byte_clk",
765 "pixel_clk",
766 "core_clk";
767 phys = <&dsi_phy0>;
768 phy-names = "dsi-phy";
769
770 ports {
771 #address-cells = <1>;
772 #size-cells = <0>;
773
774 port@0 {
775 reg = <0>;
776 dsi0_in: endpoint {
777 remote-endpoint = <&mdp5_intf1_out>;
778 };
779 };
780
781 port@1 {
782 reg = <1>;
783 dsi0_out: endpoint {
784 };
785 };
786 };
787 };
788
789 dsi_phy0: dsi-phy@1a98300 {
790 compatible = "qcom,dsi-phy-28nm-lp";
791 reg = <0x1a98300 0xd4>,
792 <0x1a98500 0x280>,
793 <0x1a98780 0x30>;
794 reg-names = "dsi_pll",
795 "dsi_phy",
796 "dsi_phy_regulator";
797
798 #clock-cells = <1>;
799
800 clocks = <&gcc GCC_MDSS_AHB_CLK>;
801 clock-names = "iface_clk";
802 };
803 };
57f0a7ea 804 };
8fd55d41
AG		 805
806 smd {
807 compatible = "qcom,smd";
808
809 rpm {
810 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
811 qcom,ipc = <&apcs 8 0>;
812 qcom,smd-edge = <15>;
813
814 rpm_requests {
815 compatible = "qcom,rpm-msm8916";
816 qcom,smd-channels = "rpm_requests";
9e1dfb85 817
e2841db7
GD		 818 rpmcc: qcom,rpmcc {
819 compatible = "qcom,rpmcc-msm8916", "qcom,rpmcc";
820 #clock-cells = <1>;
821 };
822
0ba7da26 823 smd_rpm_regulators: pm8916-regulators {
9e1dfb85
AG		 824 compatible = "qcom,rpm-pm8916-regulators";
825
826 pm8916_s1: s1 {};
9e1dfb85
AG		 827 pm8916_s3: s3 {};
828 pm8916_s4: s4 {};
829
830 pm8916_l1: l1 {};
831 pm8916_l2: l2 {};
832 pm8916_l3: l3 {};
833 pm8916_l4: l4 {};
834 pm8916_l5: l5 {};
835 pm8916_l6: l6 {};
836 pm8916_l7: l7 {};
837 pm8916_l8: l8 {};
838 pm8916_l9: l9 {};
839 pm8916_l10: l10 {};
840 pm8916_l11: l11 {};
841 pm8916_l12: l12 {};
842 pm8916_l13: l13 {};
843 pm8916_l14: l14 {};
844 pm8916_l15: l15 {};
845 pm8916_l16: l16 {};
846 pm8916_l17: l17 {};
847 pm8916_l18: l18 {};
848 };
8fd55d41
AG		 849 };
850 };
851 };
1fb47e0a
BA		 852
853 hexagon-smp2p {
854 compatible = "qcom,smp2p";
855 qcom,smem = <435>, <428>;
856
857 interrupts = <0 27 IRQ_TYPE_EDGE_RISING>;
858
859 qcom,ipc = <&apcs 8 14>;
860
861 qcom,local-pid = <0>;
862 qcom,remote-pid = <1>;
863
864 hexagon_smp2p_out: master-kernel {
865 qcom,entry-name = "master-kernel";
866
867 #qcom,smem-state-cells = <1>;
868 };
869
870 hexagon_smp2p_in: slave-kernel {
871 qcom,entry-name = "slave-kernel";
872
873 interrupt-controller;
874 #interrupt-cells = <2>;
875 };
876 };
877
878 wcnss-smp2p {
879 compatible = "qcom,smp2p";
880 qcom,smem = <451>, <431>;
881
882 interrupts = <0 143 IRQ_TYPE_EDGE_RISING>;
883
884 qcom,ipc = <&apcs 8 18>;
885
886 qcom,local-pid = <0>;
887 qcom,remote-pid = <4>;
888
889 wcnss_smp2p_out: master-kernel {
890 qcom,entry-name = "master-kernel";
891
892 #qcom,smem-state-cells = <1>;
893 };
894
895 wcnss_smp2p_in: slave-kernel {
896 qcom,entry-name = "slave-kernel";
897
898 interrupt-controller;
899 #interrupt-cells = <2>;
900 };
901 };
902
903 smsm {
904 compatible = "qcom,smsm";
905
906 #address-cells = <1>;
907 #size-cells = <0>;
908
909 qcom,ipc-1 = <&apcs 0 13>;
910 qcom,ipc-6 = <&apcs 0 19>;
911
912 apps_smsm: apps@0 {
913 reg = <0>;
914
915 #qcom,smem-state-cells = <1>;
916 };
917
918 hexagon_smsm: hexagon@1 {
919 reg = <1>;
920 interrupts = <0 26 IRQ_TYPE_EDGE_RISING>;
921
922 interrupt-controller;
923 #interrupt-cells = <2>;
924 };
925
926 wcnss_smsm: wcnss@6 {
927 reg = <6>;
928 interrupts = <0 144 IRQ_TYPE_EDGE_RISING>;
929
930 interrupt-controller;
931 #interrupt-cells = <2>;
932 };
933 };
57f0a7ea 934};
1b08a582
II		 935
936#include "msm8916-pins.dtsi"
Linux kernel - Deliverables
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