projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 1561f207 SH |
1 | /* |
| 2 | * Device Tree Source for the r8a7796 SoC | |
| 3 | * | |
| 4 | * Copyright (C) 2016 Renesas Electronics Corp. | |
| 5 | * | |
| 6 | * This file is licensed under the terms of the GNU General Public License | |
| 7 | * version 2. This program is licensed "as is" without any warranty of any | |
| 8 | * kind, whether express or implied. | |
| 9 | */ | |
| 10 | ||
| 11 | #include <dt-bindings/clock/r8a7796-cpg-mssr.h> | |
| 12 | #include <dt-bindings/interrupt-controller/arm-gic.h> | |
| 56aebae0 | 13 | #include <dt-bindings/power/r8a7796-sysc.h> |
| 1561f207 SH |
14 | |
| 15 | / { | |
| 16 | compatible = "renesas,r8a7796"; | |
| 17 | #address-cells = <2>; | |
| 18 | #size-cells = <2>; | |
| 19 | ||
| 20 | psci { | |
| 21 | compatible = "arm,psci-0.2"; | |
| 22 | method = "smc"; | |
| 23 | }; | |
| 24 | ||
| 25 | cpus { | |
| 26 | #address-cells = <1>; | |
| 27 | #size-cells = <0>; | |
| 28 | ||
| 29 | /* 1 core only at this point */ | |
| 30 | a57_0: cpu@0 { | |
| 31 | compatible = "arm,cortex-a57", "arm,armv8"; | |
| 32 | reg = <0x0>; | |
| 33 | device_type = "cpu"; | |
| 56aebae0 | 34 | power-domains = <&sysc R8A7796_PD_CA57_CPU0>; |
| 1561f207 SH |
35 | next-level-cache = <&L2_CA57>; |
| 36 | enable-method = "psci"; | |
| 37 | }; | |
| 38 | ||
| 39 | L2_CA57: cache-controller@0 { | |
| 40 | compatible = "cache"; | |
| 41 | reg = <0>; | |
| 56aebae0 | 42 | power-domains = <&sysc R8A7796_PD_CA57_SCU>; |
| 1561f207 SH |
43 | cache-unified; |
| 44 | cache-level = <2>; | |
| 45 | }; | |
| 46 | }; | |
| 47 | ||
| 48 | extal_clk: extal { | |
| 49 | compatible = "fixed-clock"; | |
| 50 | #clock-cells = <0>; | |
| 51 | /* This value must be overridden by the board */ | |
| 52 | clock-frequency = <0>; | |
| 53 | }; | |
| 54 | ||
| 55 | extalr_clk: extalr { | |
| 56 | compatible = "fixed-clock"; | |
| 57 | #clock-cells = <0>; | |
| 58 | /* This value must be overridden by the board */ | |
| 59 | clock-frequency = <0>; | |
| 60 | }; | |
| 61 | ||
| 62 | /* External SCIF clock - to be overridden by boards that provide it */ | |
| 63 | scif_clk: scif { | |
| 64 | compatible = "fixed-clock"; | |
| 65 | #clock-cells = <0>; | |
| 66 | clock-frequency = <0>; | |
| 67 | }; | |
| 68 | ||
| 69 | soc { | |
| 70 | compatible = "simple-bus"; | |
| 71 | interrupt-parent = <&gic>; | |
| 72 | #address-cells = <2>; | |
| 73 | #size-cells = <2>; | |
| 74 | ranges; | |
| 75 | ||
| 76 | gic: interrupt-controller@f1010000 { | |
| 77 | compatible = "arm,gic-400"; | |
| 78 | #interrupt-cells = <3>; | |
| 79 | #address-cells = <0>; | |
| 80 | interrupt-controller; | |
| 81 | reg = <0x0 0xf1010000 0 0x1000>, | |
| 82 | <0x0 0xf1020000 0 0x20000>, | |
| 83 | <0x0 0xf1040000 0 0x20000>, | |
| 84 | <0x0 0xf1060000 0 0x20000>; | |
| 85 | interrupts = <GIC_PPI 9 | |
| 86 | (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>; | |
| 87 | }; | |
| 88 | ||
| 89 | timer { | |
| 90 | compatible = "arm,armv8-timer"; | |
| 91 | interrupts = <GIC_PPI 13 | |
| 92 | (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, | |
| 93 | <GIC_PPI 14 | |
| 94 | (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, | |
| 95 | <GIC_PPI 11 | |
| 96 | (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, | |
| 97 | <GIC_PPI 10 | |
| 98 | (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; | |
| 99 | }; | |
| 100 | ||
| c8ce8007 GU |
101 | wdt0: watchdog@e6020000 { |
| 102 | compatible = "renesas,r8a7796-wdt", | |
| 103 | "renesas,rcar-gen3-wdt"; | |
| 104 | reg = <0 0xe6020000 0 0x0c>; | |
| 105 | clocks = <&cpg CPG_MOD 402>; | |
| 106 | power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; | |
| 107 | status = "disabled"; | |
| 108 | }; | |
| 109 | ||
| fa765e5e TK |
110 | gpio0: gpio@e6050000 { |
| 111 | compatible = "renesas,gpio-r8a7796", | |
| 112 | "renesas,gpio-rcar"; | |
| 113 | reg = <0 0xe6050000 0 0x50>; | |
| 114 | interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; | |
| 115 | #gpio-cells = <2>; | |
| 116 | gpio-controller; | |
| 117 | gpio-ranges = <&pfc 0 0 16>; | |
| 118 | #interrupt-cells = <2>; | |
| 119 | interrupt-controller; | |
| 120 | clocks = <&cpg CPG_MOD 912>; | |
| 121 | power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; | |
| 122 | }; | |
| 123 | ||
| 124 | gpio1: gpio@e6051000 { | |
| 125 | compatible = "renesas,gpio-r8a7796", | |
| 126 | "renesas,gpio-rcar"; | |
| 127 | reg = <0 0xe6051000 0 0x50>; | |
| 128 | interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; | |
| 129 | #gpio-cells = <2>; | |
| 130 | gpio-controller; | |
| 131 | gpio-ranges = <&pfc 0 32 29>; | |
| 132 | #interrupt-cells = <2>; | |
| 133 | interrupt-controller; | |
| 134 | clocks = <&cpg CPG_MOD 911>; | |
| 135 | power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; | |
| 136 | }; | |
| 137 | ||
| 138 | gpio2: gpio@e6052000 { | |
| 139 | compatible = "renesas,gpio-r8a7796", | |
| 140 | "renesas,gpio-rcar"; | |
| 141 | reg = <0 0xe6052000 0 0x50>; | |
| 142 | interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; | |
| 143 | #gpio-cells = <2>; | |
| 144 | gpio-controller; | |
| 145 | gpio-ranges = <&pfc 0 64 15>; | |
| 146 | #interrupt-cells = <2>; | |
| 147 | interrupt-controller; | |
| 148 | clocks = <&cpg CPG_MOD 910>; | |
| 149 | power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; | |
| 150 | }; | |
| 151 | ||
| 152 | gpio3: gpio@e6053000 { | |
| 153 | compatible = "renesas,gpio-r8a7796", | |
| 154 | "renesas,gpio-rcar"; | |
| 155 | reg = <0 0xe6053000 0 0x50>; | |
| 156 | interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; | |
| 157 | #gpio-cells = <2>; | |
| 158 | gpio-controller; | |
| 159 | gpio-ranges = <&pfc 0 96 16>; | |
| 160 | #interrupt-cells = <2>; | |
| 161 | interrupt-controller; | |
| 162 | clocks = <&cpg CPG_MOD 909>; | |
| 163 | power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; | |
| 164 | }; | |
| 165 | ||
| 166 | gpio4: gpio@e6054000 { | |
| 167 | compatible = "renesas,gpio-r8a7796", | |
| 168 | "renesas,gpio-rcar"; | |
| 169 | reg = <0 0xe6054000 0 0x50>; | |
| 170 | interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; | |
| 171 | #gpio-cells = <2>; | |
| 172 | gpio-controller; | |
| 173 | gpio-ranges = <&pfc 0 128 18>; | |
| 174 | #interrupt-cells = <2>; | |
| 175 | interrupt-controller; | |
| 176 | clocks = <&cpg CPG_MOD 908>; | |
| 177 | power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; | |
| 178 | }; | |
| 179 | ||
| 180 | gpio5: gpio@e6055000 { | |
| 181 | compatible = "renesas,gpio-r8a7796", | |
| 182 | "renesas,gpio-rcar"; | |
| 183 | reg = <0 0xe6055000 0 0x50>; | |
| 184 | interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; | |
| 185 | #gpio-cells = <2>; | |
| 186 | gpio-controller; | |
| 187 | gpio-ranges = <&pfc 0 160 26>; | |
| 188 | #interrupt-cells = <2>; | |
| 189 | interrupt-controller; | |
| 190 | clocks = <&cpg CPG_MOD 907>; | |
| 191 | power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; | |
| 192 | }; | |
| 193 | ||
| 194 | gpio6: gpio@e6055400 { | |
| 195 | compatible = "renesas,gpio-r8a7796", | |
| 196 | "renesas,gpio-rcar"; | |
| 197 | reg = <0 0xe6055400 0 0x50>; | |
| 198 | interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; | |
| 199 | #gpio-cells = <2>; | |
| 200 | gpio-controller; | |
| 201 | gpio-ranges = <&pfc 0 192 32>; | |
| 202 | #interrupt-cells = <2>; | |
| 203 | interrupt-controller; | |
| 204 | clocks = <&cpg CPG_MOD 906>; | |
| 205 | power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; | |
| 206 | }; | |
| 207 | ||
| 208 | gpio7: gpio@e6055800 { | |
| 209 | compatible = "renesas,gpio-r8a7796", | |
| 210 | "renesas,gpio-rcar"; | |
| 211 | reg = <0 0xe6055800 0 0x50>; | |
| 212 | interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; | |
| 213 | #gpio-cells = <2>; | |
| 214 | gpio-controller; | |
| 215 | gpio-ranges = <&pfc 0 224 4>; | |
| 216 | #interrupt-cells = <2>; | |
| 217 | interrupt-controller; | |
| 218 | clocks = <&cpg CPG_MOD 905>; | |
| 219 | power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; | |
| 220 | }; | |
| 221 | ||
| 50809470 TK |
222 | pfc: pin-controller@e6060000 { |
| 223 | compatible = "renesas,pfc-r8a7796"; | |
| 224 | reg = <0 0xe6060000 0 0x50c>; | |
| 225 | }; | |
| 226 | ||
| 1561f207 SH |
227 | cpg: clock-controller@e6150000 { |
| 228 | compatible = "renesas,r8a7796-cpg-mssr"; | |
| 229 | reg = <0 0xe6150000 0 0x1000>; | |
| 230 | clocks = <&extal_clk>, <&extalr_clk>; | |
| 231 | clock-names = "extal", "extalr"; | |
| 232 | #clock-cells = <2>; | |
| 233 | #power-domain-cells = <0>; | |
| 234 | }; | |
| 235 | ||
| 56aebae0 GU |
236 | sysc: system-controller@e6180000 { |
| 237 | compatible = "renesas,r8a7796-sysc"; | |
| 238 | reg = <0 0xe6180000 0 0x0400>; | |
| 239 | #power-domain-cells = <1>; | |
| 240 | }; | |
| 241 | ||
| 1561f207 SH |
242 | scif2: serial@e6e88000 { |
| 243 | compatible = "renesas,scif-r8a7796", | |
| 244 | "renesas,rcar-gen3-scif", "renesas,scif"; | |
| 245 | reg = <0 0xe6e88000 0 64>; | |
| 246 | interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; | |
| 247 | clocks = <&cpg CPG_MOD 310>, | |
| 248 | <&cpg CPG_CORE R8A7796_CLK_S3D1>, | |
| 249 | <&scif_clk>; | |
| 250 | clock-names = "fck", "brg_int", "scif_clk"; | |
| a9003187 | 251 | power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; |
| 1561f207 SH |
252 | status = "disabled"; |
| 253 | }; | |
| 254 | }; | |
| 255 | }; |