[deliverable/linux.git] / arch / arm64 / boot / dts / rtsm_ve-motherboard.dtsi

/*
 * ARM Ltd. Fast Models
 *
 * Versatile Express (VE) system model
 * Motherboard component
 *
 * VEMotherBoard.lisa
 */

	motherboard {
		arm,v2m-memory-map = "rs1";
		compatible = "arm,vexpress,v2m-p1", "simple-bus";
		#address-cells = <2>; /* SMB chipselect number and offset */
		#size-cells = <1>;
		#interrupt-cells = <1>;
		ranges;

		flash@0,00000000 {
			compatible = "arm,vexpress-flash", "cfi-flash";
			reg = <0 0x00000000 0x04000000>,
			      <4 0x00000000 0x04000000>;
			bank-width = <4>;
		};

		v2m_video_ram: vram@2,00000000 {
			compatible = "arm,vexpress-vram";
			reg = <2 0x00000000 0x00800000>;
		};

		ethernet@2,02000000 {
			compatible = "smsc,lan91c111";
			reg = <2 0x02000000 0x10000>;
			interrupts = <15>;
		};

		v2m_clk24mhz: clk24mhz {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <24000000>;
			clock-output-names = "v2m:clk24mhz";
		};

		v2m_refclk1mhz: refclk1mhz {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <1000000>;
			clock-output-names = "v2m:refclk1mhz";
		};

		v2m_refclk32khz: refclk32khz {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <32768>;
			clock-output-names = "v2m:refclk32khz";
		};

		iofpga@3,00000000 {
			compatible = "arm,amba-bus", "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 3 0 0x200000>;

			v2m_sysreg: sysreg@010000 {
				compatible = "arm,vexpress-sysreg";
				reg = <0x010000 0x1000>;
				gpio-controller;
				#gpio-cells = <2>;
			};

			v2m_sysctl: sysctl@020000 {
				compatible = "arm,sp810", "arm,primecell";
				reg = <0x020000 0x1000>;
				clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&v2m_clk24mhz>;
				clock-names = "refclk", "timclk", "apb_pclk";
				#clock-cells = <1>;
				clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3";
			};

			aaci@040000 {
				compatible = "arm,pl041", "arm,primecell";
				reg = <0x040000 0x1000>;
				interrupts = <11>;
				clocks = <&v2m_clk24mhz>;
				clock-names = "apb_pclk";
			};

			mmci@050000 {
				compatible = "arm,pl180", "arm,primecell";
				reg = <0x050000 0x1000>;
				interrupts = <9 10>;
				cd-gpios = <&v2m_sysreg 0 0>;
				wp-gpios = <&v2m_sysreg 1 0>;
				max-frequency = <12000000>;
				vmmc-supply = <&v2m_fixed_3v3>;
				clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
				clock-names = "mclk", "apb_pclk";
			};

			kmi@060000 {
				compatible = "arm,pl050", "arm,primecell";
				reg = <0x060000 0x1000>;
				interrupts = <12>;
				clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
				clock-names = "KMIREFCLK", "apb_pclk";
			};

			kmi@070000 {
				compatible = "arm,pl050", "arm,primecell";
				reg = <0x070000 0x1000>;
				interrupts = <13>;
				clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
				clock-names = "KMIREFCLK", "apb_pclk";
			};

			v2m_serial0: uart@090000 {
				compatible = "arm,pl011", "arm,primecell";
				reg = <0x090000 0x1000>;
				interrupts = <5>;
				clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
				clock-names = "uartclk", "apb_pclk";
			};

			v2m_serial1: uart@0a0000 {
				compatible = "arm,pl011", "arm,primecell";
				reg = <0x0a0000 0x1000>;
				interrupts = <6>;
				clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
				clock-names = "uartclk", "apb_pclk";
			};

			v2m_serial2: uart@0b0000 {
				compatible = "arm,pl011", "arm,primecell";
				reg = <0x0b0000 0x1000>;
				interrupts = <7>;
				clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
				clock-names = "uartclk", "apb_pclk";
			};

			v2m_serial3: uart@0c0000 {
				compatible = "arm,pl011", "arm,primecell";
				reg = <0x0c0000 0x1000>;
				interrupts = <8>;
				clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
				clock-names = "uartclk", "apb_pclk";
			};

			wdt@0f0000 {
				compatible = "arm,sp805", "arm,primecell";
				reg = <0x0f0000 0x1000>;
				interrupts = <0>;
				clocks = <&v2m_refclk32khz>, <&v2m_clk24mhz>;
				clock-names = "wdogclk", "apb_pclk";
			};

			v2m_timer01: timer@110000 {
				compatible = "arm,sp804", "arm,primecell";
				reg = <0x110000 0x1000>;
				interrupts = <2>;
				clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_clk24mhz>;
				clock-names = "timclken1", "timclken2", "apb_pclk";
			};

			v2m_timer23: timer@120000 {
				compatible = "arm,sp804", "arm,primecell";
				reg = <0x120000 0x1000>;
				interrupts = <3>;
				clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&v2m_clk24mhz>;
				clock-names = "timclken1", "timclken2", "apb_pclk";
			};

			rtc@170000 {
				compatible = "arm,pl031", "arm,primecell";
				reg = <0x170000 0x1000>;
				interrupts = <4>;
				clocks = <&v2m_clk24mhz>;
				clock-names = "apb_pclk";
			};

			clcd@1f0000 {
				compatible = "arm,pl111", "arm,primecell";
				reg = <0x1f0000 0x1000>;
				interrupt-names = "combined";
				interrupts = <14>;
				clocks = <&v2m_oscclk1>, <&v2m_clk24mhz>;
				clock-names = "clcdclk", "apb_pclk";
				arm,pl11x,framebuffer = <0x18000000 0x00180000>;
				memory-region = <&v2m_video_ram>;
				max-memory-bandwidth = <130000000>; /* 16bpp @ 63.5MHz */

				port {
					v2m_clcd_pads: endpoint {
						remote-endpoint = <&v2m_clcd_panel>;
						arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
					};
				};

				panel {
					compatible = "panel-dpi";

					port {
						v2m_clcd_panel: endpoint {
							remote-endpoint = <&v2m_clcd_pads>;
						};
					};

					panel-timing {
						clock-frequency = <63500127>;
						hactive = <1024>;
						hback-porch = <152>;
						hfront-porch = <48>;
						hsync-len = <104>;
						vactive = <768>;
						vback-porch = <23>;
						vfront-porch = <3>;
						vsync-len = <4>;
					};
				};
			};

			virtio_block@0130000 {
				compatible = "virtio,mmio";
				reg = <0x130000 0x200>;
				interrupts = <42>;
			};
		};

		v2m_fixed_3v3: fixedregulator@0 {
			compatible = "regulator-fixed";
			regulator-name = "3V3";
			regulator-min-microvolt = <3300000>;
			regulator-max-microvolt = <3300000>;
			regulator-always-on;
		};

		mcc {
			compatible = "arm,vexpress,config-bus";
			arm,vexpress,config-bridge = <&v2m_sysreg>;

			v2m_oscclk1: osc@1 {
				/* CLCD clock */
				compatible = "arm,vexpress-osc";
				arm,vexpress-sysreg,func = <1 1>;
				freq-range = <23750000 63500000>;
				#clock-cells = <0>;
				clock-output-names = "v2m:oscclk1";
			};

			reset@0 {
				compatible = "arm,vexpress-reset";
				arm,vexpress-sysreg,func = <5 0>;
			};

			muxfpga@0 {
				compatible = "arm,vexpress-muxfpga";
				arm,vexpress-sysreg,func = <7 0>;
			};

			shutdown@0 {
				compatible = "arm,vexpress-shutdown";
				arm,vexpress-sysreg,func = <8 0>;
			};

			reboot@0 {
				compatible = "arm,vexpress-reboot";
				arm,vexpress-sysreg,func = <9 0>;
			};

			dvimode@0 {
				compatible = "arm,vexpress-dvimode";
				arm,vexpress-sysreg,func = <11 0>;
			};
		};
	};
Commit	Line	Data
90556ca1 PM	1	/*
	2	* ARM Ltd. Fast Models
	3	*
	4	* Versatile Express (VE) system model
	5	* Motherboard component
	6	*
	7	* VEMotherBoard.lisa
	8	*/
	9
	10	motherboard {
	11	arm,v2m-memory-map = "rs1";
	12	compatible = "arm,vexpress,v2m-p1", "simple-bus";
	13	#address-cells = <2>; /* SMB chipselect number and offset */
	14	#size-cells = <1>;
	15	#interrupt-cells = <1>;
	16	ranges;
	17
	18	flash@0,00000000 {
	19	compatible = "arm,vexpress-flash", "cfi-flash";
	20	reg = <0 0x00000000 0x04000000>,
	21	<4 0x00000000 0x04000000>;
	22	bank-width = <4>;
	23	};
	24
e2b6b35e	25	v2m_video_ram: vram@2,00000000 {
90556ca1 PM	26	compatible = "arm,vexpress-vram";
	27	reg = <2 0x00000000 0x00800000>;
	28	};
	29
	30	ethernet@2,02000000 {
	31	compatible = "smsc,lan91c111";
	32	reg = <2 0x02000000 0x10000>;
	33	interrupts = <15>;
	34	};
	35
	36	v2m_clk24mhz: clk24mhz {
	37	compatible = "fixed-clock";
	38	#clock-cells = <0>;
	39	clock-frequency = <24000000>;
	40	clock-output-names = "v2m:clk24mhz";
	41	};
	42
	43	v2m_refclk1mhz: refclk1mhz {
	44	compatible = "fixed-clock";
	45	#clock-cells = <0>;
	46	clock-frequency = <1000000>;
	47	clock-output-names = "v2m:refclk1mhz";
	48	};
	49
	50	v2m_refclk32khz: refclk32khz {
	51	compatible = "fixed-clock";
	52	#clock-cells = <0>;
	53	clock-frequency = <32768>;
	54	clock-output-names = "v2m:refclk32khz";
	55	};
	56
	57	iofpga@3,00000000 {
	58	compatible = "arm,amba-bus", "simple-bus";
	59	#address-cells = <1>;
	60	#size-cells = <1>;
	61	ranges = <0 3 0 0x200000>;
	62
	63	v2m_sysreg: sysreg@010000 {
	64	compatible = "arm,vexpress-sysreg";
	65	reg = <0x010000 0x1000>;
	66	gpio-controller;
	67	#gpio-cells = <2>;
	68	};
	69
	70	v2m_sysctl: sysctl@020000 {
	71	compatible = "arm,sp810", "arm,primecell";
	72	reg = <0x020000 0x1000>;
	73	clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&v2m_clk24mhz>;
	74	clock-names = "refclk", "timclk", "apb_pclk";
	75	#clock-cells = <1>;
	76	clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3";
	77	};
	78
	79	aaci@040000 {
	80	compatible = "arm,pl041", "arm,primecell";
	81	reg = <0x040000 0x1000>;
	82	interrupts = <11>;
	83	clocks = <&v2m_clk24mhz>;
	84	clock-names = "apb_pclk";
	85	};
	86
	87	mmci@050000 {
	88	compatible = "arm,pl180", "arm,primecell";
	89	reg = <0x050000 0x1000>;
90	interrupts = <9 10>;
91	cd-gpios = <&v2m_sysreg 0 0>;
92	wp-gpios = <&v2m_sysreg 1 0>;
93	max-frequency = <12000000>;
94	vmmc-supply = <&v2m_fixed_3v3>;
95	clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
96	clock-names = "mclk", "apb_pclk";
97	};
98
99	kmi@060000 {
100	compatible = "arm,pl050", "arm,primecell";
101	reg = <0x060000 0x1000>;
102	interrupts = <12>;
103	clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
104	clock-names = "KMIREFCLK", "apb_pclk";
105	};
106
107	kmi@070000 {
108	compatible = "arm,pl050", "arm,primecell";
109	reg = <0x070000 0x1000>;
110	interrupts = <13>;
111	clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
112	clock-names = "KMIREFCLK", "apb_pclk";
113	};
114
115	v2m_serial0: uart@090000 {
116	compatible = "arm,pl011", "arm,primecell";
117	reg = <0x090000 0x1000>;
118	interrupts = <5>;
119	clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
120	clock-names = "uartclk", "apb_pclk";
121	};
122
123	v2m_serial1: uart@0a0000 {
124	compatible = "arm,pl011", "arm,primecell";
125	reg = <0x0a0000 0x1000>;
126	interrupts = <6>;
127	clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
128	clock-names = "uartclk", "apb_pclk";
129	};
130
131	v2m_serial2: uart@0b0000 {
132	compatible = "arm,pl011", "arm,primecell";
133	reg = <0x0b0000 0x1000>;
134	interrupts = <7>;
135	clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
136	clock-names = "uartclk", "apb_pclk";
137	};
138
139	v2m_serial3: uart@0c0000 {
140	compatible = "arm,pl011", "arm,primecell";
141	reg = <0x0c0000 0x1000>;
142	interrupts = <8>;
143	clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
144	clock-names = "uartclk", "apb_pclk";
145	};
146
147	wdt@0f0000 {
148	compatible = "arm,sp805", "arm,primecell";
149	reg = <0x0f0000 0x1000>;
150	interrupts = <0>;
151	clocks = <&v2m_refclk32khz>, <&v2m_clk24mhz>;
152	clock-names = "wdogclk", "apb_pclk";
153	};
154
155	v2m_timer01: timer@110000 {
156	compatible = "arm,sp804", "arm,primecell";
157	reg = <0x110000 0x1000>;
158	interrupts = <2>;
159	clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_clk24mhz>;
160	clock-names = "timclken1", "timclken2", "apb_pclk";
161	};
162
163	v2m_timer23: timer@120000 {
164	compatible = "arm,sp804", "arm,primecell";
165	reg = <0x120000 0x1000>;
166	interrupts = <3>;
167	clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&v2m_clk24mhz>;
168	clock-names = "timclken1", "timclken2", "apb_pclk";
169	};
170
171	rtc@170000 {
172	compatible = "arm,pl031", "arm,primecell";
173	reg = <0x170000 0x1000>;
174	interrupts = <4>;
175	clocks = <&v2m_clk24mhz>;
176	clock-names = "apb_pclk";
177	};
178
179	clcd@1f0000 {
180	compatible = "arm,pl111", "arm,primecell";
181	reg = <0x1f0000 0x1000>;
e2b6b35e	182	interrupt-names = "combined";
90556ca1 PM	183	interrupts = <14>;
	184	clocks = <&v2m_oscclk1>, <&v2m_clk24mhz>;
	185	clock-names = "clcdclk", "apb_pclk";
e2b6b35e CM	186	arm,pl11x,framebuffer = <0x18000000 0x00180000>;
	187	memory-region = <&v2m_video_ram>;
	188	max-memory-bandwidth = <130000000>; /* 16bpp @ 63.5MHz */
	189
	190	port {
	191	v2m_clcd_pads: endpoint {
	192	remote-endpoint = <&v2m_clcd_panel>;
	193	arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
	194	};
	195	};
	196
	197	panel {
	198	compatible = "panel-dpi";
	199
	200	port {
	201	v2m_clcd_panel: endpoint {
	202	remote-endpoint = <&v2m_clcd_pads>;
	203	};
	204	};
	205
	206	panel-timing {
	207	clock-frequency = <63500127>;
	208	hactive = <1024>;
	209	hback-porch = <152>;
	210	hfront-porch = <48>;
	211	hsync-len = <104>;
	212	vactive = <768>;
	213	vback-porch = <23>;
	214	vfront-porch = <3>;
	215	vsync-len = <4>;
	216	};
	217	};
90556ca1	218	};
1bb2cbb6 MH	219
	220	virtio_block@0130000 {
	221	compatible = "virtio,mmio";
	222	reg = <0x130000 0x200>;
	223	interrupts = <42>;
	224	};
90556ca1 PM	225	};
	226
	227	v2m_fixed_3v3: fixedregulator@0 {
	228	compatible = "regulator-fixed";
	229	regulator-name = "3V3";
	230	regulator-min-microvolt = <3300000>;
	231	regulator-max-microvolt = <3300000>;
	232	regulator-always-on;
	233	};
	234
	235	mcc {
3b9334ac	236	compatible = "arm,vexpress,config-bus";
90556ca1 PM	237	arm,vexpress,config-bridge = <&v2m_sysreg>;
	238
	239	v2m_oscclk1: osc@1 {
	240	/* CLCD clock */
	241	compatible = "arm,vexpress-osc";
	242	arm,vexpress-sysreg,func = <1 1>;
	243	freq-range = <23750000 63500000>;
	244	#clock-cells = <0>;
	245	clock-output-names = "v2m:oscclk1";
	246	};
	247
	248	reset@0 {
	249	compatible = "arm,vexpress-reset";
	250	arm,vexpress-sysreg,func = <5 0>;
	251	};
	252
	253	muxfpga@0 {
	254	compatible = "arm,vexpress-muxfpga";
	255	arm,vexpress-sysreg,func = <7 0>;
	256	};
	257
	258	shutdown@0 {
	259	compatible = "arm,vexpress-shutdown";
	260	arm,vexpress-sysreg,func = <8 0>;
	261	};
	262
	263	reboot@0 {
	264	compatible = "arm,vexpress-reboot";
	265	arm,vexpress-sysreg,func = <9 0>;
	266	};
	267
	268	dvimode@0 {
	269	compatible = "arm,vexpress-dvimode";
	270	arm,vexpress-sysreg,func = <11 0>;
	271	};
	272	};
	273	};