[deliverable/linux.git] / arch / arm64 / include / asm / hw_breakpoint.h

/*
 * Copyright (C) 2012 ARM Ltd.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */
#ifndef __ASM_HW_BREAKPOINT_H
#define __ASM_HW_BREAKPOINT_H

#include <asm/cputype.h>
#include <asm/cpufeature.h>
#include <asm/virt.h>

#ifdef __KERNEL__

struct arch_hw_breakpoint_ctrl {
	u32 __reserved	: 19,
	len		: 8,
	type		: 2,
	privilege	: 2,
	enabled		: 1;
};

struct arch_hw_breakpoint {
	u64 address;
	u64 trigger;
	struct arch_hw_breakpoint_ctrl ctrl;
};

/* Privilege Levels */
#define AARCH64_BREAKPOINT_EL1	1
#define AARCH64_BREAKPOINT_EL0	2

#define DBG_HMC_HYP		(1 << 13)

static inline u32 encode_ctrl_reg(struct arch_hw_breakpoint_ctrl ctrl)
{
	u32 val = (ctrl.len << 5) | (ctrl.type << 3) | (ctrl.privilege << 1) |
		ctrl.enabled;

	if (is_kernel_in_hyp_mode() && ctrl.privilege == AARCH64_BREAKPOINT_EL1)
		val |= DBG_HMC_HYP;

	return val;
}

static inline void decode_ctrl_reg(u32 reg,
				   struct arch_hw_breakpoint_ctrl *ctrl)
{
	ctrl->enabled	= reg & 0x1;
	reg >>= 1;
	ctrl->privilege	= reg & 0x3;
	reg >>= 2;
	ctrl->type	= reg & 0x3;
	reg >>= 2;
	ctrl->len	= reg & 0xff;
}

/* Breakpoint */
#define ARM_BREAKPOINT_EXECUTE	0

/* Watchpoints */
#define ARM_BREAKPOINT_LOAD	1
#define ARM_BREAKPOINT_STORE	2
#define AARCH64_ESR_ACCESS_MASK	(1 << 6)

/* Lengths */
#define ARM_BREAKPOINT_LEN_1	0x1
#define ARM_BREAKPOINT_LEN_2	0x3
#define ARM_BREAKPOINT_LEN_4	0xf
#define ARM_BREAKPOINT_LEN_8	0xff

/* Kernel stepping */
#define ARM_KERNEL_STEP_NONE	0
#define ARM_KERNEL_STEP_ACTIVE	1
#define ARM_KERNEL_STEP_SUSPEND	2

/*
 * Limits.
 * Changing these will require modifications to the register accessors.
 */
#define ARM_MAX_BRP		16
#define ARM_MAX_WRP		16

/* Virtual debug register bases. */
#define AARCH64_DBG_REG_BVR	0
#define AARCH64_DBG_REG_BCR	(AARCH64_DBG_REG_BVR + ARM_MAX_BRP)
#define AARCH64_DBG_REG_WVR	(AARCH64_DBG_REG_BCR + ARM_MAX_BRP)
#define AARCH64_DBG_REG_WCR	(AARCH64_DBG_REG_WVR + ARM_MAX_WRP)

/* Debug register names. */
#define AARCH64_DBG_REG_NAME_BVR	"bvr"
#define AARCH64_DBG_REG_NAME_BCR	"bcr"
#define AARCH64_DBG_REG_NAME_WVR	"wvr"
#define AARCH64_DBG_REG_NAME_WCR	"wcr"

/* Accessor macros for the debug registers. */
#define AARCH64_DBG_READ(N, REG, VAL) do {\
	asm volatile("mrs %0, dbg" REG #N "_el1" : "=r" (VAL));\
} while (0)

#define AARCH64_DBG_WRITE(N, REG, VAL) do {\
	asm volatile("msr dbg" REG #N "_el1, %0" :: "r" (VAL));\
} while (0)

struct task_struct;
struct notifier_block;
struct perf_event;
struct pmu;

extern int arch_bp_generic_fields(struct arch_hw_breakpoint_ctrl ctrl,
				  int *gen_len, int *gen_type);
extern int arch_check_bp_in_kernelspace(struct perf_event *bp);
extern int arch_validate_hwbkpt_settings(struct perf_event *bp);
extern int hw_breakpoint_exceptions_notify(struct notifier_block *unused,
					   unsigned long val, void *data);

extern int arch_install_hw_breakpoint(struct perf_event *bp);
extern void arch_uninstall_hw_breakpoint(struct perf_event *bp);
extern void hw_breakpoint_pmu_read(struct perf_event *bp);
extern int hw_breakpoint_slots(int type);

#ifdef CONFIG_HAVE_HW_BREAKPOINT
extern void hw_breakpoint_thread_switch(struct task_struct *next);
extern void ptrace_hw_copy_thread(struct task_struct *task);
#else
static inline void hw_breakpoint_thread_switch(struct task_struct *next)
{
}
static inline void ptrace_hw_copy_thread(struct task_struct *task)
{
}
#endif

extern struct pmu perf_ops_bp;

/* Determine number of BRP registers available. */
static inline int get_num_brps(void)
{
	u64 dfr0 = read_system_reg(SYS_ID_AA64DFR0_EL1);
	return 1 +
		cpuid_feature_extract_unsigned_field(dfr0,
						ID_AA64DFR0_BRPS_SHIFT);
}

/* Determine number of WRP registers available. */
static inline int get_num_wrps(void)
{
	u64 dfr0 = read_system_reg(SYS_ID_AA64DFR0_EL1);
	return 1 +
		cpuid_feature_extract_unsigned_field(dfr0,
						ID_AA64DFR0_WRPS_SHIFT);
}

#endif	/* __KERNEL__ */
#endif	/* __ASM_BREAKPOINT_H */
Commit	Line	Data
478fcb2c WD	1	/*
	2	* Copyright (C) 2012 ARM Ltd.
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License version 2 as
	6	* published by the Free Software Foundation.
	7	*
	8	* This program is distributed in the hope that it will be useful,
	9	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	10	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	11	* GNU General Public License for more details.
	12	*
	13	* You should have received a copy of the GNU General Public License
	14	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	15	*/
	16	#ifndef __ASM_HW_BREAKPOINT_H
	17	#define __ASM_HW_BREAKPOINT_H
	18
834bf887	19	#include <asm/cputype.h>
3085bb01	20	#include <asm/cpufeature.h>
ae7e27fe	21	#include <asm/virt.h>
834bf887	22
478fcb2c WD	23	#ifdef __KERNEL__
	24
	25	struct arch_hw_breakpoint_ctrl {
	26	u32 __reserved : 19,
	27	len : 8,
	28	type : 2,
	29	privilege : 2,
	30	enabled : 1;
	31	};
	32
	33	struct arch_hw_breakpoint {
	34	u64 address;
	35	u64 trigger;
	36	struct arch_hw_breakpoint_ctrl ctrl;
	37	};
	38
ae7e27fe MZ	39	/* Privilege Levels */
	40	#define AARCH64_BREAKPOINT_EL1 1
	41	#define AARCH64_BREAKPOINT_EL0 2
	42
	43	#define DBG_HMC_HYP (1 << 13)
	44
478fcb2c WD	45	static inline u32 encode_ctrl_reg(struct arch_hw_breakpoint_ctrl ctrl)
478fcb2c WD	46	{
ae7e27fe	47	u32 val = (ctrl.len << 5) \| (ctrl.type << 3) \| (ctrl.privilege << 1) \|
478fcb2c	48	ctrl.enabled;
ae7e27fe MZ	49
	50	if (is_kernel_in_hyp_mode() && ctrl.privilege == AARCH64_BREAKPOINT_EL1)
	51	val \|= DBG_HMC_HYP;
	52
	53	return val;
478fcb2c WD	54	}
	55
	56	static inline void decode_ctrl_reg(u32 reg,
	57	struct arch_hw_breakpoint_ctrl *ctrl)
	58	{
	59	ctrl->enabled = reg & 0x1;
	60	reg >>= 1;
	61	ctrl->privilege = reg & 0x3;
	62	reg >>= 2;
	63	ctrl->type = reg & 0x3;
	64	reg >>= 2;
	65	ctrl->len = reg & 0xff;
	66	}
	67
	68	/* Breakpoint */
	69	#define ARM_BREAKPOINT_EXECUTE 0
	70
	71	/* Watchpoints */
	72	#define ARM_BREAKPOINT_LOAD 1
	73	#define ARM_BREAKPOINT_STORE 2
	74	#define AARCH64_ESR_ACCESS_MASK (1 << 6)
	75
478fcb2c WD	76	/* Lengths */
	77	#define ARM_BREAKPOINT_LEN_1 0x1
	78	#define ARM_BREAKPOINT_LEN_2 0x3
	79	#define ARM_BREAKPOINT_LEN_4 0xf
	80	#define ARM_BREAKPOINT_LEN_8 0xff
	81
	82	/* Kernel stepping */
	83	#define ARM_KERNEL_STEP_NONE 0
	84	#define ARM_KERNEL_STEP_ACTIVE 1
	85	#define ARM_KERNEL_STEP_SUSPEND 2
	86
	87	/*
	88	* Limits.
	89	* Changing these will require modifications to the register accessors.
	90	*/
	91	#define ARM_MAX_BRP 16
	92	#define ARM_MAX_WRP 16
478fcb2c WD	93
	94	/* Virtual debug register bases. */
	95	#define AARCH64_DBG_REG_BVR 0
	96	#define AARCH64_DBG_REG_BCR (AARCH64_DBG_REG_BVR + ARM_MAX_BRP)
	97	#define AARCH64_DBG_REG_WVR (AARCH64_DBG_REG_BCR + ARM_MAX_BRP)
	98	#define AARCH64_DBG_REG_WCR (AARCH64_DBG_REG_WVR + ARM_MAX_WRP)
	99
	100	/* Debug register names. */
	101	#define AARCH64_DBG_REG_NAME_BVR "bvr"
	102	#define AARCH64_DBG_REG_NAME_BCR "bcr"
	103	#define AARCH64_DBG_REG_NAME_WVR "wvr"
	104	#define AARCH64_DBG_REG_NAME_WCR "wcr"
	105
	106	/* Accessor macros for the debug registers. */
	107	#define AARCH64_DBG_READ(N, REG, VAL) do {\
	108	asm volatile("mrs %0, dbg" REG #N "_el1" : "=r" (VAL));\
	109	} while (0)
	110
	111	#define AARCH64_DBG_WRITE(N, REG, VAL) do {\
	112	asm volatile("msr dbg" REG #N "_el1, %0" :: "r" (VAL));\
	113	} while (0)
	114
	115	struct task_struct;
	116	struct notifier_block;
	117	struct perf_event;
	118	struct pmu;
	119
	120	extern int arch_bp_generic_fields(struct arch_hw_breakpoint_ctrl ctrl,
	121	int gen_len, int gen_type);
	122	extern int arch_check_bp_in_kernelspace(struct perf_event *bp);
	123	extern int arch_validate_hwbkpt_settings(struct perf_event *bp);
	124	extern int hw_breakpoint_exceptions_notify(struct notifier_block *unused,
	125	unsigned long val, void *data);
	126
	127	extern int arch_install_hw_breakpoint(struct perf_event *bp);
	128	extern void arch_uninstall_hw_breakpoint(struct perf_event *bp);
	129	extern void hw_breakpoint_pmu_read(struct perf_event *bp);
	130	extern int hw_breakpoint_slots(int type);
	131
	132	#ifdef CONFIG_HAVE_HW_BREAKPOINT
	133	extern void hw_breakpoint_thread_switch(struct task_struct *next);
	134	extern void ptrace_hw_copy_thread(struct task_struct *task);
	135	#else
	136	static inline void hw_breakpoint_thread_switch(struct task_struct *next)
	137	{
	138	}
	139	static inline void ptrace_hw_copy_thread(struct task_struct *task)
	140	{
	141	}
	142	#endif
	143
	144	extern struct pmu perf_ops_bp;
	145
834bf887 AB	146	/* Determine number of BRP registers available. */
	147	static inline int get_num_brps(void)
	148	{
1944bf8e	149	u64 dfr0 = read_system_reg(SYS_ID_AA64DFR0_EL1);
3085bb01	150	return 1 +
1944bf8e	151	cpuid_feature_extract_unsigned_field(dfr0,
3085bb01	152	ID_AA64DFR0_BRPS_SHIFT);
834bf887 AB	153	}
	154
	155	/* Determine number of WRP registers available. */
	156	static inline int get_num_wrps(void)
	157	{
1944bf8e	158	u64 dfr0 = read_system_reg(SYS_ID_AA64DFR0_EL1);
3085bb01	159	return 1 +
1944bf8e	160	cpuid_feature_extract_unsigned_field(dfr0,
3085bb01	161	ID_AA64DFR0_WRPS_SHIFT);
834bf887 AB	162	}
834bf887 AB	163
478fcb2c WD	164	#endif /* __KERNEL__ */
478fcb2c WD	165	#endif /* __ASM_BREAKPOINT_H */