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b3901d54 CM |
1 | /* |
2 | * Based on arch/arm/include/asm/mmu_context.h | |
3 | * | |
4 | * Copyright (C) 1996 Russell King. | |
5 | * Copyright (C) 2012 ARM Ltd. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | #ifndef __ASM_MMU_CONTEXT_H | |
20 | #define __ASM_MMU_CONTEXT_H | |
21 | ||
22 | #include <linux/compiler.h> | |
23 | #include <linux/sched.h> | |
24 | ||
25 | #include <asm/cacheflush.h> | |
26 | #include <asm/proc-fns.h> | |
27 | #include <asm-generic/mm_hooks.h> | |
28 | #include <asm/cputype.h> | |
29 | #include <asm/pgtable.h> | |
30 | ||
ec45d1cf WD |
31 | #ifdef CONFIG_PID_IN_CONTEXTIDR |
32 | static inline void contextidr_thread_switch(struct task_struct *next) | |
33 | { | |
34 | asm( | |
35 | " msr contextidr_el1, %0\n" | |
36 | " isb" | |
37 | : | |
38 | : "r" (task_pid_nr(next))); | |
39 | } | |
40 | #else | |
41 | static inline void contextidr_thread_switch(struct task_struct *next) | |
42 | { | |
43 | } | |
44 | #endif | |
45 | ||
b3901d54 CM |
46 | /* |
47 | * Set TTBR0 to empty_zero_page. No translations will be possible via TTBR0. | |
48 | */ | |
49 | static inline void cpu_set_reserved_ttbr0(void) | |
50 | { | |
51 | unsigned long ttbr = page_to_phys(empty_zero_page); | |
52 | ||
53 | asm( | |
54 | " msr ttbr0_el1, %0 // set TTBR0\n" | |
55 | " isb" | |
56 | : | |
57 | : "r" (ttbr)); | |
58 | } | |
59 | ||
dd006da2 AB |
60 | /* |
61 | * TCR.T0SZ value to use when the ID map is active. Usually equals | |
62 | * TCR_T0SZ(VA_BITS), unless system RAM is positioned very high in | |
63 | * physical memory, in which case it will be smaller. | |
64 | */ | |
65 | extern u64 idmap_t0sz; | |
66 | ||
67 | static inline bool __cpu_uses_extended_idmap(void) | |
68 | { | |
69 | return (!IS_ENABLED(CONFIG_ARM64_VA_BITS_48) && | |
70 | unlikely(idmap_t0sz != TCR_T0SZ(VA_BITS))); | |
71 | } | |
72 | ||
dd006da2 AB |
73 | /* |
74 | * Set TCR.T0SZ to its default value (based on VA_BITS) | |
75 | */ | |
76 | static inline void cpu_set_default_tcr_t0sz(void) | |
77 | { | |
c51e97d8 WD |
78 | unsigned long tcr; |
79 | ||
80 | if (!__cpu_uses_extended_idmap()) | |
81 | return; | |
82 | ||
83 | asm volatile ( | |
84 | " mrs %0, tcr_el1 ;" | |
85 | " bfi %0, %1, %2, %3 ;" | |
86 | " msr tcr_el1, %0 ;" | |
87 | " isb" | |
88 | : "=&r" (tcr) | |
89 | : "r"(TCR_T0SZ(VA_BITS)), "I"(TCR_T0SZ_OFFSET), "I"(TCR_TxSZ_WIDTH)); | |
dd006da2 AB |
90 | } |
91 | ||
5aec715d WD |
92 | /* |
93 | * It would be nice to return ASIDs back to the allocator, but unfortunately | |
94 | * that introduces a race with a generation rollover where we could erroneously | |
95 | * free an ASID allocated in a future generation. We could workaround this by | |
96 | * freeing the ASID from the context of the dying mm (e.g. in arch_exit_mmap), | |
97 | * but we'd then need to make sure that we didn't dirty any TLBs afterwards. | |
98 | * Setting a reserved TTBR0 or EPD0 would work, but it all gets ugly when you | |
99 | * take CPU migration into account. | |
100 | */ | |
b3901d54 | 101 | #define destroy_context(mm) do { } while(0) |
5aec715d | 102 | void check_and_switch_context(struct mm_struct *mm, unsigned int cpu); |
b3901d54 | 103 | |
5aec715d | 104 | #define init_new_context(tsk,mm) ({ atomic64_set(&mm->context.id, 0); 0; }) |
b3901d54 CM |
105 | |
106 | /* | |
107 | * This is called when "tsk" is about to enter lazy TLB mode. | |
108 | * | |
109 | * mm: describes the currently active mm context | |
110 | * tsk: task which is entering lazy tlb | |
111 | * cpu: cpu number which is entering lazy tlb | |
112 | * | |
113 | * tsk->mm will be NULL | |
114 | */ | |
115 | static inline void | |
116 | enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk) | |
117 | { | |
118 | } | |
119 | ||
120 | /* | |
121 | * This is the actual mm switch as far as the scheduler | |
122 | * is concerned. No registers are touched. We avoid | |
123 | * calling the CPU specific function when the mm hasn't | |
124 | * actually changed. | |
125 | */ | |
126 | static inline void | |
127 | switch_mm(struct mm_struct *prev, struct mm_struct *next, | |
128 | struct task_struct *tsk) | |
129 | { | |
130 | unsigned int cpu = smp_processor_id(); | |
131 | ||
c2775b2e WD |
132 | if (prev == next) |
133 | return; | |
134 | ||
e53f21bc CM |
135 | /* |
136 | * init_mm.pgd does not contain any user mappings and it is always | |
137 | * active for kernel addresses in TTBR1. Just set the reserved TTBR0. | |
138 | */ | |
139 | if (next == &init_mm) { | |
140 | cpu_set_reserved_ttbr0(); | |
141 | return; | |
142 | } | |
143 | ||
c2775b2e | 144 | check_and_switch_context(next, cpu); |
b3901d54 CM |
145 | } |
146 | ||
147 | #define deactivate_mm(tsk,mm) do { } while (0) | |
148 | #define activate_mm(prev,next) switch_mm(prev, next, NULL) | |
149 | ||
150 | #endif |