[deliverable/linux.git] / arch / arm64 / include / asm / pgtable-hwdef.h

/*
 * Copyright (C) 2012 ARM Ltd.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */
#ifndef __ASM_PGTABLE_HWDEF_H
#define __ASM_PGTABLE_HWDEF_H

#define PTRS_PER_PTE		(1 << (PAGE_SHIFT - 3))

/*
 * PMD_SHIFT determines the size a level 2 page table entry can map.
 */
#if CONFIG_PGTABLE_LEVELS > 2
#define PMD_SHIFT		((PAGE_SHIFT - 3) * 2 + 3)
#define PMD_SIZE		(_AC(1, UL) << PMD_SHIFT)
#define PMD_MASK		(~(PMD_SIZE-1))
#define PTRS_PER_PMD		PTRS_PER_PTE
#endif

/*
 * PUD_SHIFT determines the size a level 1 page table entry can map.
 */
#if CONFIG_PGTABLE_LEVELS > 3
#define PUD_SHIFT		((PAGE_SHIFT - 3) * 3 + 3)
#define PUD_SIZE		(_AC(1, UL) << PUD_SHIFT)
#define PUD_MASK		(~(PUD_SIZE-1))
#define PTRS_PER_PUD		PTRS_PER_PTE
#endif

/*
 * PGDIR_SHIFT determines the size a top-level page table entry can map
 * (depending on the configuration, this level can be 0, 1 or 2).
 */
#define PGDIR_SHIFT		((PAGE_SHIFT - 3) * CONFIG_PGTABLE_LEVELS + 3)
#define PGDIR_SIZE		(_AC(1, UL) << PGDIR_SHIFT)
#define PGDIR_MASK		(~(PGDIR_SIZE-1))
#define PTRS_PER_PGD		(1 << (VA_BITS - PGDIR_SHIFT))

/*
 * Section address mask and size definitions.
 */
#define SECTION_SHIFT		PMD_SHIFT
#define SECTION_SIZE		(_AC(1, UL) << SECTION_SHIFT)
#define SECTION_MASK		(~(SECTION_SIZE-1))

/*
 * Hardware page table definitions.
 *
 * Level 1 descriptor (PUD).
 */
#define PUD_TYPE_TABLE		(_AT(pudval_t, 3) << 0)
#define PUD_TABLE_BIT		(_AT(pgdval_t, 1) << 1)
#define PUD_TYPE_MASK		(_AT(pgdval_t, 3) << 0)
#define PUD_TYPE_SECT		(_AT(pgdval_t, 1) << 0)

/*
 * Level 2 descriptor (PMD).
 */
#define PMD_TYPE_MASK		(_AT(pmdval_t, 3) << 0)
#define PMD_TYPE_FAULT		(_AT(pmdval_t, 0) << 0)
#define PMD_TYPE_TABLE		(_AT(pmdval_t, 3) << 0)
#define PMD_TYPE_SECT		(_AT(pmdval_t, 1) << 0)
#define PMD_TABLE_BIT		(_AT(pmdval_t, 1) << 1)

/*
 * Section
 */
#define PMD_SECT_VALID		(_AT(pmdval_t, 1) << 0)
#define PMD_SECT_PROT_NONE	(_AT(pmdval_t, 1) << 58)
#define PMD_SECT_USER		(_AT(pmdval_t, 1) << 6)		/* AP[1] */
#define PMD_SECT_RDONLY		(_AT(pmdval_t, 1) << 7)		/* AP[2] */
#define PMD_SECT_S		(_AT(pmdval_t, 3) << 8)
#define PMD_SECT_AF		(_AT(pmdval_t, 1) << 10)
#define PMD_SECT_NG		(_AT(pmdval_t, 1) << 11)
#define PMD_SECT_PXN		(_AT(pmdval_t, 1) << 53)
#define PMD_SECT_UXN		(_AT(pmdval_t, 1) << 54)

/*
 * AttrIndx[2:0] encoding (mapping attributes defined in the MAIR* registers).
 */
#define PMD_ATTRINDX(t)		(_AT(pmdval_t, (t)) << 2)
#define PMD_ATTRINDX_MASK	(_AT(pmdval_t, 7) << 2)

/*
 * Level 3 descriptor (PTE).
 */
#define PTE_TYPE_MASK		(_AT(pteval_t, 3) << 0)
#define PTE_TYPE_FAULT		(_AT(pteval_t, 0) << 0)
#define PTE_TYPE_PAGE		(_AT(pteval_t, 3) << 0)
#define PTE_TABLE_BIT		(_AT(pteval_t, 1) << 1)
#define PTE_USER		(_AT(pteval_t, 1) << 6)		/* AP[1] */
#define PTE_RDONLY		(_AT(pteval_t, 1) << 7)		/* AP[2] */
#define PTE_SHARED		(_AT(pteval_t, 3) << 8)		/* SH[1:0], inner shareable */
#define PTE_AF			(_AT(pteval_t, 1) << 10)	/* Access Flag */
#define PTE_NG			(_AT(pteval_t, 1) << 11)	/* nG */
#define PTE_DBM			(_AT(pteval_t, 1) << 51)	/* Dirty Bit Management */
#define PTE_PXN			(_AT(pteval_t, 1) << 53)	/* Privileged XN */
#define PTE_UXN			(_AT(pteval_t, 1) << 54)	/* User XN */

/*
 * AttrIndx[2:0] encoding (mapping attributes defined in the MAIR* registers).
 */
#define PTE_ATTRINDX(t)		(_AT(pteval_t, (t)) << 2)
#define PTE_ATTRINDX_MASK	(_AT(pteval_t, 7) << 2)

/*
 * 2nd stage PTE definitions
 */
#define PTE_S2_RDONLY		(_AT(pteval_t, 1) << 6)   /* HAP[2:1] */
#define PTE_S2_RDWR		(_AT(pteval_t, 3) << 6)   /* HAP[2:1] */

#define PMD_S2_RDONLY		(_AT(pmdval_t, 1) << 6)   /* HAP[2:1] */
#define PMD_S2_RDWR		(_AT(pmdval_t, 3) << 6)   /* HAP[2:1] */

/*
 * Memory Attribute override for Stage-2 (MemAttr[3:0])
 */
#define PTE_S2_MEMATTR(t)	(_AT(pteval_t, (t)) << 2)
#define PTE_S2_MEMATTR_MASK	(_AT(pteval_t, 0xf) << 2)

/*
 * EL2/HYP PTE/PMD definitions
 */
#define PMD_HYP			PMD_SECT_USER
#define PTE_HYP			PTE_USER

/*
 * Highest possible physical address supported.
 */
#define PHYS_MASK_SHIFT		(48)
#define PHYS_MASK		((UL(1) << PHYS_MASK_SHIFT) - 1)

/*
 * TCR flags.
 */
#define TCR_T0SZ_OFFSET		0
#define TCR_T1SZ_OFFSET		16
#define TCR_T0SZ(x)		((UL(64) - (x)) << TCR_T0SZ_OFFSET)
#define TCR_T1SZ(x)		((UL(64) - (x)) << TCR_T1SZ_OFFSET)
#define TCR_TxSZ(x)		(TCR_T0SZ(x) | TCR_T1SZ(x))
#define TCR_TxSZ_WIDTH		6
#define TCR_IRGN_NC		((UL(0) << 8) | (UL(0) << 24))
#define TCR_IRGN_WBWA		((UL(1) << 8) | (UL(1) << 24))
#define TCR_IRGN_WT		((UL(2) << 8) | (UL(2) << 24))
#define TCR_IRGN_WBnWA		((UL(3) << 8) | (UL(3) << 24))
#define TCR_IRGN_MASK		((UL(3) << 8) | (UL(3) << 24))
#define TCR_ORGN_NC		((UL(0) << 10) | (UL(0) << 26))
#define TCR_ORGN_WBWA		((UL(1) << 10) | (UL(1) << 26))
#define TCR_ORGN_WT		((UL(2) << 10) | (UL(2) << 26))
#define TCR_ORGN_WBnWA		((UL(3) << 10) | (UL(3) << 26))
#define TCR_ORGN_MASK		((UL(3) << 10) | (UL(3) << 26))
#define TCR_SHARED		((UL(3) << 12) | (UL(3) << 28))
#define TCR_TG0_4K		(UL(0) << 14)
#define TCR_TG0_64K		(UL(1) << 14)
#define TCR_TG0_16K		(UL(2) << 14)
#define TCR_TG1_16K		(UL(1) << 30)
#define TCR_TG1_4K		(UL(2) << 30)
#define TCR_TG1_64K		(UL(3) << 30)
#define TCR_ASID16		(UL(1) << 36)
#define TCR_TBI0		(UL(1) << 37)
#define TCR_HA			(UL(1) << 39)
#define TCR_HD			(UL(1) << 40)

#endif
Commit	Line	Data
4f04d8f0 CM	1	/*
	2	* Copyright (C) 2012 ARM Ltd.
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License version 2 as
	6	* published by the Free Software Foundation.
	7	*
	8	* This program is distributed in the hope that it will be useful,
	9	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	10	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	11	* GNU General Public License for more details.
	12	*
	13	* You should have received a copy of the GNU General Public License
	14	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	15	*/
	16	#ifndef __ASM_PGTABLE_HWDEF_H
	17	#define __ASM_PGTABLE_HWDEF_H
	18
6b4fee24 CM	19	#define PTRS_PER_PTE (1 << (PAGE_SHIFT - 3))
	20
	21	/*
	22	* PMD_SHIFT determines the size a level 2 page table entry can map.
	23	*/
9f25e6ad	24	#if CONFIG_PGTABLE_LEVELS > 2
6b4fee24 CM	25	#define PMD_SHIFT ((PAGE_SHIFT - 3) * 2 + 3)
	26	#define PMD_SIZE (_AC(1, UL) << PMD_SHIFT)
	27	#define PMD_MASK (~(PMD_SIZE-1))
	28	#define PTRS_PER_PMD PTRS_PER_PTE
	29	#endif
	30
	31	/*
	32	* PUD_SHIFT determines the size a level 1 page table entry can map.
	33	*/
9f25e6ad	34	#if CONFIG_PGTABLE_LEVELS > 3
6b4fee24 CM	35	#define PUD_SHIFT ((PAGE_SHIFT - 3) * 3 + 3)
	36	#define PUD_SIZE (_AC(1, UL) << PUD_SHIFT)
	37	#define PUD_MASK (~(PUD_SIZE-1))
	38	#define PTRS_PER_PUD PTRS_PER_PTE
4f04d8f0 CM	39	#endif
4f04d8f0 CM	40
6b4fee24 CM	41	/*
	42	* PGDIR_SHIFT determines the size a top-level page table entry can map
	43	* (depending on the configuration, this level can be 0, 1 or 2).
	44	*/
9f25e6ad	45	#define PGDIR_SHIFT ((PAGE_SHIFT - 3) * CONFIG_PGTABLE_LEVELS + 3)
6b4fee24 CM	46	#define PGDIR_SIZE (_AC(1, UL) << PGDIR_SHIFT)
	47	#define PGDIR_MASK (~(PGDIR_SIZE-1))
	48	#define PTRS_PER_PGD (1 << (VA_BITS - PGDIR_SHIFT))
	49
	50	/*
	51	* Section address mask and size definitions.
	52	*/
	53	#define SECTION_SHIFT PMD_SHIFT
	54	#define SECTION_SIZE (_AC(1, UL) << SECTION_SHIFT)
	55	#define SECTION_MASK (~(SECTION_SIZE-1))
	56
4f04d8f0 CM	57	/*
	58	* Hardware page table definitions.
	59	*
084bd298 SC	60	* Level 1 descriptor (PUD).
084bd298 SC	61	*/
c79b954b	62	#define PUD_TYPE_TABLE (_AT(pudval_t, 3) << 0)
084bd298	63	#define PUD_TABLE_BIT (_AT(pgdval_t, 1) << 1)
206a2a73 SC	64	#define PUD_TYPE_MASK (_AT(pgdval_t, 3) << 0)
206a2a73 SC	65	#define PUD_TYPE_SECT (_AT(pgdval_t, 1) << 0)
084bd298 SC	66
084bd298 SC	67	/*
4f04d8f0 CM	68	* Level 2 descriptor (PMD).
	69	*/
	70	#define PMD_TYPE_MASK (_AT(pmdval_t, 3) << 0)
	71	#define PMD_TYPE_FAULT (_AT(pmdval_t, 0) << 0)
	72	#define PMD_TYPE_TABLE (_AT(pmdval_t, 3) << 0)
	73	#define PMD_TYPE_SECT (_AT(pmdval_t, 1) << 0)
084bd298	74	#define PMD_TABLE_BIT (_AT(pmdval_t, 1) << 1)
4f04d8f0 CM	75
	76	/*
	77	* Section
	78	*/
af074848	79	#define PMD_SECT_VALID (_AT(pmdval_t, 1) << 0)
db4ed53c	80	#define PMD_SECT_PROT_NONE (_AT(pmdval_t, 1) << 58)
af074848 SC	81	#define PMD_SECT_USER (_AT(pmdval_t, 1) << 6) /* AP[1] */
af074848 SC	82	#define PMD_SECT_RDONLY (_AT(pmdval_t, 1) << 7) /* AP[2] */
4f04d8f0 CM	83	#define PMD_SECT_S (_AT(pmdval_t, 3) << 8)
	84	#define PMD_SECT_AF (_AT(pmdval_t, 1) << 10)
	85	#define PMD_SECT_NG (_AT(pmdval_t, 1) << 11)
8e620b04 CM	86	#define PMD_SECT_PXN (_AT(pmdval_t, 1) << 53)
8e620b04 CM	87	#define PMD_SECT_UXN (_AT(pmdval_t, 1) << 54)
4f04d8f0 CM	88
	89	/*
	90	* AttrIndx[2:0] encoding (mapping attributes defined in the MAIR* registers).
	91	*/
	92	#define PMD_ATTRINDX(t) (_AT(pmdval_t, (t)) << 2)
	93	#define PMD_ATTRINDX_MASK (_AT(pmdval_t, 7) << 2)
	94
	95	/*
	96	* Level 3 descriptor (PTE).
	97	*/
	98	#define PTE_TYPE_MASK (_AT(pteval_t, 3) << 0)
	99	#define PTE_TYPE_FAULT (_AT(pteval_t, 0) << 0)
	100	#define PTE_TYPE_PAGE (_AT(pteval_t, 3) << 0)
084bd298	101	#define PTE_TABLE_BIT (_AT(pteval_t, 1) << 1)
4f04d8f0 CM	102	#define PTE_USER (_AT(pteval_t, 1) << 6) /* AP[1] */
	103	#define PTE_RDONLY (_AT(pteval_t, 1) << 7) /* AP[2] */
	104	#define PTE_SHARED (_AT(pteval_t, 3) << 8) /* SH[1:0], inner shareable */
	105	#define PTE_AF (_AT(pteval_t, 1) << 10) /* Access Flag */
	106	#define PTE_NG (_AT(pteval_t, 1) << 11) /* nG */
2f4b829c	107	#define PTE_DBM (_AT(pteval_t, 1) << 51) /* Dirty Bit Management */
8e620b04 CM	108	#define PTE_PXN (_AT(pteval_t, 1) << 53) /* Privileged XN */
8e620b04 CM	109	#define PTE_UXN (_AT(pteval_t, 1) << 54) /* User XN */
4f04d8f0 CM	110
	111	/*
	112	* AttrIndx[2:0] encoding (mapping attributes defined in the MAIR* registers).
	113	*/
	114	#define PTE_ATTRINDX(t) (_AT(pteval_t, (t)) << 2)
	115	#define PTE_ATTRINDX_MASK (_AT(pteval_t, 7) << 2)
	116
36311607 MZ	117	/*
	118	* 2nd stage PTE definitions
	119	*/
	120	#define PTE_S2_RDONLY (_AT(pteval_t, 1) << 6) /* HAP[2:1] */
	121	#define PTE_S2_RDWR (_AT(pteval_t, 3) << 6) /* HAP[2:1] */
	122
8199ed0e	123	#define PMD_S2_RDONLY (_AT(pmdval_t, 1) << 6) /* HAP[2:1] */
ad361f09 CD	124	#define PMD_S2_RDWR (_AT(pmdval_t, 3) << 6) /* HAP[2:1] */
ad361f09 CD	125
36311607 MZ	126	/*
	127	* Memory Attribute override for Stage-2 (MemAttr[3:0])
	128	*/
	129	#define PTE_S2_MEMATTR(t) (_AT(pteval_t, (t)) << 2)
	130	#define PTE_S2_MEMATTR_MASK (_AT(pteval_t, 0xf) << 2)
	131
	132	/*
	133	* EL2/HYP PTE/PMD definitions
	134	*/
	135	#define PMD_HYP PMD_SECT_USER
	136	#define PTE_HYP PTE_USER
	137
4f04d8f0	138	/*
87366d8c	139	* Highest possible physical address supported.
4f04d8f0	140	*/
87366d8c	141	#define PHYS_MASK_SHIFT (48)
4f04d8f0 CM	142	#define PHYS_MASK ((UL(1) << PHYS_MASK_SHIFT) - 1)
	143
	144	/*
	145	* TCR flags.
	146	*/
dd006da2 AB	147	#define TCR_T0SZ_OFFSET 0
	148	#define TCR_T1SZ_OFFSET 16
	149	#define TCR_T0SZ(x) ((UL(64) - (x)) << TCR_T0SZ_OFFSET)
	150	#define TCR_T1SZ(x) ((UL(64) - (x)) << TCR_T1SZ_OFFSET)
	151	#define TCR_TxSZ(x) (TCR_T0SZ(x) \| TCR_T1SZ(x))
	152	#define TCR_TxSZ_WIDTH 6
4f04d8f0 CM	153	#define TCR_IRGN_NC ((UL(0) << 8) \| (UL(0) << 24))
	154	#define TCR_IRGN_WBWA ((UL(1) << 8) \| (UL(1) << 24))
	155	#define TCR_IRGN_WT ((UL(2) << 8) \| (UL(2) << 24))
	156	#define TCR_IRGN_WBnWA ((UL(3) << 8) \| (UL(3) << 24))
	157	#define TCR_IRGN_MASK ((UL(3) << 8) \| (UL(3) << 24))
	158	#define TCR_ORGN_NC ((UL(0) << 10) \| (UL(0) << 26))
	159	#define TCR_ORGN_WBWA ((UL(1) << 10) \| (UL(1) << 26))
	160	#define TCR_ORGN_WT ((UL(2) << 10) \| (UL(2) << 26))
	161	#define TCR_ORGN_WBnWA ((UL(3) << 10) \| (UL(3) << 26))
	162	#define TCR_ORGN_MASK ((UL(3) << 10) \| (UL(3) << 26))
	163	#define TCR_SHARED ((UL(3) << 12) \| (UL(3) << 28))
35a86976	164	#define TCR_TG0_4K (UL(0) << 14)
4f04d8f0	165	#define TCR_TG0_64K (UL(1) << 14)
35a86976 CM	166	#define TCR_TG0_16K (UL(2) << 14)
	167	#define TCR_TG1_16K (UL(1) << 30)
	168	#define TCR_TG1_4K (UL(2) << 30)
	169	#define TCR_TG1_64K (UL(3) << 30)
4f04d8f0	170	#define TCR_ASID16 (UL(1) << 36)
d50240a5	171	#define TCR_TBI0 (UL(1) << 37)
2f4b829c CM	172	#define TCR_HA (UL(1) << 39)
2f4b829c CM	173	#define TCR_HD (UL(1) << 40)
4f04d8f0 CM	174
4f04d8f0 CM	175	#endif