projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
arm64: mm: move pte_* macros
[deliverable/linux.git] / arch / arm64 / include / asm / pgtable.h
CommitLineData
4f04d8f0
CM		 1/*
2 * Copyright (C) 2012 ARM Ltd.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16#ifndef __ASM_PGTABLE_H
17#define __ASM_PGTABLE_H
18
2f4b829c 19#include <asm/bug.h>
4f04d8f0
CM		 20#include <asm/proc-fns.h>
21
22#include <asm/memory.h>
23#include <asm/pgtable-hwdef.h>
24
25/*
26 * Software defined PTE bits definition.
27 */
a6fadf7e 28#define PTE_VALID (_AT(pteval_t, 1) << 0)
bf950040 29#define PTE_WRITE (PTE_DBM) /* same as DBM (51) */
4f04d8f0
CM		 30#define PTE_DIRTY (_AT(pteval_t, 1) << 55)
31#define PTE_SPECIAL (_AT(pteval_t, 1) << 56)
3676f9ef 32#define PTE_PROT_NONE (_AT(pteval_t, 1) << 58) /* only when !PTE_VALID */
4f04d8f0
CM		 33
34/*
35 * VMALLOC and SPARSEMEM_VMEMMAP ranges.
08375198
CM		 36 *
37 * VMEMAP_SIZE: allows the whole VA space to be covered by a struct page array
38 * (rounded up to PUD_SIZE).
39 * VMALLOC_START: beginning of the kernel VA space
40 * VMALLOC_END: extends to the available space below vmmemmap, PCI I/O space,
41 * fixed mappings and modules
4f04d8f0 42 */
08375198 43#define VMEMMAP_SIZE ALIGN((1UL << (VA_BITS - PAGE_SHIFT)) * sizeof(struct page), PUD_SIZE)
39d114dd
AR		 44
45#ifndef CONFIG_KASAN
127db024 46#define VMALLOC_START (VA_START)
39d114dd
AR		 47#else
48#include <asm/kasan.h>
49#define VMALLOC_START (KASAN_SHADOW_END + SZ_64K)
50#endif
51
08375198 52#define VMALLOC_END (PAGE_OFFSET - PUD_SIZE - VMEMMAP_SIZE - SZ_64K)
4f04d8f0
CM		 53
54#define vmemmap ((struct page *)(VMALLOC_END + SZ_64K))
55
d016bf7e 56#define FIRST_USER_ADDRESS 0UL
4f04d8f0
CM		 57
58#ifndef __ASSEMBLY__
2f4b829c
CM		 59
60#include <linux/mmdebug.h>
61
4f04d8f0
CM		 62extern void __pte_error(const char *file, int line, unsigned long val);
63extern void __pmd_error(const char *file, int line, unsigned long val);
c79b954b 64extern void __pud_error(const char *file, int line, unsigned long val);
4f04d8f0
CM		 65extern void __pgd_error(const char *file, int line, unsigned long val);
66
a501e324
CM		 67#define PROT_DEFAULT (PTE_TYPE_PAGE | PTE_AF | PTE_SHARED)
68#define PROT_SECT_DEFAULT (PMD_TYPE_SECT | PMD_SECT_AF | PMD_SECT_S)
4f04d8f0 69
ac15bd63
CM		 70#define PROT_DEVICE_nGnRnE (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_DIRTY | PTE_WRITE | PTE_ATTRINDX(MT_DEVICE_nGnRnE))
71#define PROT_DEVICE_nGnRE (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_DIRTY | PTE_WRITE | PTE_ATTRINDX(MT_DEVICE_nGnRE))
72#define PROT_NORMAL_NC (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_DIRTY | PTE_WRITE | PTE_ATTRINDX(MT_NORMAL_NC))
73#define PROT_NORMAL_WT (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_DIRTY | PTE_WRITE | PTE_ATTRINDX(MT_NORMAL_WT))
74#define PROT_NORMAL (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_DIRTY | PTE_WRITE | PTE_ATTRINDX(MT_NORMAL))
4f04d8f0 75
a501e324
CM		 76#define PROT_SECT_DEVICE_nGnRE (PROT_SECT_DEFAULT | PMD_SECT_PXN | PMD_SECT_UXN | PMD_ATTRINDX(MT_DEVICE_nGnRE))
77#define PROT_SECT_NORMAL (PROT_SECT_DEFAULT | PMD_SECT_PXN | PMD_SECT_UXN | PMD_ATTRINDX(MT_NORMAL))
78#define PROT_SECT_NORMAL_EXEC (PROT_SECT_DEFAULT | PMD_SECT_UXN | PMD_ATTRINDX(MT_NORMAL))
a6fadf7e 79
a501e324 80#define _PAGE_DEFAULT (PROT_DEFAULT | PTE_ATTRINDX(MT_NORMAL))
4f04d8f0 81
a501e324 82#define PAGE_KERNEL __pgprot(_PAGE_DEFAULT | PTE_PXN | PTE_UXN | PTE_DIRTY | PTE_WRITE)
fb226c3d 83#define PAGE_KERNEL_RO __pgprot(_PAGE_DEFAULT | PTE_PXN | PTE_UXN | PTE_DIRTY | PTE_RDONLY)
ac15bd63 84#define PAGE_KERNEL_ROX __pgprot(_PAGE_DEFAULT | PTE_UXN | PTE_DIRTY | PTE_RDONLY)
a501e324 85#define PAGE_KERNEL_EXEC __pgprot(_PAGE_DEFAULT | PTE_UXN | PTE_DIRTY | PTE_WRITE)
06f90d25 86#define PAGE_KERNEL_EXEC_CONT __pgprot(_PAGE_DEFAULT | PTE_UXN | PTE_DIRTY | PTE_WRITE | PTE_CONT)
8e620b04 87
a501e324 88#define PAGE_HYP __pgprot(_PAGE_DEFAULT | PTE_HYP)
36311607
MZ		 89#define PAGE_HYP_DEVICE __pgprot(PROT_DEVICE_nGnRE | PTE_HYP)
90
a501e324 91#define PAGE_S2 __pgprot(PROT_DEFAULT | PTE_S2_MEMATTR(MT_S2_NORMAL) | PTE_S2_RDONLY)
4a513fb0 92#define PAGE_S2_DEVICE __pgprot(PROT_DEFAULT | PTE_S2_MEMATTR(MT_S2_DEVICE_nGnRE) | PTE_S2_RDONLY | PTE_UXN)
36311607 93
1a541b4e 94#define PAGE_NONE __pgprot(((_PAGE_DEFAULT) & ~PTE_VALID) | PTE_PROT_NONE | PTE_PXN | PTE_UXN)
a501e324
CM		 95#define PAGE_SHARED __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN | PTE_UXN | PTE_WRITE)
96#define PAGE_SHARED_EXEC __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN | PTE_WRITE)
97#define PAGE_COPY __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN | PTE_UXN)
98#define PAGE_COPY_EXEC __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN)
99#define PAGE_READONLY __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN | PTE_UXN)
100#define PAGE_READONLY_EXEC __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN)
a501e324
CM		 101
102#define __P000 PAGE_NONE
103#define __P001 PAGE_READONLY
104#define __P010 PAGE_COPY
105#define __P011 PAGE_COPY
5a0fdfad 106#define __P100 PAGE_READONLY_EXEC
a501e324
CM		 107#define __P101 PAGE_READONLY_EXEC
108#define __P110 PAGE_COPY_EXEC
109#define __P111 PAGE_COPY_EXEC
110
111#define __S000 PAGE_NONE
112#define __S001 PAGE_READONLY
113#define __S010 PAGE_SHARED
114#define __S011 PAGE_SHARED
5a0fdfad 115#define __S100 PAGE_READONLY_EXEC
a501e324
CM		 116#define __S101 PAGE_READONLY_EXEC
117#define __S110 PAGE_SHARED_EXEC
118#define __S111 PAGE_SHARED_EXEC
4f04d8f0 119
4f04d8f0
CM		 120/*
121 * ZERO_PAGE is a global shared page that is always zero: used
122 * for zero-mapped memory areas etc..
123 */
5227cfa7
MR		 124extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)];
125#define ZERO_PAGE(vaddr) virt_to_page(empty_zero_page)
4f04d8f0 126
7078db46
CM		 127#define pte_ERROR(pte) __pte_error(__FILE__, __LINE__, pte_val(pte))
128
4f04d8f0
CM		 129#define pte_pfn(pte) ((pte_val(pte) & PHYS_MASK) >> PAGE_SHIFT)
130
131#define pfn_pte(pfn,prot) (__pte(((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)))
132
133#define pte_none(pte) (!pte_val(pte))
134#define pte_clear(mm,addr,ptep) set_pte(ptep, __pte(0))
135#define pte_page(pte) (pfn_to_page(pte_pfn(pte)))
7078db46 136
4f04d8f0
CM		 137/*
138 * The following only work if pte_present(). Undefined behaviour otherwise.
139 */
84fe6826 140#define pte_present(pte) (!!(pte_val(pte) & (PTE_VALID | PTE_PROT_NONE)))
84fe6826
SC		 141#define pte_young(pte) (!!(pte_val(pte) & PTE_AF))
142#define pte_special(pte) (!!(pte_val(pte) & PTE_SPECIAL))
143#define pte_write(pte) (!!(pte_val(pte) & PTE_WRITE))
8e620b04 144#define pte_exec(pte) (!(pte_val(pte) & PTE_UXN))
93ef666a 145#define pte_cont(pte) (!!(pte_val(pte) & PTE_CONT))
ac15bd63 146#define pte_user(pte) (!!(pte_val(pte) & PTE_USER))
4f04d8f0 147
2f4b829c 148#ifdef CONFIG_ARM64_HW_AFDBM
b847415c 149#define pte_hw_dirty(pte) (pte_write(pte) && !(pte_val(pte) & PTE_RDONLY))
2f4b829c
CM		 150#else
151#define pte_hw_dirty(pte) (0)
152#endif
153#define pte_sw_dirty(pte) (!!(pte_val(pte) & PTE_DIRTY))
154#define pte_dirty(pte) (pte_sw_dirty(pte) || pte_hw_dirty(pte))
155
766ffb69 156#define pte_valid(pte) (!!(pte_val(pte) & PTE_VALID))
7f0b1bf0
CM		 157#define pte_valid_not_user(pte) \
158 ((pte_val(pte) & (PTE_VALID | PTE_USER)) == PTE_VALID)
76c714be
WD		 159#define pte_valid_young(pte) \
160 ((pte_val(pte) & (PTE_VALID | PTE_AF)) == (PTE_VALID | PTE_AF))
161
162/*
163 * Could the pte be present in the TLB? We must check mm_tlb_flush_pending
164 * so that we don't erroneously return false for pages that have been
165 * remapped as PROT_NONE but are yet to be flushed from the TLB.
166 */
167#define pte_accessible(mm, pte) \
168 (mm_tlb_flush_pending(mm) ? pte_present(pte) : pte_valid_young(pte))
4f04d8f0 169
b6d4f280 170static inline pte_t clear_pte_bit(pte_t pte, pgprot_t prot)
44b6dfc5 171{
b6d4f280 172 pte_val(pte) &= ~pgprot_val(prot);
44b6dfc5
SC		 173 return pte;
174}
175
b6d4f280 176static inline pte_t set_pte_bit(pte_t pte, pgprot_t prot)
44b6dfc5 177{
b6d4f280 178 pte_val(pte) |= pgprot_val(prot);
44b6dfc5
SC		 179 return pte;
180}
181
b6d4f280
LA		 182static inline pte_t pte_wrprotect(pte_t pte)
183{
184 return clear_pte_bit(pte, __pgprot(PTE_WRITE));
185}
186
187static inline pte_t pte_mkwrite(pte_t pte)
188{
189 return set_pte_bit(pte, __pgprot(PTE_WRITE));
190}
191
44b6dfc5
SC		 192static inline pte_t pte_mkclean(pte_t pte)
193{
b6d4f280 194 return clear_pte_bit(pte, __pgprot(PTE_DIRTY));
44b6dfc5
SC		 195}
196
197static inline pte_t pte_mkdirty(pte_t pte)
198{
b6d4f280 199 return set_pte_bit(pte, __pgprot(PTE_DIRTY));
44b6dfc5
SC		 200}
201
202static inline pte_t pte_mkold(pte_t pte)
203{
b6d4f280 204 return clear_pte_bit(pte, __pgprot(PTE_AF));
44b6dfc5
SC		 205}
206
207static inline pte_t pte_mkyoung(pte_t pte)
208{
b6d4f280 209 return set_pte_bit(pte, __pgprot(PTE_AF));
44b6dfc5
SC		 210}
211
212static inline pte_t pte_mkspecial(pte_t pte)
213{
b6d4f280 214 return set_pte_bit(pte, __pgprot(PTE_SPECIAL));
44b6dfc5 215}
4f04d8f0 216
93ef666a
JL		 217static inline pte_t pte_mkcont(pte_t pte)
218{
66b3923a
DW		 219 pte = set_pte_bit(pte, __pgprot(PTE_CONT));
220 return set_pte_bit(pte, __pgprot(PTE_TYPE_PAGE));
93ef666a
JL		 221}
222
223static inline pte_t pte_mknoncont(pte_t pte)
224{
225 return clear_pte_bit(pte, __pgprot(PTE_CONT));
226}
227
66b3923a
DW		 228static inline pmd_t pmd_mkcont(pmd_t pmd)
229{
230 return __pmd(pmd_val(pmd) | PMD_SECT_CONT);
231}
232
4f04d8f0
CM		 233static inline void set_pte(pte_t *ptep, pte_t pte)
234{
235 *ptep = pte;
7f0b1bf0
CM		 236
237 /*
238 * Only if the new pte is valid and kernel, otherwise TLB maintenance
239 * or update_mmu_cache() have the necessary barriers.
240 */
241 if (pte_valid_not_user(pte)) {
242 dsb(ishst);
243 isb();
244 }
4f04d8f0
CM		 245}
246
2f4b829c
CM		 247struct mm_struct;
248struct vm_area_struct;
249
4f04d8f0
CM		 250extern void __sync_icache_dcache(pte_t pteval, unsigned long addr);
251
2f4b829c
CM		 252/*
253 * PTE bits configuration in the presence of hardware Dirty Bit Management
254 * (PTE_WRITE == PTE_DBM):
255 *
256 * Dirty Writable | PTE_RDONLY PTE_WRITE PTE_DIRTY (sw)
257 * 0 0 | 1 0 0
258 * 0 1 | 1 1 0
259 * 1 0 | 1 0 1
260 * 1 1 | 0 1 x
261 *
262 * When hardware DBM is not present, the sofware PTE_DIRTY bit is updated via
263 * the page fault mechanism. Checking the dirty status of a pte becomes:
264 *
b847415c 265 * PTE_DIRTY || (PTE_WRITE && !PTE_RDONLY)
2f4b829c 266 */
4f04d8f0
CM		 267static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
268 pte_t *ptep, pte_t pte)
269{
ac15bd63 270 if (pte_valid(pte)) {
2f4b829c 271 if (pte_sw_dirty(pte) && pte_write(pte))
c2c93e5b
SC		 272 pte_val(pte) &= ~PTE_RDONLY;
273 else
274 pte_val(pte) |= PTE_RDONLY;
ac15bd63
CM		 275 if (pte_user(pte) && pte_exec(pte) && !pte_special(pte))
276 __sync_icache_dcache(pte, addr);
02522463
WD		 277 }
278
2f4b829c
CM		 279 /*
280 * If the existing pte is valid, check for potential race with
281 * hardware updates of the pte (ptep_set_access_flags safely changes
282 * valid ptes without going through an invalid entry).
283 */
82d34008
CM		 284 if (IS_ENABLED(CONFIG_ARM64_HW_AFDBM) &&
285 pte_valid(*ptep) && pte_valid(pte)) {
286 VM_WARN_ONCE(!pte_young(pte),
287 "%s: racy access flag clearing: 0x%016llx -> 0x%016llx",
288 __func__, pte_val(*ptep), pte_val(pte));
289 VM_WARN_ONCE(pte_write(*ptep) && !pte_dirty(pte),
290 "%s: racy dirty state clearing: 0x%016llx -> 0x%016llx",
291 __func__, pte_val(*ptep), pte_val(pte));
2f4b829c
CM		 292 }
293
4f04d8f0
CM		 294 set_pte(ptep, pte);
295}
296
297/*
298 * Huge pte definitions.
299 */
084bd298
SC		 300#define pte_huge(pte) (!(pte_val(pte) & PTE_TABLE_BIT))
301#define pte_mkhuge(pte) (__pte(pte_val(pte) & ~PTE_TABLE_BIT))
302
303/*
304 * Hugetlb definitions.
305 */
66b3923a 306#define HUGE_MAX_HSTATE 4
084bd298
SC		 307#define HPAGE_SHIFT PMD_SHIFT
308#define HPAGE_SIZE (_AC(1, UL) << HPAGE_SHIFT)
309#define HPAGE_MASK (~(HPAGE_SIZE - 1))
310#define HUGETLB_PAGE_ORDER (HPAGE_SHIFT - PAGE_SHIFT)
4f04d8f0 311
4f04d8f0
CM		 312#define __HAVE_ARCH_PTE_SPECIAL
313
29e56940
SC		 314static inline pte_t pud_pte(pud_t pud)
315{
316 return __pte(pud_val(pud));
317}
318
319static inline pmd_t pud_pmd(pud_t pud)
320{
321 return __pmd(pud_val(pud));
322}
323
9c7e535f
SC		 324static inline pte_t pmd_pte(pmd_t pmd)
325{
326 return __pte(pmd_val(pmd));
327}
af074848 328
9c7e535f
SC		 329static inline pmd_t pte_pmd(pte_t pte)
330{
331 return __pmd(pte_val(pte));
332}
af074848 333
8ce837ce
AB		 334static inline pgprot_t mk_sect_prot(pgprot_t prot)
335{
336 return __pgprot(pgprot_val(prot) & ~PTE_TABLE_BIT);
337}
338
af074848
SC		 339/*
340 * THP definitions.
341 */
af074848
SC		 342
343#ifdef CONFIG_TRANSPARENT_HUGEPAGE
344#define pmd_trans_huge(pmd) (pmd_val(pmd) && !(pmd_val(pmd) & PMD_TABLE_BIT))
29e56940 345#endif /* CONFIG_TRANSPARENT_HUGEPAGE */
af074848 346
c164e038 347#define pmd_dirty(pmd) pte_dirty(pmd_pte(pmd))
9c7e535f
SC		 348#define pmd_young(pmd) pte_young(pmd_pte(pmd))
349#define pmd_wrprotect(pmd) pte_pmd(pte_wrprotect(pmd_pte(pmd)))
9c7e535f
SC		 350#define pmd_mkold(pmd) pte_pmd(pte_mkold(pmd_pte(pmd)))
351#define pmd_mkwrite(pmd) pte_pmd(pte_mkwrite(pmd_pte(pmd)))
05ee26d9 352#define pmd_mkclean(pmd) pte_pmd(pte_mkclean(pmd_pte(pmd)))
9c7e535f
SC		 353#define pmd_mkdirty(pmd) pte_pmd(pte_mkdirty(pmd_pte(pmd)))
354#define pmd_mkyoung(pmd) pte_pmd(pte_mkyoung(pmd_pte(pmd)))
e3a920af 355#define pmd_mknotpresent(pmd) (__pmd(pmd_val(pmd) & ~PMD_TYPE_MASK))
af074848 356
9c7e535f
SC		 357#define __HAVE_ARCH_PMD_WRITE
358#define pmd_write(pmd) pte_write(pmd_pte(pmd))
af074848
SC		 359
360#define pmd_mkhuge(pmd) (__pmd(pmd_val(pmd) & ~PMD_TABLE_BIT))
361
362#define pmd_pfn(pmd) (((pmd_val(pmd) & PMD_MASK) & PHYS_MASK) >> PAGE_SHIFT)
363#define pfn_pmd(pfn,prot) (__pmd(((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)))
364#define mk_pmd(page,prot) pfn_pmd(page_to_pfn(page),prot)
365
29e56940 366#define pud_write(pud) pte_write(pud_pte(pud))
206a2a73 367#define pud_pfn(pud) (((pud_val(pud) & PUD_MASK) & PHYS_MASK) >> PAGE_SHIFT)
af074848 368
ceb21835 369#define set_pmd_at(mm, addr, pmdp, pmd) set_pte_at(mm, addr, (pte_t *)pmdp, pmd_pte(pmd))
af074848
SC		 370
371static inline int has_transparent_hugepage(void)
372{
373 return 1;
374}
375
a501e324
CM		 376#define __pgprot_modify(prot,mask,bits) \
377 __pgprot((pgprot_val(prot) & ~(mask)) | (bits))
378
4f04d8f0
CM		 379/*
380 * Mark the prot value as uncacheable and unbufferable.
381 */
382#define pgprot_noncached(prot) \
de2db743 383 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRnE) | PTE_PXN | PTE_UXN)
4f04d8f0 384#define pgprot_writecombine(prot) \
de2db743 385 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN)
d1e6dc91
LD		 386#define pgprot_device(prot) \
387 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRE) | PTE_PXN | PTE_UXN)
4f04d8f0
CM		 388#define __HAVE_PHYS_MEM_ACCESS_PROT
389struct file;
390extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
391 unsigned long size, pgprot_t vma_prot);
392
393#define pmd_none(pmd) (!pmd_val(pmd))
394#define pmd_present(pmd) (pmd_val(pmd))
395
396#define pmd_bad(pmd) (!(pmd_val(pmd) & 2))
397
36311607
MZ		 398#define pmd_table(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \
399 PMD_TYPE_TABLE)
400#define pmd_sect(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \
401 PMD_TYPE_SECT)
402
f3b766a2 403#ifdef CONFIG_ARM64_64K_PAGES
206a2a73 404#define pud_sect(pud) (0)
523d6e9f 405#define pud_table(pud) (1)
206a2a73
SC		 406#else
407#define pud_sect(pud) ((pud_val(pud) & PUD_TYPE_MASK) == \
408 PUD_TYPE_SECT)
523d6e9f 409#define pud_table(pud) ((pud_val(pud) & PUD_TYPE_MASK) == \
410 PUD_TYPE_TABLE)
206a2a73 411#endif
36311607 412
4f04d8f0
CM		 413static inline void set_pmd(pmd_t *pmdp, pmd_t pmd)
414{
415 *pmdp = pmd;
98f7685e 416 dsb(ishst);
7f0b1bf0 417 isb();
4f04d8f0
CM		 418}
419
420static inline void pmd_clear(pmd_t *pmdp)
421{
422 set_pmd(pmdp, __pmd(0));
423}
424
425static inline pte_t *pmd_page_vaddr(pmd_t pmd)
426{
427 return __va(pmd_val(pmd) & PHYS_MASK & (s32)PAGE_MASK);
428}
429
053520f7
MR		 430/* Find an entry in the third-level page table. */
431#define pte_index(addr) (((addr) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
432
433#define pte_offset_kernel(dir,addr) (pmd_page_vaddr(*(dir)) + pte_index(addr))
434
435#define pte_offset_map(dir,addr) pte_offset_kernel((dir), (addr))
436#define pte_offset_map_nested(dir,addr) pte_offset_kernel((dir), (addr))
437#define pte_unmap(pte) do { } while (0)
438#define pte_unmap_nested(pte) do { } while (0)
439
4f04d8f0
CM		 440#define pmd_page(pmd) pfn_to_page(__phys_to_pfn(pmd_val(pmd) & PHYS_MASK))
441
442/*
443 * Conversion functions: convert a page and protection to a page entry,
444 * and a page entry and page directory to the page they refer to.
445 */
446#define mk_pte(page,prot) pfn_pte(page_to_pfn(page),prot)
447
9f25e6ad 448#if CONFIG_PGTABLE_LEVELS > 2
4f04d8f0 449
7078db46
CM		 450#define pmd_ERROR(pmd) __pmd_error(__FILE__, __LINE__, pmd_val(pmd))
451
4f04d8f0
CM		 452#define pud_none(pud) (!pud_val(pud))
453#define pud_bad(pud) (!(pud_val(pud) & 2))
454#define pud_present(pud) (pud_val(pud))
455
456static inline void set_pud(pud_t *pudp, pud_t pud)
457{
458 *pudp = pud;
98f7685e 459 dsb(ishst);
7f0b1bf0 460 isb();
4f04d8f0
CM		 461}
462
463static inline void pud_clear(pud_t *pudp)
464{
465 set_pud(pudp, __pud(0));
466}
467
468static inline pmd_t *pud_page_vaddr(pud_t pud)
469{
470 return __va(pud_val(pud) & PHYS_MASK & (s32)PAGE_MASK);
471}
472
7078db46
CM		 473/* Find an entry in the second-level page table. */
474#define pmd_index(addr) (((addr) >> PMD_SHIFT) & (PTRS_PER_PMD - 1))
475
476static inline pmd_t *pmd_offset(pud_t *pud, unsigned long addr)
477{
478 return (pmd_t *)pud_page_vaddr(*pud) + pmd_index(addr);
479}
480
5d96e0cb 481#define pud_page(pud) pfn_to_page(__phys_to_pfn(pud_val(pud) & PHYS_MASK))
29e56940 482
9f25e6ad 483#endif /* CONFIG_PGTABLE_LEVELS > 2 */
4f04d8f0 484
9f25e6ad 485#if CONFIG_PGTABLE_LEVELS > 3
c79b954b 486
7078db46
CM		 487#define pud_ERROR(pud) __pud_error(__FILE__, __LINE__, pud_val(pud))
488
c79b954b
JL		 489#define pgd_none(pgd) (!pgd_val(pgd))
490#define pgd_bad(pgd) (!(pgd_val(pgd) & 2))
491#define pgd_present(pgd) (pgd_val(pgd))
492
493static inline void set_pgd(pgd_t *pgdp, pgd_t pgd)
494{
495 *pgdp = pgd;
496 dsb(ishst);
497}
498
499static inline void pgd_clear(pgd_t *pgdp)
500{
501 set_pgd(pgdp, __pgd(0));
502}
503
504static inline pud_t *pgd_page_vaddr(pgd_t pgd)
505{
506 return __va(pgd_val(pgd) & PHYS_MASK & (s32)PAGE_MASK);
507}
508
7078db46
CM		 509/* Find an entry in the frst-level page table. */
510#define pud_index(addr) (((addr) >> PUD_SHIFT) & (PTRS_PER_PUD - 1))
511
512static inline pud_t *pud_offset(pgd_t *pgd, unsigned long addr)
513{
514 return (pud_t *)pgd_page_vaddr(*pgd) + pud_index(addr);
515}
516
5d96e0cb
JL		 517#define pgd_page(pgd) pfn_to_page(__phys_to_pfn(pgd_val(pgd) & PHYS_MASK))
518
9f25e6ad 519#endif /* CONFIG_PGTABLE_LEVELS > 3 */
c79b954b 520
7078db46
CM		 521#define pgd_ERROR(pgd) __pgd_error(__FILE__, __LINE__, pgd_val(pgd))
522
4f04d8f0
CM		 523/* to find an entry in a page-table-directory */
524#define pgd_index(addr) (((addr) >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1))
525
526#define pgd_offset(mm, addr) ((mm)->pgd+pgd_index(addr))
527
528/* to find an entry in a kernel page-table-directory */
529#define pgd_offset_k(addr) pgd_offset(&init_mm, addr)
530
4f04d8f0
CM		 531static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
532{
a6fadf7e 533 const pteval_t mask = PTE_USER | PTE_PXN | PTE_UXN | PTE_RDONLY |
1a541b4e 534 PTE_PROT_NONE | PTE_VALID | PTE_WRITE;
2f4b829c
CM		 535 /* preserve the hardware dirty information */
536 if (pte_hw_dirty(pte))
62d96c71 537 pte = pte_mkdirty(pte);
4f04d8f0
CM		 538 pte_val(pte) = (pte_val(pte) & ~mask) | (pgprot_val(newprot) & mask);
539 return pte;
540}
541
9c7e535f
SC		 542static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot)
543{
544 return pte_pmd(pte_modify(pmd_pte(pmd), newprot));
545}
546
2f4b829c
CM		 547#ifdef CONFIG_ARM64_HW_AFDBM
548/*
549 * Atomic pte/pmd modifications.
550 */
551#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
552static inline int ptep_test_and_clear_young(struct vm_area_struct *vma,
553 unsigned long address,
554 pte_t *ptep)
555{
556 pteval_t pteval;
557 unsigned int tmp, res;
558
559 asm volatile("// ptep_test_and_clear_young\n"
560 " prfm pstl1strm, %2\n"
561 "1: ldxr %0, %2\n"
562 " ubfx %w3, %w0, %5, #1 // extract PTE_AF (young)\n"
563 " and %0, %0, %4 // clear PTE_AF\n"
564 " stxr %w1, %0, %2\n"
565 " cbnz %w1, 1b\n"
566 : "=&r" (pteval), "=&r" (tmp), "+Q" (pte_val(*ptep)), "=&r" (res)
567 : "L" (~PTE_AF), "I" (ilog2(PTE_AF)));
568
569 return res;
570}
571
572#ifdef CONFIG_TRANSPARENT_HUGEPAGE
573#define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG
574static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma,
575 unsigned long address,
576 pmd_t *pmdp)
577{
578 return ptep_test_and_clear_young(vma, address, (pte_t *)pmdp);
579}
580#endif /* CONFIG_TRANSPARENT_HUGEPAGE */
581
582#define __HAVE_ARCH_PTEP_GET_AND_CLEAR
583static inline pte_t ptep_get_and_clear(struct mm_struct *mm,
584 unsigned long address, pte_t *ptep)
585{
586 pteval_t old_pteval;
587 unsigned int tmp;
588
589 asm volatile("// ptep_get_and_clear\n"
590 " prfm pstl1strm, %2\n"
591 "1: ldxr %0, %2\n"
592 " stxr %w1, xzr, %2\n"
593 " cbnz %w1, 1b\n"
594 : "=&r" (old_pteval), "=&r" (tmp), "+Q" (pte_val(*ptep)));
595
596 return __pte(old_pteval);
597}
598
599#ifdef CONFIG_TRANSPARENT_HUGEPAGE
600#define __HAVE_ARCH_PMDP_GET_AND_CLEAR
601static inline pmd_t pmdp_get_and_clear(struct mm_struct *mm,
602 unsigned long address, pmd_t *pmdp)
603{
604 return pte_pmd(ptep_get_and_clear(mm, address, (pte_t *)pmdp));
605}
606#endif /* CONFIG_TRANSPARENT_HUGEPAGE */
607
608/*
609 * ptep_set_wrprotect - mark read-only while trasferring potential hardware
610 * dirty status (PTE_DBM && !PTE_RDONLY) to the software PTE_DIRTY bit.
611 */
612#define __HAVE_ARCH_PTEP_SET_WRPROTECT
613static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long address, pte_t *ptep)
614{
615 pteval_t pteval;
616 unsigned long tmp;
617
618 asm volatile("// ptep_set_wrprotect\n"
619 " prfm pstl1strm, %2\n"
620 "1: ldxr %0, %2\n"
621 " tst %0, %4 // check for hw dirty (!PTE_RDONLY)\n"
622 " csel %1, %3, xzr, eq // set PTE_DIRTY|PTE_RDONLY if dirty\n"
623 " orr %0, %0, %1 // if !dirty, PTE_RDONLY is already set\n"
624 " and %0, %0, %5 // clear PTE_WRITE/PTE_DBM\n"
625 " stxr %w1, %0, %2\n"
626 " cbnz %w1, 1b\n"
627 : "=&r" (pteval), "=&r" (tmp), "+Q" (pte_val(*ptep))
628 : "r" (PTE_DIRTY|PTE_RDONLY), "L" (PTE_RDONLY), "L" (~PTE_WRITE)
629 : "cc");
630}
631
632#ifdef CONFIG_TRANSPARENT_HUGEPAGE
633#define __HAVE_ARCH_PMDP_SET_WRPROTECT
634static inline void pmdp_set_wrprotect(struct mm_struct *mm,
635 unsigned long address, pmd_t *pmdp)
636{
637 ptep_set_wrprotect(mm, address, (pte_t *)pmdp);
638}
639#endif
640#endif /* CONFIG_ARM64_HW_AFDBM */
641
4f04d8f0
CM		 642extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
643extern pgd_t idmap_pg_dir[PTRS_PER_PGD];
644
4f04d8f0
CM		 645/*
646 * Encode and decode a swap entry:
3676f9ef 647 * bits 0-1: present (must be zero)
9b3e661e
KS		 648 * bits 2-7: swap type
649 * bits 8-57: swap offset
4f04d8f0 650 */
9b3e661e 651#define __SWP_TYPE_SHIFT 2
4f04d8f0 652#define __SWP_TYPE_BITS 6
9b3e661e 653#define __SWP_OFFSET_BITS 50
4f04d8f0
CM		 654#define __SWP_TYPE_MASK ((1 << __SWP_TYPE_BITS) - 1)
655#define __SWP_OFFSET_SHIFT (__SWP_TYPE_BITS + __SWP_TYPE_SHIFT)
3676f9ef 656#define __SWP_OFFSET_MASK ((1UL << __SWP_OFFSET_BITS) - 1)
4f04d8f0
CM		 657
658#define __swp_type(x) (((x).val >> __SWP_TYPE_SHIFT) & __SWP_TYPE_MASK)
3676f9ef 659#define __swp_offset(x) (((x).val >> __SWP_OFFSET_SHIFT) & __SWP_OFFSET_MASK)
4f04d8f0
CM		 660#define __swp_entry(type,offset) ((swp_entry_t) { ((type) << __SWP_TYPE_SHIFT) | ((offset) << __SWP_OFFSET_SHIFT) })
661
662#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
663#define __swp_entry_to_pte(swp) ((pte_t) { (swp).val })
664
665/*
666 * Ensure that there are not more swap files than can be encoded in the kernel
aad9061b 667 * PTEs.
4f04d8f0
CM		 668 */
669#define MAX_SWAPFILES_CHECK() BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > __SWP_TYPE_BITS)
670
4f04d8f0
CM		 671extern int kern_addr_valid(unsigned long addr);
672
673#include <asm-generic/pgtable.h>
674
39b5be9b
WD		 675void pgd_cache_init(void);
676#define pgtable_cache_init pgd_cache_init
4f04d8f0 677
cba3574f
WD		 678/*
679 * On AArch64, the cache coherency is handled via the set_pte_at() function.
680 */
681static inline void update_mmu_cache(struct vm_area_struct *vma,
682 unsigned long addr, pte_t *ptep)
683{
684 /*
120798d2
WD		 685 * We don't do anything here, so there's a very small chance of
686 * us retaking a user fault which we just fixed up. The alternative
687 * is doing a dsb(ishst), but that penalises the fastpath.
cba3574f 688 */
cba3574f
WD		 689}
690
691#define update_mmu_cache_pmd(vma, address, pmd) do { } while (0)
692
7db743c6
CM		 693#define kc_vaddr_to_offset(v) ((v) & ~VA_START)
694#define kc_offset_to_vaddr(o) ((o) | VA_START)
695
4f04d8f0
CM		 696#endif /* !__ASSEMBLY__ */
697
698#endif /* __ASM_PGTABLE_H */
Linux kernel - Deliverables
This page took 0.212009 seconds and 5 git commands to generate.