projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Merge remote-tracking branch 'iommu/next'
[deliverable/linux.git] / arch / arm64 / kernel / cpufeature.c
CommitLineData
359b7064
MZ		 1/*
2 * Contains CPU feature definitions
3 *
4 * Copyright (C) 2015 ARM Ltd.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
17 */
18
9cdf8ec4 19#define pr_fmt(fmt) "CPU features: " fmt
359b7064 20
3c739b57
SP		 21#include <linux/bsearch.h>
22#include <linux/sort.h>
359b7064
MZ		 23#include <linux/types.h>
24#include <asm/cpu.h>
25#include <asm/cpufeature.h>
dbb4e152 26#include <asm/cpu_ops.h>
13f417f3 27#include <asm/mmu_context.h>
338d4f49 28#include <asm/processor.h>
cdcf817b 29#include <asm/sysreg.h>
d88701be 30#include <asm/virt.h>
359b7064 31
9cdf8ec4
SP		 32unsigned long elf_hwcap __read_mostly;
33EXPORT_SYMBOL_GPL(elf_hwcap);
34
35#ifdef CONFIG_COMPAT
36#define COMPAT_ELF_HWCAP_DEFAULT \
37 (COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\
38 COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\
39 COMPAT_HWCAP_TLS|COMPAT_HWCAP_VFP|\
40 COMPAT_HWCAP_VFPv3|COMPAT_HWCAP_VFPv4|\
41 COMPAT_HWCAP_NEON|COMPAT_HWCAP_IDIV|\
42 COMPAT_HWCAP_LPAE)
43unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT;
44unsigned int compat_elf_hwcap2 __read_mostly;
45#endif
46
47DECLARE_BITMAP(cpu_hwcaps, ARM64_NCAPS);
48
efd9e03f
CM		 49DEFINE_STATIC_KEY_ARRAY_FALSE(cpu_hwcap_keys, ARM64_NCAPS);
50EXPORT_SYMBOL(cpu_hwcap_keys);
51
4f0a606b 52#define __ARM64_FTR_BITS(SIGNED, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
3c739b57 53 { \
4f0a606b 54 .sign = SIGNED, \
3c739b57
SP		 55 .strict = STRICT, \
56 .type = TYPE, \
57 .shift = SHIFT, \
58 .width = WIDTH, \
59 .safe_val = SAFE_VAL, \
60 }
61
0710cfdb 62/* Define a feature with unsigned values */
4f0a606b 63#define ARM64_FTR_BITS(STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
4f0a606b
SP		 64 __ARM64_FTR_BITS(FTR_UNSIGNED, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
65
0710cfdb
SP		 66/* Define a feature with a signed value */
67#define S_ARM64_FTR_BITS(STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
68 __ARM64_FTR_BITS(FTR_SIGNED, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
69
3c739b57
SP		 70#define ARM64_FTR_END \
71 { \
72 .width = 0, \
73 }
74
70544196
JM		 75/* meta feature for alternatives */
76static bool __maybe_unused
92406f0c
SP		 77cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry, int __unused);
78
70544196 79
5e49d73c 80static const struct arm64_ftr_bits ftr_id_aa64isar0[] = {
3c739b57
SP		 81 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 32, 32, 0),
82 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64ISAR0_RDM_SHIFT, 4, 0),
83 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 24, 4, 0),
84 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_ATOMICS_SHIFT, 4, 0),
85 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_CRC32_SHIFT, 4, 0),
86 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA2_SHIFT, 4, 0),
87 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA1_SHIFT, 4, 0),
88 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_AES_SHIFT, 4, 0),
89 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 4, 0), /* RAZ */
90 ARM64_FTR_END,
91};
92
5e49d73c 93static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = {
3c739b57
SP		 94 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 32, 32, 0),
95 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 28, 4, 0),
96 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64PFR0_GIC_SHIFT, 4, 0),
0710cfdb
SP		 97 S_ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_ASIMD_SHIFT, 4, ID_AA64PFR0_ASIMD_NI),
98 S_ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_FP_SHIFT, 4, ID_AA64PFR0_FP_NI),
3c739b57
SP		 99 /* Linux doesn't care about the EL3 */
100 ARM64_FTR_BITS(FTR_NONSTRICT, FTR_EXACT, ID_AA64PFR0_EL3_SHIFT, 4, 0),
101 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64PFR0_EL2_SHIFT, 4, 0),
102 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64PFR0_EL1_SHIFT, 4, ID_AA64PFR0_EL1_64BIT_ONLY),
103 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64PFR0_EL0_SHIFT, 4, ID_AA64PFR0_EL0_64BIT_ONLY),
104 ARM64_FTR_END,
105};
106
5e49d73c 107static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = {
3c739b57 108 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 32, 32, 0),
0710cfdb
SP		 109 S_ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN4_SHIFT, 4, ID_AA64MMFR0_TGRAN4_NI),
110 S_ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN64_SHIFT, 4, ID_AA64MMFR0_TGRAN64_NI),
3c739b57
SP		 111 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN16_SHIFT, 4, ID_AA64MMFR0_TGRAN16_NI),
112 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_BIGENDEL0_SHIFT, 4, 0),
113 /* Linux shouldn't care about secure memory */
114 ARM64_FTR_BITS(FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_SNSMEM_SHIFT, 4, 0),
115 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_BIGENDEL_SHIFT, 4, 0),
116 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_ASID_SHIFT, 4, 0),
117 /*
118 * Differing PARange is fine as long as all peripherals and memory are mapped
119 * within the minimum PARange of all CPUs
120 */
0710cfdb 121 ARM64_FTR_BITS(FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_PARANGE_SHIFT, 4, 0),
3c739b57
SP		 122 ARM64_FTR_END,
123};
124
5e49d73c 125static const struct arm64_ftr_bits ftr_id_aa64mmfr1[] = {
3c739b57
SP		 126 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 32, 32, 0),
127 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_PAN_SHIFT, 4, 0),
128 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_LOR_SHIFT, 4, 0),
129 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_HPD_SHIFT, 4, 0),
130 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_VHE_SHIFT, 4, 0),
131 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_VMIDBITS_SHIFT, 4, 0),
132 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_HADBS_SHIFT, 4, 0),
133 ARM64_FTR_END,
134};
135
5e49d73c 136static const struct arm64_ftr_bits ftr_id_aa64mmfr2[] = {
7d7b4ae4
KW		 137 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR2_LVA_SHIFT, 4, 0),
138 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR2_IESB_SHIFT, 4, 0),
139 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR2_LSM_SHIFT, 4, 0),
406e3087 140 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR2_UAO_SHIFT, 4, 0),
7d7b4ae4 141 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR2_CNP_SHIFT, 4, 0),
406e3087
JM		 142 ARM64_FTR_END,
143};
144
5e49d73c 145static const struct arm64_ftr_bits ftr_ctr[] = {
0710cfdb 146 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 31, 1, 1), /* RAO */
3c739b57 147 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 28, 3, 0),
0710cfdb
SP		 148 ARM64_FTR_BITS(FTR_STRICT, FTR_HIGHER_SAFE, 24, 4, 0), /* CWG */
149 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0), /* ERG */
150 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 1), /* DminLine */
3c739b57
SP		 151 /*
152 * Linux can handle differing I-cache policies. Userspace JITs will
ee7bc638
SP		 153 * make use of *minLine.
154 * If we have differing I-cache policies, report it as the weakest - AIVIVT.
3c739b57 155 */
ee7bc638 156 ARM64_FTR_BITS(FTR_NONSTRICT, FTR_EXACT, 14, 2, ICACHE_POLICY_AIVIVT), /* L1Ip */
3c739b57 157 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 4, 10, 0), /* RAZ */
0710cfdb 158 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), /* IminLine */
3c739b57
SP		 159 ARM64_FTR_END,
160};
161
675b0563
AB		 162struct arm64_ftr_reg arm64_ftr_reg_ctrel0 = {
163 .name = "SYS_CTR_EL0",
164 .ftr_bits = ftr_ctr
165};
166
5e49d73c 167static const struct arm64_ftr_bits ftr_id_mmfr0[] = {
0710cfdb 168 S_ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 28, 4, 0xf), /* InnerShr */
3c739b57
SP		 169 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 24, 4, 0), /* FCSE */
170 ARM64_FTR_BITS(FTR_NONSTRICT, FTR_LOWER_SAFE, 20, 4, 0), /* AuxReg */
171 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 16, 4, 0), /* TCM */
172 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 12, 4, 0), /* ShareLvl */
0710cfdb 173 S_ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 8, 4, 0xf), /* OuterShr */
3c739b57
SP		 174 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 4, 4, 0), /* PMSA */
175 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 4, 0), /* VMSA */
176 ARM64_FTR_END,
177};
178
5e49d73c 179static const struct arm64_ftr_bits ftr_id_aa64dfr0[] = {
3c739b57 180 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 32, 32, 0),
0710cfdb
SP		 181 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_CTX_CMPS_SHIFT, 4, 0),
182 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_WRPS_SHIFT, 4, 0),
183 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_BRPS_SHIFT, 4, 0),
184 S_ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64DFR0_PMUVER_SHIFT, 4, 0),
185 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64DFR0_TRACEVER_SHIFT, 4, 0),
186 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64DFR0_DEBUGVER_SHIFT, 4, 0x6),
3c739b57
SP		 187 ARM64_FTR_END,
188};
189
5e49d73c 190static const struct arm64_ftr_bits ftr_mvfr2[] = {
3c739b57
SP		 191 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 8, 24, 0), /* RAZ */
192 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 4, 4, 0), /* FPMisc */
193 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 4, 0), /* SIMDMisc */
194 ARM64_FTR_END,
195};
196
5e49d73c 197static const struct arm64_ftr_bits ftr_dczid[] = {
3c739b57
SP		 198 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 5, 27, 0), /* RAZ */
199 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 4, 1, 1), /* DZP */
200 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), /* BS */
201 ARM64_FTR_END,
202};
203
204
5e49d73c 205static const struct arm64_ftr_bits ftr_id_isar5[] = {
3c739b57
SP		 206 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_ISAR5_RDM_SHIFT, 4, 0),
207 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 20, 4, 0), /* RAZ */
208 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_ISAR5_CRC32_SHIFT, 4, 0),
209 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_ISAR5_SHA2_SHIFT, 4, 0),
210 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_ISAR5_SHA1_SHIFT, 4, 0),
211 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_ISAR5_AES_SHIFT, 4, 0),
212 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_ISAR5_SEVL_SHIFT, 4, 0),
213 ARM64_FTR_END,
214};
215
5e49d73c 216static const struct arm64_ftr_bits ftr_id_mmfr4[] = {
3c739b57
SP		 217 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 8, 24, 0), /* RAZ */
218 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 4, 4, 0), /* ac2 */
219 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 4, 0), /* RAZ */
220 ARM64_FTR_END,
221};
222
5e49d73c 223static const struct arm64_ftr_bits ftr_id_pfr0[] = {
3c739b57
SP		 224 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 16, 16, 0), /* RAZ */
225 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 12, 4, 0), /* State3 */
226 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 8, 4, 0), /* State2 */
227 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 4, 4, 0), /* State1 */
228 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 4, 0), /* State0 */
229 ARM64_FTR_END,
230};
231
5e49d73c 232static const struct arm64_ftr_bits ftr_id_dfr0[] = {
e5343503 233 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0),
0710cfdb 234 S_ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0xf), /* PerfMon */
e5343503
SP		 235 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0),
236 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0),
237 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),
238 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),
239 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),
240 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),
241 ARM64_FTR_END,
242};
243
3c739b57
SP		 244/*
245 * Common ftr bits for a 32bit register with all hidden, strict
246 * attributes, with 4bit feature fields and a default safe value of
247 * 0. Covers the following 32bit registers:
248 * id_isar[0-4], id_mmfr[1-3], id_pfr1, mvfr[0-1]
249 */
5e49d73c 250static const struct arm64_ftr_bits ftr_generic_32bits[] = {
3c739b57
SP		 251 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0),
252 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0),
253 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0),
254 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0),
255 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),
256 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),
257 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),
258 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),
259 ARM64_FTR_END,
260};
261
5e49d73c 262static const struct arm64_ftr_bits ftr_generic[] = {
3c739b57
SP		 263 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 64, 0),
264 ARM64_FTR_END,
265};
266
5e49d73c 267static const struct arm64_ftr_bits ftr_generic32[] = {
3c739b57
SP		 268 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 32, 0),
269 ARM64_FTR_END,
270};
271
5e49d73c 272static const struct arm64_ftr_bits ftr_aa64raz[] = {
3c739b57
SP		 273 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 64, 0),
274 ARM64_FTR_END,
275};
276
6f2b7eef
AB		 277#define ARM64_FTR_REG(id, table) { \
278 .sys_id = id, \
279 .reg = &(struct arm64_ftr_reg){ \
3c739b57
SP		 280 .name = #id, \
281 .ftr_bits = &((table)[0]), \
6f2b7eef 282 }}
3c739b57 283
6f2b7eef
AB		 284static const struct __ftr_reg_entry {
285 u32 sys_id;
286 struct arm64_ftr_reg *reg;
287} arm64_ftr_regs[] = {
3c739b57
SP		 288
289 /* Op1 = 0, CRn = 0, CRm = 1 */
290 ARM64_FTR_REG(SYS_ID_PFR0_EL1, ftr_id_pfr0),
291 ARM64_FTR_REG(SYS_ID_PFR1_EL1, ftr_generic_32bits),
e5343503 292 ARM64_FTR_REG(SYS_ID_DFR0_EL1, ftr_id_dfr0),
3c739b57
SP		 293 ARM64_FTR_REG(SYS_ID_MMFR0_EL1, ftr_id_mmfr0),
294 ARM64_FTR_REG(SYS_ID_MMFR1_EL1, ftr_generic_32bits),
295 ARM64_FTR_REG(SYS_ID_MMFR2_EL1, ftr_generic_32bits),
296 ARM64_FTR_REG(SYS_ID_MMFR3_EL1, ftr_generic_32bits),
297
298 /* Op1 = 0, CRn = 0, CRm = 2 */
299 ARM64_FTR_REG(SYS_ID_ISAR0_EL1, ftr_generic_32bits),
300 ARM64_FTR_REG(SYS_ID_ISAR1_EL1, ftr_generic_32bits),
301 ARM64_FTR_REG(SYS_ID_ISAR2_EL1, ftr_generic_32bits),
302 ARM64_FTR_REG(SYS_ID_ISAR3_EL1, ftr_generic_32bits),
303 ARM64_FTR_REG(SYS_ID_ISAR4_EL1, ftr_generic_32bits),
304 ARM64_FTR_REG(SYS_ID_ISAR5_EL1, ftr_id_isar5),
305 ARM64_FTR_REG(SYS_ID_MMFR4_EL1, ftr_id_mmfr4),
306
307 /* Op1 = 0, CRn = 0, CRm = 3 */
308 ARM64_FTR_REG(SYS_MVFR0_EL1, ftr_generic_32bits),
309 ARM64_FTR_REG(SYS_MVFR1_EL1, ftr_generic_32bits),
310 ARM64_FTR_REG(SYS_MVFR2_EL1, ftr_mvfr2),
311
312 /* Op1 = 0, CRn = 0, CRm = 4 */
313 ARM64_FTR_REG(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0),
314 ARM64_FTR_REG(SYS_ID_AA64PFR1_EL1, ftr_aa64raz),
315
316 /* Op1 = 0, CRn = 0, CRm = 5 */
317 ARM64_FTR_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0),
318 ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1, ftr_generic),
319
320 /* Op1 = 0, CRn = 0, CRm = 6 */
321 ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0),
322 ARM64_FTR_REG(SYS_ID_AA64ISAR1_EL1, ftr_aa64raz),
323
324 /* Op1 = 0, CRn = 0, CRm = 7 */
325 ARM64_FTR_REG(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0),
326 ARM64_FTR_REG(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1),
406e3087 327 ARM64_FTR_REG(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2),
3c739b57
SP		 328
329 /* Op1 = 3, CRn = 0, CRm = 0 */
675b0563 330 { SYS_CTR_EL0, &arm64_ftr_reg_ctrel0 },
3c739b57
SP		 331 ARM64_FTR_REG(SYS_DCZID_EL0, ftr_dczid),
332
333 /* Op1 = 3, CRn = 14, CRm = 0 */
334 ARM64_FTR_REG(SYS_CNTFRQ_EL0, ftr_generic32),
335};
336
337static int search_cmp_ftr_reg(const void *id, const void *regp)
338{
6f2b7eef 339 return (int)(unsigned long)id - (int)((const struct __ftr_reg_entry *)regp)->sys_id;
3c739b57
SP		 340}
341
342/*
343 * get_arm64_ftr_reg - Lookup a feature register entry using its
344 * sys_reg() encoding. With the array arm64_ftr_regs sorted in the
345 * ascending order of sys_id , we use binary search to find a matching
346 * entry.
347 *
348 * returns - Upon success, matching ftr_reg entry for id.
349 * - NULL on failure. It is upto the caller to decide
350 * the impact of a failure.
351 */
352static struct arm64_ftr_reg *get_arm64_ftr_reg(u32 sys_id)
353{
6f2b7eef
AB		 354 const struct __ftr_reg_entry *ret;
355
356 ret = bsearch((const void *)(unsigned long)sys_id,
3c739b57
SP		 357 arm64_ftr_regs,
358 ARRAY_SIZE(arm64_ftr_regs),
359 sizeof(arm64_ftr_regs[0]),
360 search_cmp_ftr_reg);
6f2b7eef
AB		 361 if (ret)
362 return ret->reg;
363 return NULL;
3c739b57
SP		 364}
365
5e49d73c
AB		 366static u64 arm64_ftr_set_value(const struct arm64_ftr_bits *ftrp, s64 reg,
367 s64 ftr_val)
3c739b57
SP		 368{
369 u64 mask = arm64_ftr_mask(ftrp);
370
371 reg &= ~mask;
372 reg |= (ftr_val << ftrp->shift) & mask;
373 return reg;
374}
375
5e49d73c
AB		 376static s64 arm64_ftr_safe_value(const struct arm64_ftr_bits *ftrp, s64 new,
377 s64 cur)
3c739b57
SP		 378{
379 s64 ret = 0;
380
381 switch (ftrp->type) {
382 case FTR_EXACT:
383 ret = ftrp->safe_val;
384 break;
385 case FTR_LOWER_SAFE:
386 ret = new < cur ? new : cur;
387 break;
388 case FTR_HIGHER_SAFE:
389 ret = new > cur ? new : cur;
390 break;
391 default:
392 BUG();
393 }
394
395 return ret;
396}
397
3c739b57
SP		 398static void __init sort_ftr_regs(void)
399{
6f2b7eef
AB		 400 int i;
401
402 /* Check that the array is sorted so that we can do the binary search */
403 for (i = 1; i < ARRAY_SIZE(arm64_ftr_regs); i++)
404 BUG_ON(arm64_ftr_regs[i].sys_id < arm64_ftr_regs[i - 1].sys_id);
3c739b57
SP		 405}
406
407/*
408 * Initialise the CPU feature register from Boot CPU values.
409 * Also initiliases the strict_mask for the register.
410 */
411static void __init init_cpu_ftr_reg(u32 sys_reg, u64 new)
412{
413 u64 val = 0;
414 u64 strict_mask = ~0x0ULL;
5e49d73c 415 const struct arm64_ftr_bits *ftrp;
3c739b57
SP		 416 struct arm64_ftr_reg *reg = get_arm64_ftr_reg(sys_reg);
417
418 BUG_ON(!reg);
419
420 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) {
421 s64 ftr_new = arm64_ftr_value(ftrp, new);
422
423 val = arm64_ftr_set_value(ftrp, val, ftr_new);
424 if (!ftrp->strict)
425 strict_mask &= ~arm64_ftr_mask(ftrp);
426 }
427 reg->sys_val = val;
428 reg->strict_mask = strict_mask;
429}
430
431void __init init_cpu_features(struct cpuinfo_arm64 *info)
432{
433 /* Before we start using the tables, make sure it is sorted */
434 sort_ftr_regs();
435
436 init_cpu_ftr_reg(SYS_CTR_EL0, info->reg_ctr);
437 init_cpu_ftr_reg(SYS_DCZID_EL0, info->reg_dczid);
438 init_cpu_ftr_reg(SYS_CNTFRQ_EL0, info->reg_cntfrq);
439 init_cpu_ftr_reg(SYS_ID_AA64DFR0_EL1, info->reg_id_aa64dfr0);
440 init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1, info->reg_id_aa64dfr1);
441 init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0);
442 init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1, info->reg_id_aa64isar1);
443 init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0);
444 init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1);
406e3087 445 init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1, info->reg_id_aa64mmfr2);
3c739b57
SP		 446 init_cpu_ftr_reg(SYS_ID_AA64PFR0_EL1, info->reg_id_aa64pfr0);
447 init_cpu_ftr_reg(SYS_ID_AA64PFR1_EL1, info->reg_id_aa64pfr1);
a6dc3cd7
SP		 448
449 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) {
450 init_cpu_ftr_reg(SYS_ID_DFR0_EL1, info->reg_id_dfr0);
451 init_cpu_ftr_reg(SYS_ID_ISAR0_EL1, info->reg_id_isar0);
452 init_cpu_ftr_reg(SYS_ID_ISAR1_EL1, info->reg_id_isar1);
453 init_cpu_ftr_reg(SYS_ID_ISAR2_EL1, info->reg_id_isar2);
454 init_cpu_ftr_reg(SYS_ID_ISAR3_EL1, info->reg_id_isar3);
455 init_cpu_ftr_reg(SYS_ID_ISAR4_EL1, info->reg_id_isar4);
456 init_cpu_ftr_reg(SYS_ID_ISAR5_EL1, info->reg_id_isar5);
457 init_cpu_ftr_reg(SYS_ID_MMFR0_EL1, info->reg_id_mmfr0);
458 init_cpu_ftr_reg(SYS_ID_MMFR1_EL1, info->reg_id_mmfr1);
459 init_cpu_ftr_reg(SYS_ID_MMFR2_EL1, info->reg_id_mmfr2);
460 init_cpu_ftr_reg(SYS_ID_MMFR3_EL1, info->reg_id_mmfr3);
461 init_cpu_ftr_reg(SYS_ID_PFR0_EL1, info->reg_id_pfr0);
462 init_cpu_ftr_reg(SYS_ID_PFR1_EL1, info->reg_id_pfr1);
463 init_cpu_ftr_reg(SYS_MVFR0_EL1, info->reg_mvfr0);
464 init_cpu_ftr_reg(SYS_MVFR1_EL1, info->reg_mvfr1);
465 init_cpu_ftr_reg(SYS_MVFR2_EL1, info->reg_mvfr2);
466 }
467
3c739b57
SP		 468}
469
3086d391 470static void update_cpu_ftr_reg(struct arm64_ftr_reg *reg, u64 new)
3c739b57 471{
5e49d73c 472 const struct arm64_ftr_bits *ftrp;
3c739b57
SP		 473
474 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) {
475 s64 ftr_cur = arm64_ftr_value(ftrp, reg->sys_val);
476 s64 ftr_new = arm64_ftr_value(ftrp, new);
477
478 if (ftr_cur == ftr_new)
479 continue;
480 /* Find a safe value */
481 ftr_new = arm64_ftr_safe_value(ftrp, ftr_new, ftr_cur);
482 reg->sys_val = arm64_ftr_set_value(ftrp, reg->sys_val, ftr_new);
483 }
484
485}
486
3086d391 487static int check_update_ftr_reg(u32 sys_id, int cpu, u64 val, u64 boot)
cdcf817b 488{
3086d391
SP		 489 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id);
490
491 BUG_ON(!regp);
492 update_cpu_ftr_reg(regp, val);
493 if ((boot & regp->strict_mask) == (val & regp->strict_mask))
494 return 0;
495 pr_warn("SANITY CHECK: Unexpected variation in %s. Boot CPU: %#016llx, CPU%d: %#016llx\n",
496 regp->name, boot, cpu, val);
497 return 1;
498}
499
500/*
501 * Update system wide CPU feature registers with the values from a
502 * non-boot CPU. Also performs SANITY checks to make sure that there
503 * aren't any insane variations from that of the boot CPU.
504 */
505void update_cpu_features(int cpu,
506 struct cpuinfo_arm64 *info,
507 struct cpuinfo_arm64 *boot)
508{
509 int taint = 0;
510
511 /*
512 * The kernel can handle differing I-cache policies, but otherwise
513 * caches should look identical. Userspace JITs will make use of
514 * *minLine.
515 */
516 taint |= check_update_ftr_reg(SYS_CTR_EL0, cpu,
517 info->reg_ctr, boot->reg_ctr);
518
519 /*
520 * Userspace may perform DC ZVA instructions. Mismatched block sizes
521 * could result in too much or too little memory being zeroed if a
522 * process is preempted and migrated between CPUs.
523 */
524 taint |= check_update_ftr_reg(SYS_DCZID_EL0, cpu,
525 info->reg_dczid, boot->reg_dczid);
526
527 /* If different, timekeeping will be broken (especially with KVM) */
528 taint |= check_update_ftr_reg(SYS_CNTFRQ_EL0, cpu,
529 info->reg_cntfrq, boot->reg_cntfrq);
530
531 /*
532 * The kernel uses self-hosted debug features and expects CPUs to
533 * support identical debug features. We presently need CTX_CMPs, WRPs,
534 * and BRPs to be identical.
535 * ID_AA64DFR1 is currently RES0.
536 */
537 taint |= check_update_ftr_reg(SYS_ID_AA64DFR0_EL1, cpu,
538 info->reg_id_aa64dfr0, boot->reg_id_aa64dfr0);
539 taint |= check_update_ftr_reg(SYS_ID_AA64DFR1_EL1, cpu,
540 info->reg_id_aa64dfr1, boot->reg_id_aa64dfr1);
541 /*
542 * Even in big.LITTLE, processors should be identical instruction-set
543 * wise.
544 */
545 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR0_EL1, cpu,
546 info->reg_id_aa64isar0, boot->reg_id_aa64isar0);
547 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR1_EL1, cpu,
548 info->reg_id_aa64isar1, boot->reg_id_aa64isar1);
549
550 /*
551 * Differing PARange support is fine as long as all peripherals and
552 * memory are mapped within the minimum PARange of all CPUs.
553 * Linux should not care about secure memory.
554 */
555 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR0_EL1, cpu,
556 info->reg_id_aa64mmfr0, boot->reg_id_aa64mmfr0);
557 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR1_EL1, cpu,
558 info->reg_id_aa64mmfr1, boot->reg_id_aa64mmfr1);
406e3087
JM		 559 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR2_EL1, cpu,
560 info->reg_id_aa64mmfr2, boot->reg_id_aa64mmfr2);
3086d391
SP		 561
562 /*
563 * EL3 is not our concern.
564 * ID_AA64PFR1 is currently RES0.
565 */
566 taint |= check_update_ftr_reg(SYS_ID_AA64PFR0_EL1, cpu,
567 info->reg_id_aa64pfr0, boot->reg_id_aa64pfr0);
568 taint |= check_update_ftr_reg(SYS_ID_AA64PFR1_EL1, cpu,
569 info->reg_id_aa64pfr1, boot->reg_id_aa64pfr1);
570
571 /*
a6dc3cd7
SP		 572 * If we have AArch32, we care about 32-bit features for compat.
573 * If the system doesn't support AArch32, don't update them.
3086d391 574 */
a6dc3cd7
SP		 575 if (id_aa64pfr0_32bit_el0(read_system_reg(SYS_ID_AA64PFR0_EL1)) &&
576 id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) {
577
578 taint |= check_update_ftr_reg(SYS_ID_DFR0_EL1, cpu,
3086d391 579 info->reg_id_dfr0, boot->reg_id_dfr0);
a6dc3cd7 580 taint |= check_update_ftr_reg(SYS_ID_ISAR0_EL1, cpu,
3086d391 581 info->reg_id_isar0, boot->reg_id_isar0);
a6dc3cd7 582 taint |= check_update_ftr_reg(SYS_ID_ISAR1_EL1, cpu,
3086d391 583 info->reg_id_isar1, boot->reg_id_isar1);
a6dc3cd7 584 taint |= check_update_ftr_reg(SYS_ID_ISAR2_EL1, cpu,
3086d391 585 info->reg_id_isar2, boot->reg_id_isar2);
a6dc3cd7 586 taint |= check_update_ftr_reg(SYS_ID_ISAR3_EL1, cpu,
3086d391 587 info->reg_id_isar3, boot->reg_id_isar3);
a6dc3cd7 588 taint |= check_update_ftr_reg(SYS_ID_ISAR4_EL1, cpu,
3086d391 589 info->reg_id_isar4, boot->reg_id_isar4);
a6dc3cd7 590 taint |= check_update_ftr_reg(SYS_ID_ISAR5_EL1, cpu,
3086d391
SP		 591 info->reg_id_isar5, boot->reg_id_isar5);
592
a6dc3cd7
SP		 593 /*
594 * Regardless of the value of the AuxReg field, the AIFSR, ADFSR, and
595 * ACTLR formats could differ across CPUs and therefore would have to
596 * be trapped for virtualization anyway.
597 */
598 taint |= check_update_ftr_reg(SYS_ID_MMFR0_EL1, cpu,
3086d391 599 info->reg_id_mmfr0, boot->reg_id_mmfr0);
a6dc3cd7 600 taint |= check_update_ftr_reg(SYS_ID_MMFR1_EL1, cpu,
3086d391 601 info->reg_id_mmfr1, boot->reg_id_mmfr1);
a6dc3cd7 602 taint |= check_update_ftr_reg(SYS_ID_MMFR2_EL1, cpu,
3086d391 603 info->reg_id_mmfr2, boot->reg_id_mmfr2);
a6dc3cd7 604 taint |= check_update_ftr_reg(SYS_ID_MMFR3_EL1, cpu,
3086d391 605 info->reg_id_mmfr3, boot->reg_id_mmfr3);
a6dc3cd7 606 taint |= check_update_ftr_reg(SYS_ID_PFR0_EL1, cpu,
3086d391 607 info->reg_id_pfr0, boot->reg_id_pfr0);
a6dc3cd7 608 taint |= check_update_ftr_reg(SYS_ID_PFR1_EL1, cpu,
3086d391 609 info->reg_id_pfr1, boot->reg_id_pfr1);
a6dc3cd7 610 taint |= check_update_ftr_reg(SYS_MVFR0_EL1, cpu,
3086d391 611 info->reg_mvfr0, boot->reg_mvfr0);
a6dc3cd7 612 taint |= check_update_ftr_reg(SYS_MVFR1_EL1, cpu,
3086d391 613 info->reg_mvfr1, boot->reg_mvfr1);
a6dc3cd7 614 taint |= check_update_ftr_reg(SYS_MVFR2_EL1, cpu,
3086d391 615 info->reg_mvfr2, boot->reg_mvfr2);
a6dc3cd7 616 }
3086d391
SP		 617
618 /*
619 * Mismatched CPU features are a recipe for disaster. Don't even
620 * pretend to support them.
621 */
622 WARN_TAINT_ONCE(taint, TAINT_CPU_OUT_OF_SPEC,
623 "Unsupported CPU feature variation.\n");
cdcf817b
SP		 624}
625
b3f15378
SP		 626u64 read_system_reg(u32 id)
627{
628 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(id);
629
630 /* We shouldn't get a request for an unsupported register */
631 BUG_ON(!regp);
632 return regp->sys_val;
633}
359b7064 634
92406f0c
SP		 635/*
636 * __raw_read_system_reg() - Used by a STARTING cpu before cpuinfo is populated.
637 * Read the system register on the current CPU
638 */
639static u64 __raw_read_system_reg(u32 sys_id)
640{
641 switch (sys_id) {
642 case SYS_ID_PFR0_EL1: return read_cpuid(ID_PFR0_EL1);
643 case SYS_ID_PFR1_EL1: return read_cpuid(ID_PFR1_EL1);
644 case SYS_ID_DFR0_EL1: return read_cpuid(ID_DFR0_EL1);
645 case SYS_ID_MMFR0_EL1: return read_cpuid(ID_MMFR0_EL1);
646 case SYS_ID_MMFR1_EL1: return read_cpuid(ID_MMFR1_EL1);
647 case SYS_ID_MMFR2_EL1: return read_cpuid(ID_MMFR2_EL1);
648 case SYS_ID_MMFR3_EL1: return read_cpuid(ID_MMFR3_EL1);
649 case SYS_ID_ISAR0_EL1: return read_cpuid(ID_ISAR0_EL1);
650 case SYS_ID_ISAR1_EL1: return read_cpuid(ID_ISAR1_EL1);
651 case SYS_ID_ISAR2_EL1: return read_cpuid(ID_ISAR2_EL1);
652 case SYS_ID_ISAR3_EL1: return read_cpuid(ID_ISAR3_EL1);
653 case SYS_ID_ISAR4_EL1: return read_cpuid(ID_ISAR4_EL1);
654 case SYS_ID_ISAR5_EL1: return read_cpuid(ID_ISAR4_EL1);
655 case SYS_MVFR0_EL1: return read_cpuid(MVFR0_EL1);
656 case SYS_MVFR1_EL1: return read_cpuid(MVFR1_EL1);
657 case SYS_MVFR2_EL1: return read_cpuid(MVFR2_EL1);
658
659 case SYS_ID_AA64PFR0_EL1: return read_cpuid(ID_AA64PFR0_EL1);
660 case SYS_ID_AA64PFR1_EL1: return read_cpuid(ID_AA64PFR0_EL1);
661 case SYS_ID_AA64DFR0_EL1: return read_cpuid(ID_AA64DFR0_EL1);
662 case SYS_ID_AA64DFR1_EL1: return read_cpuid(ID_AA64DFR0_EL1);
663 case SYS_ID_AA64MMFR0_EL1: return read_cpuid(ID_AA64MMFR0_EL1);
664 case SYS_ID_AA64MMFR1_EL1: return read_cpuid(ID_AA64MMFR1_EL1);
665 case SYS_ID_AA64MMFR2_EL1: return read_cpuid(ID_AA64MMFR2_EL1);
666 case SYS_ID_AA64ISAR0_EL1: return read_cpuid(ID_AA64ISAR0_EL1);
667 case SYS_ID_AA64ISAR1_EL1: return read_cpuid(ID_AA64ISAR1_EL1);
668
669 case SYS_CNTFRQ_EL0: return read_cpuid(CNTFRQ_EL0);
670 case SYS_CTR_EL0: return read_cpuid(CTR_EL0);
671 case SYS_DCZID_EL0: return read_cpuid(DCZID_EL0);
672 default:
673 BUG();
674 return 0;
675 }
676}
677
963fcd40
MZ		 678#include <linux/irqchip/arm-gic-v3.h>
679
18ffa046
JM		 680static bool
681feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry)
682{
28c5dcb2 683 int val = cpuid_feature_extract_field(reg, entry->field_pos, entry->sign);
18ffa046
JM		 684
685 return val >= entry->min_field_value;
686}
687
da8d02d1 688static bool
92406f0c 689has_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope)
da8d02d1
SP		 690{
691 u64 val;
94a9e04a 692
92406f0c
SP		 693 WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible());
694 if (scope == SCOPE_SYSTEM)
695 val = read_system_reg(entry->sys_reg);
696 else
697 val = __raw_read_system_reg(entry->sys_reg);
698
da8d02d1
SP		 699 return feature_matches(val, entry);
700}
338d4f49 701
92406f0c 702static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry, int scope)
963fcd40
MZ		 703{
704 bool has_sre;
705
92406f0c 706 if (!has_cpuid_feature(entry, scope))
963fcd40
MZ		 707 return false;
708
709 has_sre = gic_enable_sre();
710 if (!has_sre)
711 pr_warn_once("%s present but disabled by higher exception level\n",
712 entry->desc);
713
714 return has_sre;
715}
716
92406f0c 717static bool has_no_hw_prefetch(const struct arm64_cpu_capabilities *entry, int __unused)
d5370f75
WD		 718{
719 u32 midr = read_cpuid_id();
720 u32 rv_min, rv_max;
721
722 /* Cavium ThunderX pass 1.x and 2.x */
723 rv_min = 0;
724 rv_max = (1 << MIDR_VARIANT_SHIFT) | MIDR_REVISION_MASK;
725
726 return MIDR_IS_CPU_MODEL_RANGE(midr, MIDR_THUNDERX, rv_min, rv_max);
727}
728
92406f0c 729static bool runs_at_el2(const struct arm64_cpu_capabilities *entry, int __unused)
d88701be
MZ		 730{
731 return is_kernel_in_hyp_mode();
732}
733
d1745910
MZ		 734static bool hyp_offset_low(const struct arm64_cpu_capabilities *entry,
735 int __unused)
736{
737 phys_addr_t idmap_addr = virt_to_phys(__hyp_idmap_text_start);
738
739 /*
740 * Activate the lower HYP offset only if:
741 * - the idmap doesn't clash with it,
742 * - the kernel is not running at EL2.
743 */
744 return idmap_addr > GENMASK(VA_BITS - 2, 0) && !is_kernel_in_hyp_mode();
745}
746
359b7064 747static const struct arm64_cpu_capabilities arm64_features[] = {
94a9e04a
MZ		 748 {
749 .desc = "GIC system register CPU interface",
750 .capability = ARM64_HAS_SYSREG_GIC_CPUIF,
92406f0c 751 .def_scope = SCOPE_SYSTEM,
963fcd40 752 .matches = has_useable_gicv3_cpuif,
da8d02d1
SP		 753 .sys_reg = SYS_ID_AA64PFR0_EL1,
754 .field_pos = ID_AA64PFR0_GIC_SHIFT,
ff96f7bc 755 .sign = FTR_UNSIGNED,
18ffa046 756 .min_field_value = 1,
94a9e04a 757 },
338d4f49
JM		 758#ifdef CONFIG_ARM64_PAN
759 {
760 .desc = "Privileged Access Never",
761 .capability = ARM64_HAS_PAN,
92406f0c 762 .def_scope = SCOPE_SYSTEM,
da8d02d1
SP		 763 .matches = has_cpuid_feature,
764 .sys_reg = SYS_ID_AA64MMFR1_EL1,
765 .field_pos = ID_AA64MMFR1_PAN_SHIFT,
ff96f7bc 766 .sign = FTR_UNSIGNED,
338d4f49
JM		 767 .min_field_value = 1,
768 .enable = cpu_enable_pan,
769 },
770#endif /* CONFIG_ARM64_PAN */
2e94da13
WD		 771#if defined(CONFIG_AS_LSE) && defined(CONFIG_ARM64_LSE_ATOMICS)
772 {
773 .desc = "LSE atomic instructions",
774 .capability = ARM64_HAS_LSE_ATOMICS,
92406f0c 775 .def_scope = SCOPE_SYSTEM,
da8d02d1
SP		 776 .matches = has_cpuid_feature,
777 .sys_reg = SYS_ID_AA64ISAR0_EL1,
778 .field_pos = ID_AA64ISAR0_ATOMICS_SHIFT,
ff96f7bc 779 .sign = FTR_UNSIGNED,
2e94da13
WD		 780 .min_field_value = 2,
781 },
782#endif /* CONFIG_AS_LSE && CONFIG_ARM64_LSE_ATOMICS */
d5370f75
WD		 783 {
784 .desc = "Software prefetching using PRFM",
785 .capability = ARM64_HAS_NO_HW_PREFETCH,
92406f0c 786 .def_scope = SCOPE_SYSTEM,
d5370f75
WD		 787 .matches = has_no_hw_prefetch,
788 },
57f4959b
JM		 789#ifdef CONFIG_ARM64_UAO
790 {
791 .desc = "User Access Override",
792 .capability = ARM64_HAS_UAO,
92406f0c 793 .def_scope = SCOPE_SYSTEM,
57f4959b
JM		 794 .matches = has_cpuid_feature,
795 .sys_reg = SYS_ID_AA64MMFR2_EL1,
796 .field_pos = ID_AA64MMFR2_UAO_SHIFT,
797 .min_field_value = 1,
798 .enable = cpu_enable_uao,
799 },
800#endif /* CONFIG_ARM64_UAO */
70544196
JM		 801#ifdef CONFIG_ARM64_PAN
802 {
803 .capability = ARM64_ALT_PAN_NOT_UAO,
92406f0c 804 .def_scope = SCOPE_SYSTEM,
70544196
JM		 805 .matches = cpufeature_pan_not_uao,
806 },
807#endif /* CONFIG_ARM64_PAN */
d88701be
MZ		 808 {
809 .desc = "Virtualization Host Extensions",
810 .capability = ARM64_HAS_VIRT_HOST_EXTN,
92406f0c 811 .def_scope = SCOPE_SYSTEM,
d88701be
MZ		 812 .matches = runs_at_el2,
813 },
042446a3
SP		 814 {
815 .desc = "32-bit EL0 Support",
816 .capability = ARM64_HAS_32BIT_EL0,
92406f0c 817 .def_scope = SCOPE_SYSTEM,
042446a3
SP		 818 .matches = has_cpuid_feature,
819 .sys_reg = SYS_ID_AA64PFR0_EL1,
820 .sign = FTR_UNSIGNED,
821 .field_pos = ID_AA64PFR0_EL0_SHIFT,
822 .min_field_value = ID_AA64PFR0_EL0_32BIT_64BIT,
823 },
d1745910
MZ		 824 {
825 .desc = "Reduced HYP mapping offset",
826 .capability = ARM64_HYP_OFFSET_LOW,
827 .def_scope = SCOPE_SYSTEM,
828 .matches = hyp_offset_low,
829 },
359b7064
MZ		 830 {},
831};
832
ff96f7bc 833#define HWCAP_CAP(reg, field, s, min_value, type, cap) \
37b01d53
SP		 834 { \
835 .desc = #cap, \
92406f0c 836 .def_scope = SCOPE_SYSTEM, \
37b01d53
SP		 837 .matches = has_cpuid_feature, \
838 .sys_reg = reg, \
839 .field_pos = field, \
ff96f7bc 840 .sign = s, \
37b01d53
SP		 841 .min_field_value = min_value, \
842 .hwcap_type = type, \
843 .hwcap = cap, \
844 }
845
f3efb675 846static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = {
ff96f7bc
SP		 847 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, HWCAP_PMULL),
848 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_AES),
849 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SHA1),
850 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SHA2),
851 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_CRC32),
852 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_ATOMICS_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, HWCAP_ATOMICS),
853 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, HWCAP_FP),
bf500618 854 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, HWCAP_FPHP),
ff96f7bc 855 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, HWCAP_ASIMD),
bf500618 856 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, HWCAP_ASIMDHP),
75283501
SP		 857 {},
858};
859
860static const struct arm64_cpu_capabilities compat_elf_hwcaps[] = {
37b01d53 861#ifdef CONFIG_COMPAT
ff96f7bc
SP		 862 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_PMULL),
863 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_AES),
864 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA1),
865 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA2),
866 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_CRC32),
37b01d53
SP		 867#endif
868 {},
869};
870
f3efb675 871static void __init cap_set_elf_hwcap(const struct arm64_cpu_capabilities *cap)
37b01d53
SP		 872{
873 switch (cap->hwcap_type) {
874 case CAP_HWCAP:
875 elf_hwcap |= cap->hwcap;
876 break;
877#ifdef CONFIG_COMPAT
878 case CAP_COMPAT_HWCAP:
879 compat_elf_hwcap |= (u32)cap->hwcap;
880 break;
881 case CAP_COMPAT_HWCAP2:
882 compat_elf_hwcap2 |= (u32)cap->hwcap;
883 break;
884#endif
885 default:
886 WARN_ON(1);
887 break;
888 }
889}
890
891/* Check if we have a particular HWCAP enabled */
f3efb675 892static bool cpus_have_elf_hwcap(const struct arm64_cpu_capabilities *cap)
37b01d53
SP		 893{
894 bool rc;
895
896 switch (cap->hwcap_type) {
897 case CAP_HWCAP:
898 rc = (elf_hwcap & cap->hwcap) != 0;
899 break;
900#ifdef CONFIG_COMPAT
901 case CAP_COMPAT_HWCAP:
902 rc = (compat_elf_hwcap & (u32)cap->hwcap) != 0;
903 break;
904 case CAP_COMPAT_HWCAP2:
905 rc = (compat_elf_hwcap2 & (u32)cap->hwcap) != 0;
906 break;
907#endif
908 default:
909 WARN_ON(1);
910 rc = false;
911 }
912
913 return rc;
914}
915
75283501 916static void __init setup_elf_hwcaps(const struct arm64_cpu_capabilities *hwcaps)
37b01d53 917{
75283501 918 for (; hwcaps->matches; hwcaps++)
92406f0c 919 if (hwcaps->matches(hwcaps, hwcaps->def_scope))
75283501 920 cap_set_elf_hwcap(hwcaps);
37b01d53
SP		 921}
922
ce8b602c 923void update_cpu_capabilities(const struct arm64_cpu_capabilities *caps,
359b7064
MZ		 924 const char *info)
925{
75283501 926 for (; caps->matches; caps++) {
92406f0c 927 if (!caps->matches(caps, caps->def_scope))
359b7064
MZ		 928 continue;
929
75283501
SP		 930 if (!cpus_have_cap(caps->capability) && caps->desc)
931 pr_info("%s %s\n", info, caps->desc);
932 cpus_set_cap(caps->capability);
359b7064 933 }
ce8b602c
SP		 934}
935
936/*
dbb4e152
SP		 937 * Run through the enabled capabilities and enable() it on all active
938 * CPUs
ce8b602c 939 */
8e231852 940void __init enable_cpu_capabilities(const struct arm64_cpu_capabilities *caps)
ce8b602c 941{
75283501
SP		 942 for (; caps->matches; caps++)
943 if (caps->enable && cpus_have_cap(caps->capability))
944 on_each_cpu(caps->enable, NULL, true);
dbb4e152
SP		 945}
946
dbb4e152
SP		 947/*
948 * Flag to indicate if we have computed the system wide
949 * capabilities based on the boot time active CPUs. This
950 * will be used to determine if a new booting CPU should
951 * go through the verification process to make sure that it
952 * supports the system capabilities, without using a hotplug
953 * notifier.
954 */
955static bool sys_caps_initialised;
956
957static inline void set_sys_caps_initialised(void)
958{
959 sys_caps_initialised = true;
960}
961
962/*
13f417f3
SP		 963 * Check for CPU features that are used in early boot
964 * based on the Boot CPU value.
dbb4e152 965 */
13f417f3 966static void check_early_cpu_features(void)
dbb4e152 967{
ac1ad20f 968 verify_cpu_run_el();
13f417f3 969 verify_cpu_asid_bits();
dbb4e152 970}
1c076303 971
75283501
SP		 972static void
973verify_local_elf_hwcaps(const struct arm64_cpu_capabilities *caps)
974{
975
92406f0c
SP		 976 for (; caps->matches; caps++)
977 if (cpus_have_elf_hwcap(caps) && !caps->matches(caps, SCOPE_LOCAL_CPU)) {
75283501
SP		 978 pr_crit("CPU%d: missing HWCAP: %s\n",
979 smp_processor_id(), caps->desc);
980 cpu_die_early();
981 }
75283501
SP		 982}
983
984static void
985verify_local_cpu_features(const struct arm64_cpu_capabilities *caps)
986{
987 for (; caps->matches; caps++) {
92406f0c 988 if (!cpus_have_cap(caps->capability))
75283501
SP		 989 continue;
990 /*
991 * If the new CPU misses an advertised feature, we cannot proceed
992 * further, park the cpu.
993 */
92406f0c 994 if (!caps->matches(caps, SCOPE_LOCAL_CPU)) {
75283501
SP		 995 pr_crit("CPU%d: missing feature: %s\n",
996 smp_processor_id(), caps->desc);
997 cpu_die_early();
998 }
999 if (caps->enable)
1000 caps->enable(NULL);
1001 }
1002}
1003
dbb4e152
SP		 1004/*
1005 * Run through the enabled system capabilities and enable() it on this CPU.
1006 * The capabilities were decided based on the available CPUs at the boot time.
1007 * Any new CPU should match the system wide status of the capability. If the
1008 * new CPU doesn't have a capability which the system now has enabled, we
1009 * cannot do anything to fix it up and could cause unexpected failures. So
1010 * we park the CPU.
1011 */
c47a1900 1012static void verify_local_cpu_capabilities(void)
dbb4e152 1013{
c47a1900
SP		 1014 verify_local_cpu_errata_workarounds();
1015 verify_local_cpu_features(arm64_features);
1016 verify_local_elf_hwcaps(arm64_elf_hwcaps);
1017 if (system_supports_32bit_el0())
1018 verify_local_elf_hwcaps(compat_elf_hwcaps);
1019}
dbb4e152 1020
c47a1900
SP		 1021void check_local_cpu_capabilities(void)
1022{
1023 /*
1024 * All secondary CPUs should conform to the early CPU features
1025 * in use by the kernel based on boot CPU.
1026 */
13f417f3
SP		 1027 check_early_cpu_features();
1028
dbb4e152 1029 /*
c47a1900
SP		 1030 * If we haven't finalised the system capabilities, this CPU gets
1031 * a chance to update the errata work arounds.
1032 * Otherwise, this CPU should verify that it has all the system
1033 * advertised capabilities.
dbb4e152
SP		 1034 */
1035 if (!sys_caps_initialised)
c47a1900
SP		 1036 update_cpu_errata_workarounds();
1037 else
1038 verify_local_cpu_capabilities();
359b7064
MZ		 1039}
1040
a7c61a34 1041static void __init setup_feature_capabilities(void)
359b7064 1042{
ce8b602c
SP		 1043 update_cpu_capabilities(arm64_features, "detected feature:");
1044 enable_cpu_capabilities(arm64_features);
359b7064
MZ		 1045}
1046
e3661b12
MZ		 1047/*
1048 * Check if the current CPU has a given feature capability.
1049 * Should be called from non-preemptible context.
1050 */
1051bool this_cpu_has_cap(unsigned int cap)
1052{
1053 const struct arm64_cpu_capabilities *caps;
1054
1055 if (WARN_ON(preemptible()))
1056 return false;
1057
1058 for (caps = arm64_features; caps->desc; caps++)
1059 if (caps->capability == cap && caps->matches)
1060 return caps->matches(caps, SCOPE_LOCAL_CPU);
1061
1062 return false;
1063}
1064
9cdf8ec4 1065void __init setup_cpu_features(void)
359b7064 1066{
9cdf8ec4
SP		 1067 u32 cwg;
1068 int cls;
1069
dbb4e152
SP		 1070 /* Set the CPU feature capabilies */
1071 setup_feature_capabilities();
8e231852 1072 enable_errata_workarounds();
75283501 1073 setup_elf_hwcaps(arm64_elf_hwcaps);
643d703d
SP		 1074
1075 if (system_supports_32bit_el0())
1076 setup_elf_hwcaps(compat_elf_hwcaps);
dbb4e152
SP		 1077
1078 /* Advertise that we have computed the system capabilities */
1079 set_sys_caps_initialised();
1080
9cdf8ec4
SP		 1081 /*
1082 * Check for sane CTR_EL0.CWG value.
1083 */
1084 cwg = cache_type_cwg();
1085 cls = cache_line_size();
1086 if (!cwg)
1087 pr_warn("No Cache Writeback Granule information, assuming cache line size %d\n",
1088 cls);
1089 if (L1_CACHE_BYTES < cls)
1090 pr_warn("L1_CACHE_BYTES smaller than the Cache Writeback Granule (%d < %d)\n",
1091 L1_CACHE_BYTES, cls);
359b7064 1092}
70544196
JM		 1093
1094static bool __maybe_unused
92406f0c 1095cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry, int __unused)
70544196
JM		 1096{
1097 return (cpus_have_cap(ARM64_HAS_PAN) && !cpus_have_cap(ARM64_HAS_UAO));
1098}
Linux kernel - Deliverables
This page took 0.159725 seconds and 5 git commands to generate.